arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6dl-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 i2c3 = &i2c4;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         next-level-cache = <&L2>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 996000  1250000
  32                                 792000  1175000
  33                                 396000  1150000
  34                         >;
  35                         fsl,soc-operating-points = <
  36                                 /* ARM kHz  SOC-PU uV */
  37                                 996000  1175000
  38                                 792000  1175000
  39                                 396000  1175000
  40                         >;
  41                         clock-latency = <61036>; /* two CLK32 periods */
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                 };
  60         };
  61
  62         soc {
  63                 ocram: sram@900000 {
  64                         compatible = "mmio-sram";
  65                         reg = <0x00900000 0x20000>;
  66                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  67                 };
  68
  69                 aips1: aips-bus@2000000 {
  70                         iomuxc: iomuxc@20e0000 {
  71                                 compatible = "fsl,imx6dl-iomuxc";
  72                         };
  73
  74                         pxp: pxp@20f0000 {
  75                                 reg = <0x020f0000 0x4000>;
  76                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
  77                         };
  78
  79                         epdc: epdc@20f4000 {
  80                                 reg = <0x020f4000 0x4000>;
  81                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
  82                         };
  83                 };
  84
  85                 aips2: aips-bus@2100000 {
  86                         i2c4: i2c@21f8000 {
  87                                 #address-cells = <1>;
  88                                 #size-cells = <0>;
  89                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  90                                 reg = <0x021f8000 0x4000>;
  91                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  92                                 clocks = <&clks IMX6DL_CLK_I2C4>;
  93                                 status = "disabled";
  94                         };
  95                 };
  96         };
  97
  98         capture-subsystem {
  99                 compatible = "fsl,imx-capture-subsystem";
 100                 ports = <&ipu1_csi0>, <&ipu1_csi1>;
 101         };
 102
 103         display-subsystem {
 104                 compatible = "fsl,imx-display-subsystem";
 105                 ports = <&ipu1_di0>, <&ipu1_di1>;
 106         };
 107 };
 108
 109 &gpio1 {
 110         gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
 111                       <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
 112                       <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
 113                       <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
 114                       <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
 115                       <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
 116                       <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
 117 };
 118
 119 &gpio2 {
 120         gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
 121                       <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
 122                       <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
 123                       <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
 124                       <&iomuxc 28 113 4>;
 125 };
 126
 127 &gpio3 {
 128         gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
 129                       <&iomuxc 16 81 16>;
 130 };
 131
 132 &gpio4 {
 133         gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
 134                       <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
 135                       <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
 136                       <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
 137                       <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
 138 };
 139
 140 &gpio5 {
 141         gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
 142                       <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
 143                       <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
 144                       <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
 145 };
 146
 147 &gpio6 {
 148         gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
 149                       <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
 150                       <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
 151                       <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
 152                       <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
 153                       <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
 154 };
 155
 156 &gpio7 {
 157         gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
 158                       <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
 159                       <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
 160 };
 161
 162 &gpr {
 163         ipu1_csi0_mux {
 164                 compatible = "video-mux";
 165                 mux-controls = <&mux 0>;
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168
 169                 port@0 {
 170                         reg = <0>;
 171
 172                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 173                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 174                         };
 175                 };
 176
 177                 port@1 {
 178                         reg = <1>;
 179
 180                         ipu1_csi0_mux_from_mipi_vc1: endpoint {
 181                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
 182                         };
 183                 };
 184
 185                 port@2 {
 186                         reg = <2>;
 187
 188                         ipu1_csi0_mux_from_mipi_vc2: endpoint {
 189                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
 190                         };
 191                 };
 192
 193                 port@3 {
 194                         reg = <3>;
 195
 196                         ipu1_csi0_mux_from_mipi_vc3: endpoint {
 197                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
 198                         };
 199                 };
 200
 201                 port@4 {
 202                         reg = <4>;
 203
 204                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 205                         };
 206                 };
 207
 208                 port@5 {
 209                         reg = <5>;
 210
 211                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 212                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 213                         };
 214                 };
 215         };
 216
 217         ipu1_csi1_mux {
 218                 compatible = "video-mux";
 219                 mux-controls = <&mux 1>;
 220                 #address-cells = <1>;
 221                 #size-cells = <0>;
 222
 223                 port@0 {
 224                         reg = <0>;
 225
 226                         ipu1_csi1_mux_from_mipi_vc0: endpoint {
 227                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
 228                         };
 229                 };
 230
 231                 port@1 {
 232                         reg = <1>;
 233
 234                         ipu1_csi1_mux_from_mipi_vc1: endpoint {
 235                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
 236                         };
 237                 };
 238
 239                 port@2 {
 240                         reg = <2>;
 241
 242                         ipu1_csi1_mux_from_mipi_vc2: endpoint {
 243                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
 244                         };
 245                 };
 246
 247                 port@3 {
 248                         reg = <3>;
 249
 250                         ipu1_csi1_mux_from_mipi_vc3: endpoint {
 251                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
 252                         };
 253                 };
 254
 255                 port@4 {
 256                         reg = <4>;
 257
 258                         ipu1_csi1_mux_from_parallel_sensor: endpoint {
 259                         };
 260                 };
 261
 262                 port@5 {
 263                         reg = <5>;
 264
 265                         ipu1_csi1_mux_to_ipu1_csi1: endpoint {
 266                                 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
 267                         };
 268                 };
 269         };
 270 };
 271
 272 &gpt {
 273         compatible = "fsl,imx6dl-gpt";
 274 };
 275
 276 &hdmi {
 277         compatible = "fsl,imx6dl-hdmi";
 278 };
 279
 280 &ipu1_csi1 {
 281         ipu1_csi1_from_ipu1_csi1_mux: endpoint {
 282                 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
 283         };
 284 };
 285
 286 &ldb {
 287         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 288                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 289                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 290         clock-names = "di0_pll", "di1_pll",
 291                       "di0_sel", "di1_sel",
 292                       "di0", "di1";
 293 };
 294
 295 &mipi_csi {
 296         port@1 {
 297                 reg = <1>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300
 301                 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
 302                         reg = <0>;
 303                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 304                 };
 305
 306                 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
 307                         reg = <1>;
 308                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
 309                 };
 310         };
 311
 312         port@2 {
 313                 reg = <2>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316
 317                 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
 318                         reg = <0>;
 319                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
 320                 };
 321
 322                 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
 323                         reg = <1>;
 324                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
 325                 };
 326         };
 327
 328         port@3 {
 329                 reg = <3>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332
 333                 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
 334                         reg = <0>;
 335                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
 336                 };
 337
 338                 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
 339                         reg = <1>;
 340                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
 341                 };
 342         };
 343
 344         port@4 {
 345                 reg = <4>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348
 349                 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
 350                         reg = <0>;
 351                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
 352                 };
 353
 354                 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
 355                         reg = <1>;
 356                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
 357                 };
 358         };
 359 };
 360
 361 &mux {
 362         mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
 363                         <0x34 0x00000038>, /* IPU_CSI1_MUX */
 364                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 365                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 366                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 367                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 368                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 369 };
 370
 371 &vpu {
 372         compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 373 };