1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
7 #include "imx6qdl.dtsi"
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
35 clock-latency = <61036>; /* two CLK32 periods */
36 clocks = <&clks IMX6QDL_CLK_ARM>,
37 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
38 <&clks IMX6QDL_CLK_STEP>,
39 <&clks IMX6QDL_CLK_PLL1_SW>,
40 <&clks IMX6QDL_CLK_PLL1_SYS>;
41 clock-names = "arm", "pll2_pfd2_396m", "step",
42 "pll1_sw", "pll1_sys";
43 arm-supply = <®_arm>;
44 pu-supply = <®_pu>;
45 soc-supply = <®_soc>;
49 compatible = "arm,cortex-a9";
52 next-level-cache = <&L2>;
58 compatible = "mmio-sram";
59 reg = <0x00900000 0x20000>;
60 clocks = <&clks IMX6QDL_CLK_OCRAM>;
63 aips1: aips-bus@2000000 {
64 iomuxc: iomuxc@20e0000 {
65 compatible = "fsl,imx6dl-iomuxc";
69 reg = <0x020f0000 0x4000>;
70 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
74 reg = <0x020f4000 0x4000>;
75 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
79 aips2: aips-bus@2100000 {
83 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
84 reg = <0x021f8000 0x4000>;
85 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&clks IMX6DL_CLK_I2C4>;
93 compatible = "fsl,imx-capture-subsystem";
94 ports = <&ipu1_csi0>, <&ipu1_csi1>;
98 compatible = "fsl,imx-display-subsystem";
99 ports = <&ipu1_di0>, <&ipu1_di1>;
104 gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
105 <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
106 <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
107 <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
108 <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
109 <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
110 <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
114 gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
115 <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
116 <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
117 <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
122 gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
127 gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
128 <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
129 <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
130 <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
131 <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
135 gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
136 <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
137 <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
138 <&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
142 gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
143 <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
144 <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
145 <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
146 <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
147 <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
151 gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
152 <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
153 <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
158 compatible = "video-mux";
159 mux-controls = <&mux 0>;
160 #address-cells = <1>;
166 ipu1_csi0_mux_from_mipi_vc0: endpoint {
167 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
174 ipu1_csi0_mux_from_mipi_vc1: endpoint {
175 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
182 ipu1_csi0_mux_from_mipi_vc2: endpoint {
183 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
190 ipu1_csi0_mux_from_mipi_vc3: endpoint {
191 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
198 ipu1_csi0_mux_from_parallel_sensor: endpoint {
205 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
206 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
212 compatible = "video-mux";
213 mux-controls = <&mux 1>;
214 #address-cells = <1>;
220 ipu1_csi1_mux_from_mipi_vc0: endpoint {
221 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
228 ipu1_csi1_mux_from_mipi_vc1: endpoint {
229 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
236 ipu1_csi1_mux_from_mipi_vc2: endpoint {
237 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
244 ipu1_csi1_mux_from_mipi_vc3: endpoint {
245 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
252 ipu1_csi1_mux_from_parallel_sensor: endpoint {
259 ipu1_csi1_mux_to_ipu1_csi1: endpoint {
260 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
267 compatible = "fsl,imx6dl-gpt";
271 compatible = "fsl,imx6dl-hdmi";
275 ipu1_csi1_from_ipu1_csi1_mux: endpoint {
276 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
281 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
282 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
283 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
284 clock-names = "di0_pll", "di1_pll",
285 "di0_sel", "di1_sel",
292 #address-cells = <1>;
295 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
297 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
300 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
302 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
308 #address-cells = <1>;
311 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
313 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
316 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
318 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
324 #address-cells = <1>;
327 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
329 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
332 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
334 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
340 #address-cells = <1>;
343 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
345 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
348 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
350 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
356 mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
357 <0x34 0x00000038>, /* IPU_CSI1_MUX */
358 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
359 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
360 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
361 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
362 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
366 compatible = "fsl,imx6dl-vpu", "cnm,coda960";