arch/arm/boot/dts/imx6dl-riotboard.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2014 Iain Paton <ipaton0@gmail.com>
   4  */
   5
   6 /dts-v1/;
   7 #include "imx6dl.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         model = "RIoTboard i.MX6S";
  12         compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
  13
  14         memory@10000000 {
  15                 device_type = "memory";
  16                 reg = <0x10000000 0x40000000>;
  17         };
  18
  19         chosen {
  20                 stdout-path = "serial1:115200n8";
  21         };
  22
  23         leds {
  24                 compatible = "gpio-leds";
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_led>;
  27
  28                 led0: user1 {
  29                         label = "user1";
  30                         gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
  31                         default-state = "on";
  32                         linux,default-trigger = "heartbeat";
  33                 };
  34
  35                 led1: user2 {
  36                         label = "user2";
  37                         gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
  38                         default-state = "off";
  39                 };
  40         };
  41
  42         sound {
  43                 compatible = "fsl,imx-audio-sgtl5000";
  44                 model = "imx6-riotboard-sgtl5000";
  45                 ssi-controller = <&ssi1>;
  46                 audio-codec = <&codec>;
  47                 audio-routing =
  48                         "MIC_IN", "Mic Jack",
  49                         "Mic Jack", "Mic Bias",
  50                         "Headphone Jack", "HP_OUT";
  51                         mux-int-port = <1>;
  52                         mux-ext-port = <3>;
  53         };
  54
  55         reg_2p5v: regulator-2p5v {
  56                 compatible = "regulator-fixed";
  57                 regulator-name = "2P5V";
  58                 regulator-min-microvolt = <2500000>;
  59                 regulator-max-microvolt = <2500000>;
  60         };
  61
  62         reg_3p3v: regulator-3p3v {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "3P3V";
  65                 regulator-min-microvolt = <3300000>;
  66                 regulator-max-microvolt = <3300000>;
  67         };
  68
  69         reg_usb_otg_vbus: regulator-usbotgvbus {
  70                 compatible = "regulator-fixed";
  71                 regulator-name = "usb_otg_vbus";
  72                 regulator-min-microvolt = <5000000>;
  73                 regulator-max-microvolt = <5000000>;
  74                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
  75         };
  76 };
  77
  78 &audmux {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_audmux>;
  81         status = "okay";
  82 };
  83
  84 &clks {
  85         fsl,pmic-stby-poweroff;
  86 };
  87
  88 &fec {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_enet>;
  91         phy-mode = "rgmii-id";
  92         phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
  93         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
  94                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
  95         fsl,err006687-workaround-present;
  96         status = "okay";
  97 };
  98
  99 &gpio1 {
 100         gpio-line-names =
 101                 "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL",
 102                         "I2C3_SDA", "I2C4_SCL",
 103                 "I2C4_SDA", "", "", "", "", "", "", "",
 104                 "", "PWM3", "", "", "", "", "", "",
 105                 "", "", "", "", "", "", "", "";
 106 };
 107
 108 &gpio3 {
 109         gpio-line-names =
 110                 "", "", "", "", "", "", "", "",
 111                 "", "", "", "", "", "", "", "",
 112                 "", "", "", "", "", "", "USB_OTG_VBUS", "",
 113                 "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", "";
 114 };
 115
 116 &gpio4 {
 117         gpio-line-names =
 118                 "", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
 119                 "UART5_TXD", "UART5_RXD", "", "", "", "", "", "",
 120                 "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "",
 121                         "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO",
 122                 "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27",
 123                         "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31";
 124 };
 125
 126 &gpio5 {
 127         gpio-line-names =
 128                 "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06",
 129                         "GPIO5_07",
 130                 "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO",
 131                         "CSPI2_CS0", "CSPI2_CLK", "", "",
 132                 "", "", "", "", "", "", "", "",
 133                 "", "", "", "", "", "", "", "";
 134 };
 135
 136 &gpio7 {
 137         gpio-line-names =
 138                 "SD3_CD", "SD3_WP", "", "", "", "", "", "",
 139                 "", "", "", "", "", "", "", "",
 140                 "", "", "", "", "", "", "", "",
 141                 "", "", "", "", "", "", "", "";
 142 };
 143
 144 &hdmi {
 145         ddc-i2c-bus = <&i2c2>;
 146         status = "okay";
 147 };
 148
 149 &i2c1 {
 150         clock-frequency = <100000>;
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_i2c1>;
 153         status = "okay";
 154
 155         codec: sgtl5000@a {
 156                 compatible = "fsl,sgtl5000";
 157                 reg = <0x0a>;
 158                 clocks = <&clks IMX6QDL_CLK_CKO>;
 159                 VDDA-supply = <&reg_2p5v>;
 160                 VDDIO-supply = <&reg_3p3v>;
 161         };
 162
 163         pmic: pf0100@8 {
 164                 compatible = "fsl,pfuze100";
 165                 reg = <0x08>;
 166                 interrupt-parent = <&gpio5>;
 167                 interrupts = <16 8>;
 168                 fsl,pmic-stby-poweroff;
 169
 170                 regulators {
 171                         reg_vddcore: sw1ab {                            /* VDDARM_IN */
 172                                 regulator-min-microvolt = <300000>;
 173                                 regulator-max-microvolt = <1875000>;
 174                                 regulator-always-on;
 175                         };
 176
 177                         reg_vddsoc: sw1c {                              /* VDDSOC_IN */
 178                                 regulator-min-microvolt = <300000>;
 179                                 regulator-max-microvolt = <1875000>;
 180                                 regulator-always-on;
 181                         };
 182
 183                         reg_gen_3v3: sw2 {                              /* VDDHIGH_IN */
 184                                 regulator-min-microvolt = <800000>;
 185                                 regulator-max-microvolt = <3300000>;
 186                                 regulator-always-on;
 187                         };
 188
 189                         reg_ddr_1v5a: sw3a {                            /* NVCC_DRAM, NVCC_RGMII */
 190                                 regulator-min-microvolt = <400000>;
 191                                 regulator-max-microvolt = <1975000>;
 192                                 regulator-always-on;
 193                         };
 194
 195                         reg_ddr_1v5b: sw3b {                            /* NVCC_DRAM, NVCC_RGMII */
 196                                 regulator-min-microvolt = <400000>;
 197                                 regulator-max-microvolt = <1975000>;
 198                                 regulator-always-on;
 199                         };
 200
 201                         reg_ddr_vtt: sw4 {                              /* MIPI conn */
 202                                 regulator-min-microvolt = <400000>;
 203                                 regulator-max-microvolt = <1975000>;
 204                                 regulator-always-on;
 205                         };
 206
 207                         reg_5v_600mA: swbst {                           /* not used */
 208                                 regulator-min-microvolt = <5000000>;
 209                                 regulator-max-microvolt = <5150000>;
 210                         };
 211
 212                         reg_snvs_3v: vsnvs {                            /* VDD_SNVS_IN */
 213                                 regulator-min-microvolt = <1500000>;
 214                                 regulator-max-microvolt = <3000000>;
 215                                 regulator-always-on;
 216                         };
 217
 218                         vref_reg: vrefddr {                             /* VREF_DDR */
 219                                 regulator-boot-on;
 220                                 regulator-always-on;
 221                         };
 222
 223                         reg_vgen1_1v5: vgen1 {                          /* not used */
 224                                 regulator-min-microvolt = <800000>;
 225                                 regulator-max-microvolt = <1550000>;
 226                         };
 227
 228                         reg_vgen2_1v2_eth: vgen2 {                      /* pcie ? */
 229                                 regulator-min-microvolt = <800000>;
 230                                 regulator-max-microvolt = <1550000>;
 231                                 regulator-always-on;
 232                         };
 233
 234                         reg_vgen3_2v8: vgen3 {                          /* not used */
 235                                 regulator-min-microvolt = <1800000>;
 236                                 regulator-max-microvolt = <3300000>;
 237                         };
 238                         reg_vgen4_1v8: vgen4 {                          /* NVCC_SD3 */
 239                                 regulator-min-microvolt = <1800000>;
 240                                 regulator-max-microvolt = <3300000>;
 241                                 regulator-always-on;
 242                         };
 243
 244                         reg_vgen5_2v5_sgtl: vgen5 {                     /* Pwr LED & 5V0_delayed enable */
 245                                 regulator-min-microvolt = <1800000>;
 246                                 regulator-max-microvolt = <3300000>;
 247                                 regulator-always-on;
 248                         };
 249
 250                         reg_vgen6_3v3: vgen6 {                          /* #V#_DELAYED enable, MIPI */
 251                                 regulator-min-microvolt = <1800000>;
 252                                 regulator-max-microvolt = <3300000>;
 253                                 regulator-always-on;
 254                         };
 255                 };
 256         };
 257 };
 258
 259 &i2c2 {
 260         clock-frequency = <100000>;
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_i2c2>;
 263         status = "okay";
 264 };
 265
 266 &i2c4 {
 267         clock-frequency = <100000>;
 268         pinctrl-names = "default";
 269         pinctrl-0 = <&pinctrl_i2c4>;
 270         clocks = <&clks 116>;
 271         status = "okay";
 272 };
 273
 274 &pwm1 {
 275         pinctrl-names = "default";
 276         pinctrl-0 = <&pinctrl_pwm1>;
 277         status = "okay";
 278 };
 279
 280 &pwm2 {
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_pwm2>;
 283         status = "okay";
 284 };
 285
 286 &pwm3 {
 287         pinctrl-names = "default";
 288         pinctrl-0 = <&pinctrl_pwm3>;
 289         status = "okay";
 290 };
 291
 292 &pwm4 {
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&pinctrl_pwm4>;
 295         status = "okay";
 296 };
 297
 298 &ssi1 {
 299         status = "okay";
 300 };
 301
 302 &uart1 {
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&pinctrl_uart1>;
 305         status = "okay";
 306 };
 307
 308 &uart2 {
 309         pinctrl-names = "default";
 310         pinctrl-0 = <&pinctrl_uart2>;
 311         status = "okay";
 312 };
 313
 314 &uart3 {
 315         pinctrl-names = "default";
 316         pinctrl-0 = <&pinctrl_uart3>;
 317         status = "okay";
 318 };
 319
 320 &uart4 {
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&pinctrl_uart4>;
 323         status = "okay";
 324 };
 325
 326 &uart5 {
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&pinctrl_uart5>;
 329         status = "okay";
 330 };
 331
 332 &usbh1 {
 333         dr_mode = "host";
 334         disable-over-current;
 335         status = "okay";
 336 };
 337
 338 &usbotg {
 339         vbus-supply = <&reg_usb_otg_vbus>;
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&pinctrl_usbotg>;
 342         disable-over-current;
 343         dr_mode = "otg";
 344         status = "okay";
 345 };
 346
 347 &usdhc2 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&pinctrl_usdhc2>;
 350         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 351         wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 352         vmmc-supply = <&reg_3p3v>;
 353         status = "okay";
 354 };
 355
 356 &usdhc3 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_usdhc3>;
 359         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 360         wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
 361         vmmc-supply = <&reg_3p3v>;
 362         status = "okay";
 363 };
 364
 365 &usdhc4 {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&pinctrl_usdhc4>;
 368         vmmc-supply = <&reg_3p3v>;
 369         non-removable;
 370         status = "okay";
 371 };
 372
 373 &iomuxc {
 374         pinctrl-names = "default";
 375
 376         imx6-riotboard {
 377                 pinctrl_audmux: audmuxgrp {
 378                         fsl,pins = <
 379                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 380                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 381                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 382                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 383                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0         /* CAM_MCLK */
 384                         >;
 385                 };
 386
 387                 pinctrl_ecspi1: ecspi1grp {
 388                         fsl,pins = <
 389                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 390                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 391                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 392                                 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x000b1         /* CS0 */
 393                         >;
 394                 };
 395
 396                 pinctrl_ecspi2: ecspi2grp {
 397                         fsl,pins = <
 398                                 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x000b1         /* CS1 */
 399                                 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI     0x100b1
 400                                 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO     0x100b1
 401                                 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x000b1         /* CS0 */
 402                                 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK     0x100b1
 403                         >;
 404                 };
 405
 406                 pinctrl_ecspi3: ecspi3grp {
 407                         fsl,pins = <
 408                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 409                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 410                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 411                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x000b1         /* CS0 */
 412                                 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25       0x000b1         /* CS1 */
 413                         >;
 414                 };
 415
 416                 pinctrl_enet: enetgrp {
 417                         fsl,pins = <
 418                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 419                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 420                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 421                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 422                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 423                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 424                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 425                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 426                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x0a0b1         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 427                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030         /* AR8035 pin strapping: IO voltage: pull up */
 428                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030         /* AR8035 pin strapping: PHYADDR#0: pull down */
 429                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030         /* AR8035 pin strapping: PHYADDR#1: pull down */
 430                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030         /* AR8035 pin strapping: MODE#1: pull up */
 431                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030         /* AR8035 pin strapping: MODE#3: pull up */
 432                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x130b0         /* AR8035 pin strapping: MODE#0: pull down */
 433                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8      /* GPIO16 -> AR8035 25MHz */
 434                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x130b0         /* RGMII_nRST */
 435                                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x180b0         /* AR8035 interrupt */
 436                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 437                         >;
 438                 };
 439
 440                 pinctrl_i2c1: i2c1grp {
 441                         fsl,pins = <
 442                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 443                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 444                         >;
 445                 };
 446
 447                 pinctrl_i2c2: i2c2grp {
 448                         fsl,pins = <
 449                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 450                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 451                         >;
 452                 };
 453
 454                 pinctrl_i2c3: i2c3grp {
 455                         fsl,pins = <
 456                                 MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
 457                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 458                         >;
 459                 };
 460
 461                 pinctrl_i2c4: i2c4grp {
 462                         fsl,pins = <
 463                                 MX6QDL_PAD_GPIO_7__I2C4_SCL             0x4001b8b1
 464                                 MX6QDL_PAD_GPIO_8__I2C4_SDA             0x4001b8b1
 465                         >;
 466                 };
 467
 468                 pinctrl_led: ledgrp {
 469                         fsl,pins = <
 470                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x1b0b1 /* user led0 */
 471                                 MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x1b0b1 /* user led1 */
 472                         >;
 473                 };
 474
 475                 pinctrl_pwm1: pwm1grp {
 476                         fsl,pins = <
 477                                 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT         0x1b0b1
 478                         >;
 479                 };
 480
 481                 pinctrl_pwm2: pwm2grp {
 482                         fsl,pins = <
 483                                 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT         0x1b0b1
 484                         >;
 485                 };
 486
 487                 pinctrl_pwm3: pwm3grp {
 488                         fsl,pins = <
 489                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 490                         >;
 491                 };
 492
 493                 pinctrl_pwm4: pwm4grp {
 494                         fsl,pins = <
 495                                 MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 496                         >;
 497                 };
 498
 499                 pinctrl_uart1: uart1grp {
 500                         fsl,pins = <
 501                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 502                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 503                         >;
 504                 };
 505
 506                 pinctrl_uart2: uart2grp {
 507                         fsl,pins = <
 508                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 509                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 510                         >;
 511                 };
 512
 513                 pinctrl_uart3: uart3grp {
 514                         fsl,pins = <
 515                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 516                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 517                         >;
 518                 };
 519
 520                 pinctrl_uart4: uart4grp {
 521                         fsl,pins = <
 522                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 523                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 524                         >;
 525                 };
 526
 527                 pinctrl_uart5: uart5grp {
 528                         fsl,pins = <
 529                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 530                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 531                         >;
 532                 };
 533
 534                 pinctrl_usbotg: usbotggrp {
 535                         fsl,pins = <
 536                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 537                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
 538                                 MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x1b0b0
 539                         >;
 540                 };
 541
 542                 pinctrl_usdhc2: usdhc2grp {
 543                         fsl,pins = <
 544                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 545                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 546                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 547                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 548                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 549                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 550                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* SD2 CD */
 551                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1f0b0 /* SD2 WP */
 552                         >;
 553                 };
 554
 555                 pinctrl_usdhc3: usdhc3grp {
 556                         fsl,pins = <
 557                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 558                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 559                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 560                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 561                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 562                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 563                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b0 /* SD3 CD */
 564                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1f0b0 /* SD3 WP */
 565                         >;
 566                 };
 567
 568                 pinctrl_usdhc4: usdhc4grp {
 569                         fsl,pins = <
 570                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 571                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 572                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 573                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 574                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 575                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 576                                 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x17059 /* SD4 RST (eMMC) */
 577                         >;
 578                 };
 579         };
 580 };