1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include "imx51-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS info.
42 tzic: tz-interrupt-controller@e0000000 {
43 compatible = "fsl,imx51-tzic", "fsl,tzic";
45 #interrupt-cells = <1>;
46 reg = <0xe0000000 0x4000>;
51 compatible = "fsl,imx-ckil", "fixed-clock";
53 clock-frequency = <32768>;
57 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
63 compatible = "fsl,imx-ckih2", "fixed-clock";
65 clock-frequency = <0>;
69 compatible = "fsl,imx-osc", "fixed-clock";
71 clock-frequency = <24000000>;
80 compatible = "arm,cortex-a8";
82 clock-latency = <62500>;
83 clocks = <&clks IMX5_CLK_CPU_PODF>;
90 voltage-tolerance = <5>;
95 compatible = "arm,cortex-a8-pmu";
96 interrupt-parent = <&tzic>;
101 compatible = "usb-nop-xceiv";
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
103 clock-names = "main_clk";
108 compatible = "fsl,imx-capture-subsystem";
109 ports = <&ipu_csi0>, <&ipu_csi1>;
113 compatible = "fsl,imx-display-subsystem";
114 ports = <&ipu_di0>, <&ipu_di1>;
118 #address-cells = <1>;
120 compatible = "simple-bus";
121 interrupt-parent = <&tzic>;
124 iram: sram@1ffe0000 {
125 compatible = "mmio-sram";
126 reg = <0x1ffe0000 0x20000>;
130 compatible = "amd,imageon-200.1", "amd,imageon";
131 reg = <0x30000000 0x20000>;
132 reg-names = "kgsl_3d0_reg_memory";
134 interrupt-names = "kgsl_3d0_irq";
135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
136 clock-names = "core_clk", "mem_iface_clk";
140 #address-cells = <1>;
142 compatible = "fsl,imx51-ipu";
143 reg = <0x40000000 0x20000000>;
144 interrupts = <11 10>;
145 clocks = <&clks IMX5_CLK_IPU_GATE>,
146 <&clks IMX5_CLK_IPU_DI0_GATE>,
147 <&clks IMX5_CLK_IPU_DI1_GATE>;
148 clock-names = "bus", "di0", "di1";
162 ipu_di0_disp1: endpoint {
169 ipu_di1_disp2: endpoint {
174 bus@70000000 { /* AIPS1 */
175 compatible = "fsl,aips-bus", "simple-bus";
176 #address-cells = <1>;
178 reg = <0x70000000 0x10000000>;
182 compatible = "fsl,spba-bus", "simple-bus";
183 #address-cells = <1>;
185 reg = <0x70000000 0x40000>;
188 esdhc1: esdhc@70004000 {
189 compatible = "fsl,imx51-esdhc";
190 reg = <0x70004000 0x4000>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
195 clock-names = "ipg", "ahb", "per";
199 esdhc2: esdhc@70008000 {
200 compatible = "fsl,imx51-esdhc";
201 reg = <0x70008000 0x4000>;
203 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
204 <&clks IMX5_CLK_DUMMY>,
205 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
206 clock-names = "ipg", "ahb", "per";
211 uart3: serial@7000c000 {
212 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
213 reg = <0x7000c000 0x4000>;
215 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
216 <&clks IMX5_CLK_UART3_PER_GATE>;
217 clock-names = "ipg", "per";
221 ecspi1: spi@70010000 {
222 #address-cells = <1>;
224 compatible = "fsl,imx51-ecspi";
225 reg = <0x70010000 0x4000>;
227 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
228 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
229 clock-names = "ipg", "per";
234 #sound-dai-cells = <0>;
235 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
236 reg = <0x70014000 0x4000>;
238 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
239 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
240 clock-names = "ipg", "baud";
241 dmas = <&sdma 24 1 0>,
243 dma-names = "rx", "tx";
244 fsl,fifo-depth = <15>;
248 esdhc3: esdhc@70020000 {
249 compatible = "fsl,imx51-esdhc";
250 reg = <0x70020000 0x4000>;
252 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
253 <&clks IMX5_CLK_DUMMY>,
254 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
255 clock-names = "ipg", "ahb", "per";
260 esdhc4: esdhc@70024000 {
261 compatible = "fsl,imx51-esdhc";
262 reg = <0x70024000 0x4000>;
264 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
265 <&clks IMX5_CLK_DUMMY>,
266 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
267 clock-names = "ipg", "ahb", "per";
273 aipstz1: bridge@73f00000 {
274 compatible = "fsl,imx51-aipstz";
275 reg = <0x73f00000 0x60>;
278 usbotg: usb@73f80000 {
279 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
280 reg = <0x73f80000 0x0200>;
282 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
283 fsl,usbmisc = <&usbmisc 0>;
284 fsl,usbphy = <&usbphy0>;
288 usbh1: usb@73f80200 {
289 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
290 reg = <0x73f80200 0x0200>;
292 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
293 fsl,usbmisc = <&usbmisc 1>;
298 usbh2: usb@73f80400 {
299 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
300 reg = <0x73f80400 0x0200>;
302 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
303 fsl,usbmisc = <&usbmisc 2>;
308 usbh3: usb@73f80600 {
309 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
310 reg = <0x73f80600 0x0200>;
312 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
313 fsl,usbmisc = <&usbmisc 3>;
318 usbmisc: usbmisc@73f80800 {
320 compatible = "fsl,imx51-usbmisc";
321 reg = <0x73f80800 0x200>;
322 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
325 gpio1: gpio@73f84000 {
326 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
327 reg = <0x73f84000 0x4000>;
328 interrupts = <50 51>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
335 gpio2: gpio@73f88000 {
336 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
337 reg = <0x73f88000 0x4000>;
338 interrupts = <52 53>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
345 gpio3: gpio@73f8c000 {
346 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
347 reg = <0x73f8c000 0x4000>;
348 interrupts = <54 55>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
355 gpio4: gpio@73f90000 {
356 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
357 reg = <0x73f90000 0x4000>;
358 interrupts = <56 57>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
366 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
367 reg = <0x73f94000 0x4000>;
369 clocks = <&clks IMX5_CLK_DUMMY>;
373 wdog1: wdog@73f98000 {
374 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
375 reg = <0x73f98000 0x4000>;
377 clocks = <&clks IMX5_CLK_DUMMY>;
380 wdog2: wdog@73f9c000 {
381 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
382 reg = <0x73f9c000 0x4000>;
384 clocks = <&clks IMX5_CLK_DUMMY>;
388 gpt: timer@73fa0000 {
389 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
390 reg = <0x73fa0000 0x4000>;
392 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
393 <&clks IMX5_CLK_GPT_HF_GATE>;
394 clock-names = "ipg", "per";
397 iomuxc: iomuxc@73fa8000 {
398 compatible = "fsl,imx51-iomuxc";
399 reg = <0x73fa8000 0x4000>;
404 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
405 reg = <0x73fb4000 0x4000>;
406 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
407 <&clks IMX5_CLK_PWM1_HF_GATE>;
408 clock-names = "ipg", "per";
414 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
415 reg = <0x73fb8000 0x4000>;
416 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
417 <&clks IMX5_CLK_PWM2_HF_GATE>;
418 clock-names = "ipg", "per";
422 uart1: serial@73fbc000 {
423 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
424 reg = <0x73fbc000 0x4000>;
426 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
427 <&clks IMX5_CLK_UART1_PER_GATE>;
428 clock-names = "ipg", "per";
432 uart2: serial@73fc0000 {
433 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
434 reg = <0x73fc0000 0x4000>;
436 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
437 <&clks IMX5_CLK_UART2_PER_GATE>;
438 clock-names = "ipg", "per";
443 compatible = "fsl,imx51-src";
444 reg = <0x73fd0000 0x4000>;
449 compatible = "fsl,imx51-ccm";
450 reg = <0x73fd4000 0x4000>;
451 interrupts = <0 71 0x04 0 72 0x04>;
456 bus@80000000 { /* AIPS2 */
457 compatible = "fsl,aips-bus", "simple-bus";
458 #address-cells = <1>;
460 reg = <0x80000000 0x10000000>;
463 aipstz2: bridge@83f00000 {
464 compatible = "fsl,imx51-aipstz";
465 reg = <0x83f00000 0x60>;
469 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
470 reg = <0x83f98000 0x4000>;
472 clocks = <&clks IMX5_CLK_IIM_GATE>;
475 tigerp: tigerp@83fa0000 {
476 compatible = "fsl,imx51-tigerp";
477 reg = <0x83fa0000 0x28>;
480 owire: owire@83fa4000 {
481 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
482 reg = <0x83fa4000 0x4000>;
484 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
488 ecspi2: spi@83fac000 {
489 #address-cells = <1>;
491 compatible = "fsl,imx51-ecspi";
492 reg = <0x83fac000 0x4000>;
494 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
495 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
496 clock-names = "ipg", "per";
500 sdma: sdma@83fb0000 {
501 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
502 reg = <0x83fb0000 0x4000>;
504 clocks = <&clks IMX5_CLK_SDMA_GATE>,
505 <&clks IMX5_CLK_AHB>;
506 clock-names = "ipg", "ahb";
508 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
512 #address-cells = <1>;
514 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
515 reg = <0x83fc0000 0x4000>;
517 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
518 <&clks IMX5_CLK_CSPI_IPG_GATE>;
519 clock-names = "ipg", "per";
524 #address-cells = <1>;
526 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
527 reg = <0x83fc4000 0x4000>;
529 clocks = <&clks IMX5_CLK_I2C2_GATE>;
534 #address-cells = <1>;
536 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
537 reg = <0x83fc8000 0x4000>;
539 clocks = <&clks IMX5_CLK_I2C1_GATE>;
544 #sound-dai-cells = <0>;
545 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
546 reg = <0x83fcc000 0x4000>;
548 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
549 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
550 clock-names = "ipg", "baud";
551 dmas = <&sdma 28 0 0>,
553 dma-names = "rx", "tx";
554 fsl,fifo-depth = <15>;
558 audmux: audmux@83fd0000 {
559 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
560 reg = <0x83fd0000 0x4000>;
561 clocks = <&clks IMX5_CLK_DUMMY>;
562 clock-names = "audmux";
566 m4if: m4if@83fd8000 {
567 compatible = "fsl,imx51-m4if";
568 reg = <0x83fd8000 0x1000>;
571 weim: weim@83fda000 {
572 #address-cells = <2>;
574 compatible = "fsl,imx51-weim";
575 reg = <0x83fda000 0x1000>;
576 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
578 0 0 0xb0000000 0x08000000
579 1 0 0xb8000000 0x08000000
580 2 0 0xc0000000 0x08000000
581 3 0 0xc8000000 0x04000000
582 4 0 0xcc000000 0x02000000
583 5 0 0xce000000 0x02000000
589 #address-cells = <1>;
591 compatible = "fsl,imx51-nand";
592 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
594 clocks = <&clks IMX5_CLK_NFC_GATE>;
598 pata: pata@83fe0000 {
599 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
600 reg = <0x83fe0000 0x4000>;
602 clocks = <&clks IMX5_CLK_PATA_GATE>;
607 #sound-dai-cells = <0>;
608 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
609 reg = <0x83fe8000 0x4000>;
611 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
612 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
613 clock-names = "ipg", "baud";
614 dmas = <&sdma 46 0 0>,
616 dma-names = "rx", "tx";
617 fsl,fifo-depth = <15>;
621 fec: ethernet@83fec000 {
622 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
623 reg = <0x83fec000 0x4000>;
625 clocks = <&clks IMX5_CLK_FEC_GATE>,
626 <&clks IMX5_CLK_FEC_GATE>,
627 <&clks IMX5_CLK_FEC_GATE>;
628 clock-names = "ipg", "ahb", "ptp";
633 compatible = "fsl,imx51-vpu", "cnm,codahx4";
634 reg = <0x83ff4000 0x1000>;
636 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
637 <&clks IMX5_CLK_VPU_GATE>;
638 clock-names = "per", "ahb";
643 sahara: crypto@83ff8000 {
644 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
645 reg = <0x83ff8000 0x4000>;
646 interrupts = <19 20>;
647 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
648 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
649 clock-names = "ipg", "ahb";