ARM: dts: imx: Switch NXP boards to SPDX identifier
[linux-2.6-microblaze.git] / arch / arm / boot / dts / imx51-babbage.dts
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
5
6 /dts-v1/;
7 #include "imx51.dtsi"
8
9 / {
10         model = "Freescale i.MX51 Babbage Board";
11         compatible = "fsl,imx51-babbage", "fsl,imx51";
12
13         chosen {
14                 stdout-path = &uart1;
15         };
16
17         memory@90000000 {
18                 reg = <0x90000000 0x20000000>;
19         };
20
21         ckih1 {
22                 clock-frequency = <22579200>;
23         };
24
25         clk_osc: clk-osc {
26                 compatible = "fixed-clock";
27                 #clock-cells = <0>;
28                 clock-frequency = <26000000>;
29         };
30
31         clk_osc_gate: clk-osc-gate {
32                 compatible = "gpio-gate-clock";
33                 pinctrl-names = "default";
34                 pinctrl-0 = <&pinctrl_clk26mhz_osc>;
35                 clocks = <&clk_osc>;
36                 #clock-cells = <0>;
37                 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
38         };
39
40         clk_audio: clk-audio {
41                 compatible = "gpio-gate-clock";
42                 pinctrl-names = "default";
43                 pinctrl-0 = <&pinctrl_clk26mhz_audio>;
44                 clocks = <&clk_osc_gate>;
45                 #clock-cells = <0>;
46                 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
47         };
48
49         clk_usb: clk-usb {
50                 compatible = "gpio-gate-clock";
51                 pinctrl-names = "default";
52                 pinctrl-0 = <&pinctrl_clk26mhz_usb>;
53                 clocks = <&clk_osc_gate>;
54                 #clock-cells = <0>;
55                 enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
56         };
57
58         display1: disp1 {
59                 compatible = "fsl,imx-parallel-display";
60                 interface-pix-fmt = "rgb24";
61                 pinctrl-names = "default";
62                 pinctrl-0 = <&pinctrl_ipu_disp1>;
63                 display-timings {
64                         native-mode = <&timing0>;
65                         timing0: dvi {
66                                 clock-frequency = <65000000>;
67                                 hactive = <1024>;
68                                 vactive = <768>;
69                                 hback-porch = <220>;
70                                 hfront-porch = <40>;
71                                 vback-porch = <21>;
72                                 vfront-porch = <7>;
73                                 hsync-len = <60>;
74                                 vsync-len = <10>;
75                         };
76                 };
77
78                 port {
79                         display0_in: endpoint {
80                                 remote-endpoint = <&ipu_di0_disp1>;
81                         };
82                 };
83         };
84
85         display2: disp2 {
86                 compatible = "fsl,imx-parallel-display";
87                 interface-pix-fmt = "rgb565";
88                 pinctrl-names = "default";
89                 pinctrl-0 = <&pinctrl_ipu_disp2>;
90                 status = "disabled";
91                 display-timings {
92                         native-mode = <&timing1>;
93                         timing1: claawvga {
94                                 clock-frequency = <27000000>;
95                                 hactive = <800>;
96                                 vactive = <480>;
97                                 hback-porch = <40>;
98                                 hfront-porch = <60>;
99                                 vback-porch = <10>;
100                                 vfront-porch = <10>;
101                                 hsync-len = <20>;
102                                 vsync-len = <10>;
103                                 hsync-active = <0>;
104                                 vsync-active = <0>;
105                                 de-active = <1>;
106                                 pixelclk-active = <0>;
107                         };
108                 };
109
110                 port {
111                         display1_in: endpoint {
112                                 remote-endpoint = <&ipu_di1_disp2>;
113                         };
114                 };
115         };
116
117         gpio-keys {
118                 compatible = "gpio-keys";
119                 pinctrl-names = "default";
120                 pinctrl-0 = <&pinctrl_gpio_keys>;
121
122                 power {
123                         label = "Power Button";
124                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
125                         linux,code = <KEY_POWER>;
126                         wakeup-source;
127                 };
128         };
129
130         leds {
131                 compatible = "gpio-leds";
132                 pinctrl-names = "default";
133                 pinctrl-0 = <&pinctrl_gpio_leds>;
134
135                 led-diagnostic {
136                         label = "diagnostic";
137                         gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
138                 };
139         };
140
141         regulators {
142                 compatible = "simple-bus";
143                 #address-cells = <1>;
144                 #size-cells = <0>;
145
146                 reg_hub_reset: regulator@0 {
147                         compatible = "regulator-fixed";
148                         pinctrl-names = "default";
149                         pinctrl-0 = <&pinctrl_usbotgreg>;
150                         reg = <0>;
151                         regulator-name = "hub_reset";
152                         regulator-min-microvolt = <5000000>;
153                         regulator-max-microvolt = <5000000>;
154                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
155                         enable-active-high;
156                 };
157         };
158
159         sound {
160                 compatible = "fsl,imx51-babbage-sgtl5000",
161                              "fsl,imx-audio-sgtl5000";
162                 model = "imx51-babbage-sgtl5000";
163                 ssi-controller = <&ssi2>;
164                 audio-codec = <&sgtl5000>;
165                 audio-routing =
166                         "MIC_IN", "Mic Jack",
167                         "Mic Jack", "Mic Bias",
168                         "Headphone Jack", "HP_OUT";
169                 mux-int-port = <2>;
170                 mux-ext-port = <3>;
171         };
172
173         usbphy {
174                 #address-cells = <1>;
175                 #size-cells = <0>;
176                 compatible = "simple-bus";
177
178                 usbh1phy: usbh1phy@0 {
179                         compatible = "usb-nop-xceiv";
180                         reg = <0>;
181                         clocks = <&clk_usb>;
182                         clock-names = "main_clk";
183                         reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
184                         vcc-supply = <&vusb_reg>;
185                         #phy-cells = <0>;
186                 };
187         };
188 };
189
190 &audmux {
191         pinctrl-names = "default";
192         pinctrl-0 = <&pinctrl_audmux>;
193         status = "okay";
194 };
195
196 &ecspi1 {
197         pinctrl-names = "default";
198         pinctrl-0 = <&pinctrl_ecspi1>;
199         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
200                    <&gpio4 25 GPIO_ACTIVE_LOW>;
201         status = "okay";
202
203         pmic: mc13892@0 {
204                 compatible = "fsl,mc13892";
205                 pinctrl-names = "default";
206                 pinctrl-0 = <&pinctrl_pmic>;
207                 spi-max-frequency = <6000000>;
208                 spi-cs-high;
209                 reg = <0>;
210                 interrupt-parent = <&gpio1>;
211                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
212                 fsl,mc13xxx-uses-rtc;
213
214                 regulators {
215                         sw1_reg: sw1 {
216                                 regulator-min-microvolt = <600000>;
217                                 regulator-max-microvolt = <1375000>;
218                                 regulator-boot-on;
219                                 regulator-always-on;
220                         };
221
222                         sw2_reg: sw2 {
223                                 regulator-min-microvolt = <900000>;
224                                 regulator-max-microvolt = <1850000>;
225                                 regulator-boot-on;
226                                 regulator-always-on;
227                         };
228
229                         sw3_reg: sw3 {
230                                 regulator-min-microvolt = <1100000>;
231                                 regulator-max-microvolt = <1850000>;
232                                 regulator-boot-on;
233                                 regulator-always-on;
234                         };
235
236                         sw4_reg: sw4 {
237                                 regulator-min-microvolt = <1100000>;
238                                 regulator-max-microvolt = <1850000>;
239                                 regulator-boot-on;
240                                 regulator-always-on;
241                         };
242
243                         vpll_reg: vpll {
244                                 regulator-min-microvolt = <1050000>;
245                                 regulator-max-microvolt = <1800000>;
246                                 regulator-boot-on;
247                                 regulator-always-on;
248                         };
249
250                         vdig_reg: vdig {
251                                 regulator-min-microvolt = <1650000>;
252                                 regulator-max-microvolt = <1650000>;
253                                 regulator-boot-on;
254                         };
255
256                         vsd_reg: vsd {
257                                 regulator-min-microvolt = <1800000>;
258                                 regulator-max-microvolt = <3150000>;
259                         };
260
261                         vusb_reg: vusb {
262                                 regulator-boot-on;
263                         };
264
265                         vusb2_reg: vusb2 {
266                                 regulator-min-microvolt = <2400000>;
267                                 regulator-max-microvolt = <2775000>;
268                                 regulator-boot-on;
269                                 regulator-always-on;
270                         };
271
272                         vvideo_reg: vvideo {
273                                 regulator-min-microvolt = <2775000>;
274                                 regulator-max-microvolt = <2775000>;
275                         };
276
277                         vaudio_reg: vaudio {
278                                 regulator-min-microvolt = <2300000>;
279                                 regulator-max-microvolt = <3000000>;
280                         };
281
282                         vcam_reg: vcam {
283                                 regulator-min-microvolt = <2500000>;
284                                 regulator-max-microvolt = <3000000>;
285                         };
286
287                         vgen1_reg: vgen1 {
288                                 regulator-min-microvolt = <1200000>;
289                                 regulator-max-microvolt = <1200000>;
290                         };
291
292                         vgen2_reg: vgen2 {
293                                 regulator-min-microvolt = <1200000>;
294                                 regulator-max-microvolt = <3150000>;
295                                 regulator-always-on;
296                         };
297
298                         vgen3_reg: vgen3 {
299                                 regulator-min-microvolt = <1800000>;
300                                 regulator-max-microvolt = <2900000>;
301                                 regulator-always-on;
302                         };
303                 };
304         };
305
306         flash: at45db321d@1 {
307                 #address-cells = <1>;
308                 #size-cells = <1>;
309                 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
310                 spi-max-frequency = <25000000>;
311                 reg = <1>;
312
313                 partition@0 {
314                         label = "U-Boot";
315                         reg = <0x0 0x40000>;
316                         read-only;
317                 };
318
319                 partition@40000 {
320                         label = "Kernel";
321                         reg = <0x40000 0x3c0000>;
322                 };
323         };
324 };
325
326 &esdhc1 {
327         pinctrl-names = "default";
328         pinctrl-0 = <&pinctrl_esdhc1>;
329         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
330         wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
331         status = "okay";
332 };
333
334 &esdhc2 {
335         pinctrl-names = "default";
336         pinctrl-0 = <&pinctrl_esdhc2>;
337         cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
338         wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
339         status = "okay";
340 };
341
342 &fec {
343         pinctrl-names = "default";
344         pinctrl-0 = <&pinctrl_fec>;
345         phy-mode = "mii";
346         phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
347         phy-reset-duration = <1>;
348         status = "okay";
349 };
350
351 &i2c1 {
352         pinctrl-names = "default";
353         pinctrl-0 = <&pinctrl_i2c1>;
354         status = "okay";
355 };
356
357 &i2c2 {
358         pinctrl-names = "default";
359         pinctrl-0 = <&pinctrl_i2c2>;
360         status = "okay";
361
362         sgtl5000: codec@a {
363                 compatible = "fsl,sgtl5000";
364                 reg = <0x0a>;
365                 #sound-dai-cells = <0>;
366                 clocks = <&clk_audio>;
367                 VDDA-supply = <&vdig_reg>;
368                 VDDIO-supply = <&vvideo_reg>;
369         };
370 };
371
372 &ipu_di0_disp1 {
373         remote-endpoint = <&display0_in>;
374 };
375
376 &ipu_di1_disp2 {
377         remote-endpoint = <&display1_in>;
378 };
379
380 &kpp {
381         pinctrl-names = "default";
382         pinctrl-0 = <&pinctrl_kpp>;
383         linux,keymap = <
384                 MATRIX_KEY(0, 0, KEY_UP)
385                 MATRIX_KEY(0, 1, KEY_DOWN)
386                 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
387                 MATRIX_KEY(0, 3, KEY_HOME)
388                 MATRIX_KEY(1, 0, KEY_RIGHT)
389                 MATRIX_KEY(1, 1, KEY_LEFT)
390                 MATRIX_KEY(1, 2, KEY_ENTER)
391                 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
392                 MATRIX_KEY(2, 0, KEY_F6)
393                 MATRIX_KEY(2, 1, KEY_F8)
394                 MATRIX_KEY(2, 2, KEY_F9)
395                 MATRIX_KEY(2, 3, KEY_F10)
396                 MATRIX_KEY(3, 0, KEY_F1)
397                 MATRIX_KEY(3, 1, KEY_F2)
398                 MATRIX_KEY(3, 2, KEY_F3)
399                 MATRIX_KEY(3, 3, KEY_POWER)
400         >;
401         status = "okay";
402 };
403
404 &ssi2 {
405         status = "okay";
406 };
407
408 &uart1 {
409         pinctrl-names = "default";
410         pinctrl-0 = <&pinctrl_uart1>;
411         uart-has-rtscts;
412         status = "okay";
413 };
414
415 &uart2 {
416         pinctrl-names = "default";
417         pinctrl-0 = <&pinctrl_uart2>;
418         status = "okay";
419 };
420
421 &uart3 {
422         pinctrl-names = "default";
423         pinctrl-0 = <&pinctrl_uart3>;
424         uart-has-rtscts;
425         status = "okay";
426 };
427
428 &usbh1 {
429         pinctrl-names = "default";
430         pinctrl-0 = <&pinctrl_usbh1>;
431         vbus-supply = <&reg_hub_reset>;
432         fsl,usbphy = <&usbh1phy>;
433         phy_type = "ulpi";
434         status = "okay";
435 };
436
437 &usbphy0 {
438         vcc-supply = <&vusb_reg>;
439 };
440
441 &usbotg {
442         dr_mode = "otg";
443         disable-over-current;
444         phy_type = "utmi_wide";
445         status = "okay";
446 };
447
448 &iomuxc {
449         imx51-babbage {
450                 pinctrl_audmux: audmuxgrp {
451                         fsl,pins = <
452                                 MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
453                                 MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
454                                 MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
455                                 MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
456                         >;
457                 };
458
459                 pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
460                         fsl,pins = <
461                                 MX51_PAD_CSPI1_RDY__GPIO4_26            0x85
462                         >;
463                 };
464
465                 pinctrl_clk26mhz_osc: clk26mhzoscgrp {
466                         fsl,pins = <
467                                 MX51_PAD_DI1_PIN12__GPIO3_1             0x85
468                         >;
469                 };
470
471                 pinctrl_clk26mhz_usb: clk26mhzusbgrp {
472                         fsl,pins = <
473                                 MX51_PAD_EIM_D17__GPIO2_1               0x85
474                         >;
475                 };
476
477                 pinctrl_ecspi1: ecspi1grp {
478                         fsl,pins = <
479                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
480                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
481                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
482                                 MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
483                                 MX51_PAD_CSPI1_SS1__GPIO4_25            0x85 /* CS1 */
484                         >;
485                 };
486
487                 pinctrl_esdhc1: esdhc1grp {
488                         fsl,pins = <
489                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
490                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
491                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
492                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
493                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
494                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
495                                 MX51_PAD_GPIO1_0__GPIO1_0               0x100
496                                 MX51_PAD_GPIO1_1__GPIO1_1               0x100
497                         >;
498                 };
499
500                 pinctrl_esdhc2: esdhc2grp {
501                         fsl,pins = <
502                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
503                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
504                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
505                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
506                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
507                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
508                                 MX51_PAD_GPIO1_5__GPIO1_5               0x100 /* WP */
509                                 MX51_PAD_GPIO1_6__GPIO1_6               0x100 /* CD */
510                         >;
511                 };
512
513                 pinctrl_fec: fecgrp {
514                         fsl,pins = <
515                                 MX51_PAD_EIM_EB2__FEC_MDIO              0x000001f5
516                                 MX51_PAD_EIM_EB3__FEC_RDATA1            0x00000085
517                                 MX51_PAD_EIM_CS2__FEC_RDATA2            0x00000085
518                                 MX51_PAD_EIM_CS3__FEC_RDATA3            0x00000085
519                                 MX51_PAD_EIM_CS4__FEC_RX_ER             0x00000180
520                                 MX51_PAD_EIM_CS5__FEC_CRS               0x00000180
521                                 MX51_PAD_NANDF_RB2__FEC_COL             0x00000180
522                                 MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x00000180
523                                 MX51_PAD_NANDF_D9__FEC_RDATA0           0x00002180
524                                 MX51_PAD_NANDF_D8__FEC_TDATA0           0x00002004
525                                 MX51_PAD_NANDF_CS2__FEC_TX_ER           0x00002004
526                                 MX51_PAD_NANDF_CS3__FEC_MDC             0x00002004
527                                 MX51_PAD_NANDF_CS4__FEC_TDATA1          0x00002004
528                                 MX51_PAD_NANDF_CS5__FEC_TDATA2          0x00002004
529                                 MX51_PAD_NANDF_CS6__FEC_TDATA3          0x00002004
530                                 MX51_PAD_NANDF_CS7__FEC_TX_EN           0x00002004
531                                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x00002180
532                                 MX51_PAD_NANDF_D11__FEC_RX_DV           0x000020a4
533                                 MX51_PAD_EIM_A20__GPIO2_14              0x00000085 /* Phy Reset */
534                         >;
535                 };
536
537                 pinctrl_gpio_keys: gpiokeysgrp {
538                         fsl,pins = <
539                                 MX51_PAD_EIM_A27__GPIO2_21              0x5
540                         >;
541                 };
542
543                 pinctrl_gpio_leds: gpioledsgrp {
544                         fsl,pins = <
545                                 MX51_PAD_EIM_D22__GPIO2_6               0x80000000
546                         >;
547                 };
548
549                 pinctrl_i2c1: i2c1grp {
550                         fsl,pins = <
551                                 MX51_PAD_EIM_D19__I2C1_SCL              0x400001ed
552                                 MX51_PAD_EIM_D16__I2C1_SDA              0x400001ed
553                         >;
554                 };
555
556                 pinctrl_i2c2: i2c2grp {
557                         fsl,pins = <
558                                 MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
559                                 MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
560                         >;
561                 };
562
563                 pinctrl_ipu_disp1: ipudisp1grp {
564                         fsl,pins = <
565                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
566                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
567                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
568                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
569                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
570                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
571                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
572                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
573                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
574                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
575                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
576                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
577                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
578                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
579                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
580                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
581                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
582                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
583                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
584                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
585                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
586                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
587                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
588                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
589                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
590                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
591                         >;
592                 };
593
594                 pinctrl_ipu_disp2: ipudisp2grp {
595                         fsl,pins = <
596                                 MX51_PAD_DISP2_DAT0__DISP2_DAT0         0x5
597                                 MX51_PAD_DISP2_DAT1__DISP2_DAT1         0x5
598                                 MX51_PAD_DISP2_DAT2__DISP2_DAT2         0x5
599                                 MX51_PAD_DISP2_DAT3__DISP2_DAT3         0x5
600                                 MX51_PAD_DISP2_DAT4__DISP2_DAT4         0x5
601                                 MX51_PAD_DISP2_DAT5__DISP2_DAT5         0x5
602                                 MX51_PAD_DISP2_DAT6__DISP2_DAT6         0x5
603                                 MX51_PAD_DISP2_DAT7__DISP2_DAT7         0x5
604                                 MX51_PAD_DISP2_DAT8__DISP2_DAT8         0x5
605                                 MX51_PAD_DISP2_DAT9__DISP2_DAT9         0x5
606                                 MX51_PAD_DISP2_DAT10__DISP2_DAT10       0x5
607                                 MX51_PAD_DISP2_DAT11__DISP2_DAT11       0x5
608                                 MX51_PAD_DISP2_DAT12__DISP2_DAT12       0x5
609                                 MX51_PAD_DISP2_DAT13__DISP2_DAT13       0x5
610                                 MX51_PAD_DISP2_DAT14__DISP2_DAT14       0x5
611                                 MX51_PAD_DISP2_DAT15__DISP2_DAT15       0x5
612                                 MX51_PAD_DI2_PIN2__DI2_PIN2             0x5
613                                 MX51_PAD_DI2_PIN3__DI2_PIN3             0x5
614                                 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
615                                 MX51_PAD_DI_GP4__DI2_PIN15              0x5
616                         >;
617                 };
618
619                 pinctrl_kpp: kppgrp {
620                         fsl,pins = <
621                                 MX51_PAD_KEY_ROW0__KEY_ROW0             0xe0
622                                 MX51_PAD_KEY_ROW1__KEY_ROW1             0xe0
623                                 MX51_PAD_KEY_ROW2__KEY_ROW2             0xe0
624                                 MX51_PAD_KEY_ROW3__KEY_ROW3             0xe0
625                                 MX51_PAD_KEY_COL0__KEY_COL0             0xe8
626                                 MX51_PAD_KEY_COL1__KEY_COL1             0xe8
627                                 MX51_PAD_KEY_COL2__KEY_COL2             0xe8
628                                 MX51_PAD_KEY_COL3__KEY_COL3             0xe8
629                         >;
630                 };
631
632                 pinctrl_pmic: pmicgrp {
633                         fsl,pins = <
634                                 MX51_PAD_GPIO1_8__GPIO1_8               0xe5 /* IRQ */
635                         >;
636                 };
637
638                 pinctrl_uart1: uart1grp {
639                         fsl,pins = <
640                                 MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
641                                 MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
642                                 MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
643                                 MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
644                         >;
645                 };
646
647                 pinctrl_uart2: uart2grp {
648                         fsl,pins = <
649                                 MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
650                                 MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
651                         >;
652                 };
653
654                 pinctrl_uart3: uart3grp {
655                         fsl,pins = <
656                                 MX51_PAD_EIM_D25__UART3_RXD             0x1c5
657                                 MX51_PAD_EIM_D26__UART3_TXD             0x1c5
658                                 MX51_PAD_EIM_D27__UART3_RTS             0x1c5
659                                 MX51_PAD_EIM_D24__UART3_CTS             0x1c5
660                         >;
661                 };
662
663                 pinctrl_usbh1: usbh1grp {
664                         fsl,pins = <
665                                 MX51_PAD_USBH1_CLK__USBH1_CLK           0x80000000
666                                 MX51_PAD_USBH1_DIR__USBH1_DIR           0x80000000
667                                 MX51_PAD_USBH1_NXT__USBH1_NXT           0x80000000
668                                 MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x80000000
669                                 MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x80000000
670                                 MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x80000000
671                                 MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x80000000
672                                 MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x80000000
673                                 MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x80000000
674                                 MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x80000000
675                                 MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x80000000
676                         >;
677                 };
678
679                 pinctrl_usbh1reg: usbh1reggrp {
680                         fsl,pins = <
681                                 MX51_PAD_EIM_D21__GPIO2_5               0x85
682                         >;
683                 };
684
685                 pinctrl_usbotgreg: usbotgreggrp {
686                         fsl,pins = <
687                                 MX51_PAD_GPIO1_7__GPIO1_7               0x85
688                         >;
689                 };
690         };
691 };