1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
8 /* First 4KB has pen for secondary cores. */
9 /memreserve/ 0x00000000 0x0001000;
12 model = "Calxeda Highbank";
13 compatible = "calxeda,highbank";
23 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
38 clock-latency = <100000>;
42 compatible = "arm,cortex-a9";
45 next-level-cache = <&L2>;
57 clock-latency = <100000>;
61 compatible = "arm,cortex-a9";
64 next-level-cache = <&L2>;
76 clock-latency = <100000>;
80 compatible = "arm,cortex-a9";
83 next-level-cache = <&L2>;
95 clock-latency = <100000>;
101 device_type = "memory";
102 reg = <0x00000000 0xff900000>;
106 ranges = <0x00000000 0x00000000 0xffffffff>;
108 memory-controller@fff00000 {
109 compatible = "calxeda,hb-ddr-ctrl";
110 reg = <0xfff00000 0x1000>;
111 interrupts = <0 91 4>;
115 compatible = "arm,cortex-a9-twd-timer";
116 reg = <0xfff10600 0x20>;
117 interrupts = <1 13 0xf01>;
118 clocks = <&a9periphclk>;
122 compatible = "arm,cortex-a9-twd-wdt";
123 reg = <0xfff10620 0x20>;
124 interrupts = <1 14 0xf01>;
125 clocks = <&a9periphclk>;
128 intc: interrupt-controller@fff11000 {
129 compatible = "arm,cortex-a9-gic";
130 #interrupt-cells = <3>;
132 #address-cells = <1>;
133 interrupt-controller;
134 reg = <0xfff11000 0x1000>,
139 compatible = "arm,pl310-cache";
140 reg = <0xfff12000 0x1000>;
141 interrupts = <0 70 4>;
147 compatible = "arm,cortex-a9-pmu";
148 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
153 compatible = "calxeda,hb-sregs-l2-ecc";
154 reg = <0xfff3c200 0x100>;
155 interrupts = <0 71 4 0 72 4>;
161 /include/ "ecx-common.dtsi"