1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for ITian Square One SQ201 NAS
9 #include <dt-bindings/input/input.h>
12 model = "ITian Square One SQ201";
13 compatible = "itian,sq201", "cortina,gemini";
17 memory@0 { /* 128 MB */
18 device_type = "memory";
19 reg = <0x00000000 0x8000000>;
23 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
28 compatible = "gpio-keys";
31 debounce-interval = <100>;
33 linux,code = <KEY_SETUP>;
34 label = "factory reset";
35 /* Conflict with NAND flash */
36 gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
41 compatible = "gpio-leds";
43 label = "sq201:green:info";
44 gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
46 linux,default-trigger = "heartbeat";
49 label = "sq201:green:usb";
50 gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
51 default-state = "off";
52 linux,default-trigger = "usb-host";
57 compatible = "virtual,mdio-gpio";
58 /* Uses MDC and MDIO */
59 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
60 <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
64 /* This is a Marvell 88E1111 ethernet transciever */
65 phy0: ethernet-phy@1 {
71 compatible = "spi-gpio";
74 /* Check pin collisions */
75 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
76 gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
77 gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
78 cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
79 num-chipselects = <1>;
82 compatible = "vitesse,vsc7395";
84 /* Specified for 2.5 MHz or below */
85 spi-max-frequency = <2500000>;
128 pinctrl-names = "enabled", "disabled";
129 pinctrl-0 = <&pflash_default_pins>;
130 pinctrl-1 = <&pflash_disabled_pins>;
132 reg = <0x30000000 0x01000000>;
135 compatible = "redboot-fis";
136 /* Eraseblock at 0xfe0000 */
137 fis-index-block = <0x1fc>;
141 syscon: syscon@40000000 {
144 * gpio0fgrp cover line 18 used by reset button
145 * gpio0ggrp cover line 20 used by info LED
146 * gpio0hgrp cover line 21, 22 used by MDIO for Marvell PHY
147 * gpio0kgrp cover line 31 used by USB LED
149 gpio0_default_pins: pinctrl-gpio0 {
152 groups = "gpio0fgrp",
157 * gpio0dgrp cover lines used by the SPI
158 * to the Vitesse G5x chip.
160 gpio1_default_pins: pinctrl-gpio1 {
163 groups = "gpio1dgrp";
167 * These GPIO groups will be mapped in over some
168 * of the flash pins when the flash is not in
171 pflash_disabled_pins: pinctrl-pflash-disabled {
174 groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
181 groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
183 /* Settings come from memory dump in PLATO */
185 pins = "V8 GMAC0 RXDV";
189 pins = "Y7 GMAC0 RXC";
193 pins = "T8 GMAC0 TXEN";
197 pins = "U8 GMAC0 TXC";
201 pins = "T10 GMAC1 RXDV";
205 pins = "Y11 GMAC1 RXC";
209 pins = "W11 GMAC1 TXEN";
213 pins = "V11 GMAC1 TXC";
217 /* The data lines all have default skew */
218 pins = "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
219 "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
220 "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
221 "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
222 "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
223 "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
224 "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
225 "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
228 /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */
230 groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
231 drive-strength = <16>;
237 sata: sata@46000000 {
238 cortina,gemini-ata-muxmode = <0>;
239 cortina,gemini-enable-sata-bridge;
243 gpio0: gpio@4d000000 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&gpio0_default_pins>;
248 gpio1: gpio@4e000000 {
249 pinctrl-names = "default";
250 pinctrl-0 = <&gpio1_default_pins>;
255 interrupt-map-mask = <0xf800 0 0 7>;
257 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
258 <0x4800 0 0 2 &pci_intc 1>,
259 <0x4800 0 0 3 &pci_intc 2>,
260 <0x4800 0 0 4 &pci_intc 3>,
261 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
262 <0x5000 0 0 2 &pci_intc 2>,
263 <0x5000 0 0 3 &pci_intc 3>,
264 <0x5000 0 0 4 &pci_intc 0>,
265 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
266 <0x5800 0 0 2 &pci_intc 3>,
267 <0x5800 0 0 3 &pci_intc 0>,
268 <0x5800 0 0 4 &pci_intc 1>,
269 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
270 <0x6000 0 0 2 &pci_intc 0>,
271 <0x6000 0 0 3 &pci_intc 1>,
272 <0x6000 0 0 4 &pci_intc 2>;
280 phy-handle = <&phy0>;