1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
5 * Copyright (c) 2017 Marek Szyprowski
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos5800.dtsi"
14 #include "exynos5422-cpus.dtsi"
18 device_type = "memory";
19 reg = <0x40000000 0x7EA00000>;
23 stdout-path = "serial2:115200n8";
27 compatible = "samsung,secure-firmware";
28 reg = <0x02073000 0x1000>;
33 compatible = "samsung,exynos5420-oscclk";
34 clock-frequency = <24000000>;
38 bus_wcore_opp_table: opp-table2 {
39 compatible = "operating-points-v2";
41 /* derived from 532MHz MPLL */
43 opp-hz = /bits/ 64 <88700000>;
44 opp-microvolt = <925000 925000 1400000>;
47 opp-hz = /bits/ 64 <133000000>;
48 opp-microvolt = <950000 950000 1400000>;
51 opp-hz = /bits/ 64 <177400000>;
52 opp-microvolt = <950000 950000 1400000>;
55 opp-hz = /bits/ 64 <266000000>;
56 opp-microvolt = <950000 950000 1400000>;
59 opp-hz = /bits/ 64 <532000000>;
60 opp-microvolt = <1000000 1000000 1400000>;
64 bus_noc_opp_table: opp-table3 {
65 compatible = "operating-points-v2";
67 /* derived from 666MHz CPLL */
69 opp-hz = /bits/ 64 <66600000>;
72 opp-hz = /bits/ 64 <74000000>;
75 opp-hz = /bits/ 64 <83250000>;
78 opp-hz = /bits/ 64 <111000000>;
82 bus_fsys_apb_opp_table: opp-table4 {
83 compatible = "operating-points-v2";
85 /* derived from 666MHz CPLL */
87 opp-hz = /bits/ 64 <111000000>;
90 opp-hz = /bits/ 64 <222000000>;
94 bus_fsys2_opp_table: opp-table5 {
95 compatible = "operating-points-v2";
97 /* derived from 600MHz DPLL */
99 opp-hz = /bits/ 64 <75000000>;
102 opp-hz = /bits/ 64 <120000000>;
105 opp-hz = /bits/ 64 <200000000>;
109 bus_mfc_opp_table: opp-table6 {
110 compatible = "operating-points-v2";
112 /* derived from 666MHz CPLL */
114 opp-hz = /bits/ 64 <83250000>;
117 opp-hz = /bits/ 64 <111000000>;
120 opp-hz = /bits/ 64 <166500000>;
123 opp-hz = /bits/ 64 <222000000>;
126 opp-hz = /bits/ 64 <333000000>;
130 bus_gen_opp_table: opp-table7 {
131 compatible = "operating-points-v2";
133 /* derived from 532MHz MPLL */
135 opp-hz = /bits/ 64 <88700000>;
138 opp-hz = /bits/ 64 <133000000>;
141 opp-hz = /bits/ 64 <178000000>;
144 opp-hz = /bits/ 64 <266000000>;
148 bus_peri_opp_table: opp-table8 {
149 compatible = "operating-points-v2";
151 /* derived from 666MHz CPLL */
153 opp-hz = /bits/ 64 <66600000>;
157 bus_g2d_opp_table: opp-table9 {
158 compatible = "operating-points-v2";
160 /* derived from 666MHz CPLL */
162 opp-hz = /bits/ 64 <83250000>;
165 opp-hz = /bits/ 64 <111000000>;
168 opp-hz = /bits/ 64 <166500000>;
171 opp-hz = /bits/ 64 <222000000>;
174 opp-hz = /bits/ 64 <333000000>;
178 bus_g2d_acp_opp_table: opp-table10 {
179 compatible = "operating-points-v2";
181 /* derived from 532MHz MPLL */
183 opp-hz = /bits/ 64 <66500000>;
186 opp-hz = /bits/ 64 <133000000>;
189 opp-hz = /bits/ 64 <178000000>;
192 opp-hz = /bits/ 64 <266000000>;
196 bus_jpeg_opp_table: opp-table11 {
197 compatible = "operating-points-v2";
199 /* derived from 600MHz DPLL */
201 opp-hz = /bits/ 64 <75000000>;
204 opp-hz = /bits/ 64 <150000000>;
207 opp-hz = /bits/ 64 <200000000>;
210 opp-hz = /bits/ 64 <300000000>;
214 bus_jpeg_apb_opp_table: opp-table12 {
215 compatible = "operating-points-v2";
217 /* derived from 666MHz CPLL */
219 opp-hz = /bits/ 64 <83250000>;
222 opp-hz = /bits/ 64 <111000000>;
225 opp-hz = /bits/ 64 <133000000>;
228 opp-hz = /bits/ 64 <166500000>;
232 bus_disp1_fimd_opp_table: opp-table13 {
233 compatible = "operating-points-v2";
235 /* derived from 600MHz DPLL */
237 opp-hz = /bits/ 64 <120000000>;
240 opp-hz = /bits/ 64 <200000000>;
244 bus_disp1_opp_table: opp-table14 {
245 compatible = "operating-points-v2";
247 /* derived from 600MHz DPLL */
249 opp-hz = /bits/ 64 <120000000>;
252 opp-hz = /bits/ 64 <200000000>;
255 opp-hz = /bits/ 64 <300000000>;
259 bus_gscl_opp_table: opp-table15 {
260 compatible = "operating-points-v2";
262 /* derived from 600MHz DPLL */
264 opp-hz = /bits/ 64 <150000000>;
267 opp-hz = /bits/ 64 <200000000>;
270 opp-hz = /bits/ 64 <300000000>;
274 bus_mscl_opp_table: opp-table16 {
275 compatible = "operating-points-v2";
277 /* derived from 666MHz CPLL */
279 opp-hz = /bits/ 64 <84000000>;
282 opp-hz = /bits/ 64 <167000000>;
285 opp-hz = /bits/ 64 <222000000>;
288 opp-hz = /bits/ 64 <333000000>;
291 opp-hz = /bits/ 64 <666000000>;
295 dmc_opp_table: opp-table17 {
296 compatible = "operating-points-v2";
299 opp-hz = /bits/ 64 <165000000>;
300 opp-microvolt = <875000>;
303 opp-hz = /bits/ 64 <206000000>;
304 opp-microvolt = <875000>;
307 opp-hz = /bits/ 64 <275000000>;
308 opp-microvolt = <875000>;
311 opp-hz = /bits/ 64 <413000000>;
312 opp-microvolt = <887500>;
315 opp-hz = /bits/ 64 <543000000>;
316 opp-microvolt = <937500>;
319 opp-hz = /bits/ 64 <633000000>;
320 opp-microvolt = <1012500>;
323 opp-hz = /bits/ 64 <728000000>;
324 opp-microvolt = <1037500>;
327 opp-hz = /bits/ 64 <825000000>;
328 opp-microvolt = <1050000>;
332 samsung_K3QF2F20DB: lpddr3 {
333 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
336 #address-cells = <1>;
349 tW2W-C2C-min-tck = <0>;
350 tR2R-C2C-min-tck = <0>;
352 tDQSCK-min-tck = <5>;
358 tCKESR-min-tck = <2>;
361 timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
362 compatible = "jedec,lpddr3-timings";
363 /* workaround: 'reg' shows max-freq */
365 min-freq = <100000000>;
389 vdd-supply = <&ldo4_reg>;
394 operating-points-v2 = <&bus_wcore_opp_table>;
395 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
396 <&nocp_mem1_0>, <&nocp_mem1_1>;
397 vdd-supply = <&buck3_reg>;
398 exynos,saturation-ratio = <100>;
403 operating-points-v2 = <&bus_noc_opp_table>;
404 devfreq = <&bus_wcore>;
409 operating-points-v2 = <&bus_fsys_apb_opp_table>;
410 devfreq = <&bus_wcore>;
415 operating-points-v2 = <&bus_fsys2_opp_table>;
416 devfreq = <&bus_wcore>;
421 operating-points-v2 = <&bus_mfc_opp_table>;
422 devfreq = <&bus_wcore>;
427 operating-points-v2 = <&bus_gen_opp_table>;
428 devfreq = <&bus_wcore>;
433 operating-points-v2 = <&bus_peri_opp_table>;
434 devfreq = <&bus_wcore>;
439 operating-points-v2 = <&bus_g2d_opp_table>;
440 devfreq = <&bus_wcore>;
445 operating-points-v2 = <&bus_g2d_acp_opp_table>;
446 devfreq = <&bus_wcore>;
451 operating-points-v2 = <&bus_jpeg_opp_table>;
452 devfreq = <&bus_wcore>;
457 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
458 devfreq = <&bus_wcore>;
463 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
464 devfreq = <&bus_wcore>;
469 operating-points-v2 = <&bus_disp1_opp_table>;
470 devfreq = <&bus_wcore>;
475 operating-points-v2 = <&bus_gscl_opp_table>;
476 devfreq = <&bus_wcore>;
481 operating-points-v2 = <&bus_mscl_opp_table>;
482 devfreq = <&bus_wcore>;
487 cpu-supply = <&buck6_reg>;
491 cpu-supply = <&buck2_reg>;
495 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
496 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
497 device-handle = <&samsung_K3QF2F20DB>;
498 operating-points-v2 = <&dmc_opp_table>;
499 vdd-supply = <&buck1_reg>;
507 compatible = "samsung,s2mps11-pmic";
509 samsung,s2mps11-acokb-ground;
511 interrupt-parent = <&gpx0>;
512 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&s2mps11_irq>;
517 s2mps11_osc: clocks {
518 compatible = "samsung,s2mps11-clk";
520 clock-output-names = "s2mps11_ap",
521 "s2mps11_cp", "s2mps11_bt";
526 regulator-name = "vdd_ldo1";
527 regulator-min-microvolt = <1000000>;
528 regulator-max-microvolt = <1000000>;
533 regulator-name = "vdd_ldo2";
534 regulator-min-microvolt = <1800000>;
535 regulator-max-microvolt = <1800000>;
540 regulator-name = "vddq_mmc0";
541 regulator-min-microvolt = <1800000>;
542 regulator-max-microvolt = <1800000>;
546 regulator-name = "vdd_adc";
547 regulator-min-microvolt = <1800000>;
548 regulator-max-microvolt = <1800000>;
550 regulator-state-mem {
551 regulator-off-in-suspend;
556 regulator-name = "vdd_ldo5";
557 regulator-min-microvolt = <1800000>;
558 regulator-max-microvolt = <1800000>;
561 regulator-state-mem {
562 regulator-off-in-suspend;
567 regulator-name = "vdd_ldo6";
568 regulator-min-microvolt = <1000000>;
569 regulator-max-microvolt = <1000000>;
572 regulator-state-mem {
573 regulator-off-in-suspend;
578 regulator-name = "vdd_ldo7";
579 regulator-min-microvolt = <1800000>;
580 regulator-max-microvolt = <1800000>;
583 regulator-state-mem {
584 regulator-off-in-suspend;
589 regulator-name = "vdd_ldo8";
590 regulator-min-microvolt = <1800000>;
591 regulator-max-microvolt = <1800000>;
594 regulator-state-mem {
595 regulator-off-in-suspend;
600 regulator-name = "vdd_ldo9";
601 regulator-min-microvolt = <3000000>;
602 regulator-max-microvolt = <3000000>;
605 regulator-state-mem {
606 regulator-off-in-suspend;
611 regulator-name = "vdd_ldo10";
612 regulator-min-microvolt = <1800000>;
613 regulator-max-microvolt = <1800000>;
616 regulator-state-mem {
617 regulator-off-in-suspend;
622 regulator-name = "vdd_ldo11";
623 regulator-min-microvolt = <1000000>;
624 regulator-max-microvolt = <1000000>;
627 regulator-state-mem {
628 regulator-off-in-suspend;
634 regulator-name = "vdd_ldo12";
635 regulator-min-microvolt = <800000>;
636 regulator-max-microvolt = <2375000>;
640 regulator-name = "vddq_mmc2";
641 regulator-min-microvolt = <1800000>;
642 regulator-max-microvolt = <2800000>;
644 regulator-state-mem {
645 regulator-off-in-suspend;
651 regulator-name = "vdd_ldo14";
652 regulator-min-microvolt = <800000>;
653 regulator-max-microvolt = <3950000>;
657 regulator-name = "vdd_ldo15";
658 regulator-min-microvolt = <3300000>;
659 regulator-max-microvolt = <3300000>;
662 regulator-state-mem {
663 regulator-off-in-suspend;
669 regulator-name = "vdd_ldo16";
670 regulator-min-microvolt = <800000>;
671 regulator-max-microvolt = <3950000>;
675 regulator-name = "vdd_ldo17";
676 regulator-min-microvolt = <3300000>;
677 regulator-max-microvolt = <3300000>;
680 regulator-state-mem {
681 regulator-off-in-suspend;
686 regulator-name = "vdd_emmc_1V8";
687 regulator-min-microvolt = <1800000>;
688 regulator-max-microvolt = <1800000>;
690 regulator-state-mem {
691 regulator-off-in-suspend;
696 regulator-name = "vdd_sd";
697 regulator-min-microvolt = <2800000>;
698 regulator-max-microvolt = <2800000>;
700 regulator-state-mem {
701 regulator-off-in-suspend;
707 regulator-name = "vdd_ldo20";
708 regulator-min-microvolt = <800000>;
709 regulator-max-microvolt = <3950000>;
714 regulator-name = "vdd_ldo21";
715 regulator-min-microvolt = <800000>;
716 regulator-max-microvolt = <3950000>;
721 regulator-name = "vdd_ldo22";
722 regulator-min-microvolt = <800000>;
723 regulator-max-microvolt = <2375000>;
727 regulator-name = "vdd_mifs";
728 regulator-min-microvolt = <1100000>;
729 regulator-max-microvolt = <1100000>;
732 regulator-state-mem {
733 regulator-off-in-suspend;
739 regulator-name = "vdd_ldo24";
740 regulator-min-microvolt = <800000>;
741 regulator-max-microvolt = <3950000>;
746 regulator-name = "vdd_ldo25";
747 regulator-min-microvolt = <800000>;
748 regulator-max-microvolt = <3950000>;
752 /* Used on XU3, XU3-Lite and XU4 */
753 regulator-name = "vdd_ldo26";
754 regulator-min-microvolt = <800000>;
755 regulator-max-microvolt = <3950000>;
757 regulator-state-mem {
758 regulator-off-in-suspend;
763 regulator-name = "vdd_g3ds";
764 regulator-min-microvolt = <1000000>;
765 regulator-max-microvolt = <1000000>;
768 regulator-state-mem {
769 regulator-off-in-suspend;
775 regulator-name = "vdd_ldo28";
776 regulator-min-microvolt = <800000>;
777 regulator-max-microvolt = <3950000>;
779 regulator-state-mem {
780 regulator-off-in-suspend;
786 regulator-name = "vdd_ldo29";
787 regulator-min-microvolt = <800000>;
788 regulator-max-microvolt = <3950000>;
793 regulator-name = "vdd_ldo30";
794 regulator-min-microvolt = <800000>;
795 regulator-max-microvolt = <3950000>;
800 regulator-name = "vdd_ldo31";
801 regulator-min-microvolt = <800000>;
802 regulator-max-microvolt = <3950000>;
807 regulator-name = "vdd_ldo32";
808 regulator-min-microvolt = <800000>;
809 regulator-max-microvolt = <3950000>;
814 regulator-name = "vdd_ldo33";
815 regulator-min-microvolt = <800000>;
816 regulator-max-microvolt = <3950000>;
821 regulator-name = "vdd_ldo34";
822 regulator-min-microvolt = <800000>;
823 regulator-max-microvolt = <3950000>;
828 regulator-name = "vdd_ldo35";
829 regulator-min-microvolt = <800000>;
830 regulator-max-microvolt = <2375000>;
835 regulator-name = "vdd_ldo36";
836 regulator-min-microvolt = <800000>;
837 regulator-max-microvolt = <3950000>;
842 regulator-name = "vdd_ldo37";
843 regulator-min-microvolt = <800000>;
844 regulator-max-microvolt = <3950000>;
849 regulator-name = "vdd_ldo38";
850 regulator-min-microvolt = <800000>;
851 regulator-max-microvolt = <3950000>;
855 regulator-name = "vdd_mif";
856 regulator-min-microvolt = <800000>;
857 regulator-max-microvolt = <1300000>;
861 regulator-state-mem {
862 regulator-off-in-suspend;
867 regulator-name = "vdd_arm";
868 regulator-min-microvolt = <800000>;
869 regulator-max-microvolt = <1500000>;
872 regulator-coupled-with = <&buck3_reg>;
873 regulator-coupled-max-spread = <300000>;
875 regulator-state-mem {
876 regulator-off-in-suspend;
881 regulator-name = "vdd_int";
882 regulator-min-microvolt = <800000>;
883 regulator-max-microvolt = <1400000>;
886 regulator-coupled-with = <&buck2_reg>;
887 regulator-coupled-max-spread = <300000>;
889 regulator-state-mem {
890 regulator-off-in-suspend;
895 regulator-name = "vdd_g3d";
896 regulator-min-microvolt = <800000>;
897 regulator-max-microvolt = <1400000>;
901 regulator-state-mem {
902 regulator-off-in-suspend;
907 regulator-name = "vdd_mem";
908 regulator-min-microvolt = <800000>;
909 regulator-max-microvolt = <1400000>;
915 regulator-name = "vdd_kfc";
916 regulator-min-microvolt = <800000>;
917 regulator-max-microvolt = <1500000>;
921 regulator-state-mem {
922 regulator-off-in-suspend;
927 regulator-name = "vdd_1.35v_ldo";
928 regulator-min-microvolt = <1200000>;
929 regulator-max-microvolt = <1500000>;
935 regulator-name = "vdd_2.0v_ldo";
936 regulator-min-microvolt = <1800000>;
937 regulator-max-microvolt = <2100000>;
943 regulator-name = "vdd_2.8v_ldo";
944 regulator-min-microvolt = <3000000>;
945 regulator-max-microvolt = <3750000>;
949 regulator-state-mem {
950 regulator-off-in-suspend;
955 regulator-name = "vdd_vmem";
956 regulator-min-microvolt = <2850000>;
957 regulator-max-microvolt = <2850000>;
959 regulator-state-mem {
960 regulator-off-in-suspend;
969 card-detect-delay = <200>;
970 samsung,dw-mshc-ciu-div = <3>;
971 samsung,dw-mshc-sdr-timing = <0 4>;
972 samsung,dw-mshc-ddr-timing = <0 2>;
973 pinctrl-names = "default";
974 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
977 max-frequency = <200000000>;
978 vmmc-supply = <&ldo19_reg>;
979 vqmmc-supply = <&ldo13_reg>;
1002 s2mps11_irq: s2mps11-irq {
1003 samsung,pins = "gpx0-4";
1004 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
1005 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1006 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1027 vtmu-supply = <&ldo7_reg>;
1031 vtmu-supply = <&ldo7_reg>;
1035 vtmu-supply = <&ldo7_reg>;
1039 vtmu-supply = <&ldo7_reg>;
1043 vtmu-supply = <&ldo7_reg>;
1047 mali-supply = <&buck4_reg>;
1053 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
1054 clock-names = "rtc", "rtc_src";
1061 /* usbdrd_dwc3_1 mode customized in each board */
1064 vdd33-supply = <&ldo9_reg>;
1065 vdd10-supply = <&ldo11_reg>;
1069 vdd33-supply = <&ldo9_reg>;
1070 vdd10-supply = <&ldo11_reg>;