1 // SPDX-License-Identifier: GPL-2.0
3 * SAMSUNG EXYNOS5420 SoC device tree source
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
9 * EXYNOS5420 based board files can include this file and provide
10 * values for board specfic bindings.
13 #include "exynos54xx.dtsi"
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "samsung,exynos5420", "samsung,exynos5";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
41 * The 'cpus' node is not present here but instead it is provided
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
46 cluster_a15_opp_table: opp_table0 {
47 compatible = "operating-points-v2";
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000>;
52 clock-latency-ns = <140000>;
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500>;
57 clock-latency-ns = <140000>;
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000>;
62 clock-latency-ns = <140000>;
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500>;
67 clock-latency-ns = <140000>;
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500>;
72 clock-latency-ns = <140000>;
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500>;
77 clock-latency-ns = <140000>;
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500>;
82 clock-latency-ns = <140000>;
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500>;
87 clock-latency-ns = <140000>;
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500>;
92 clock-latency-ns = <140000>;
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500>;
97 clock-latency-ns = <140000>;
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500>;
102 clock-latency-ns = <140000>;
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500>;
107 clock-latency-ns = <140000>;
111 cluster_a7_opp_table: opp_table1 {
112 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <1300000000>;
116 opp-microvolt = <1275000>;
117 clock-latency-ns = <140000>;
120 opp-hz = /bits/ 64 <1200000000>;
121 opp-microvolt = <1212500>;
122 clock-latency-ns = <140000>;
125 opp-hz = /bits/ 64 <1100000000>;
126 opp-microvolt = <1162500>;
127 clock-latency-ns = <140000>;
130 opp-hz = /bits/ 64 <1000000000>;
131 opp-microvolt = <1112500>;
132 clock-latency-ns = <140000>;
135 opp-hz = /bits/ 64 <900000000>;
136 opp-microvolt = <1062500>;
137 clock-latency-ns = <140000>;
140 opp-hz = /bits/ 64 <800000000>;
141 opp-microvolt = <1025000>;
142 clock-latency-ns = <140000>;
145 opp-hz = /bits/ 64 <700000000>;
146 opp-microvolt = <975000>;
147 clock-latency-ns = <140000>;
150 opp-hz = /bits/ 64 <600000000>;
151 opp-microvolt = <937500>;
152 clock-latency-ns = <140000>;
157 compatible = "arm,cci-400";
158 #address-cells = <1>;
160 reg = <0x10d20000 0x1000>;
161 ranges = <0x0 0x10d20000 0x6000>;
163 cci_control0: slave-if@4000 {
164 compatible = "arm,cci-400-ctrl-if";
165 interface-type = "ace";
166 reg = <0x4000 0x1000>;
168 cci_control1: slave-if@5000 {
169 compatible = "arm,cci-400-ctrl-if";
170 interface-type = "ace";
171 reg = <0x5000 0x1000>;
175 clock: clock-controller@10010000 {
176 compatible = "samsung,exynos5420-clock";
177 reg = <0x10010000 0x30000>;
181 clock_audss: audss-clock-controller@3810000 {
182 compatible = "samsung,exynos5420-audss-clock";
183 reg = <0x03810000 0x0C>;
185 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
186 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
187 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
188 power-domains = <&mau_pd>;
191 mfc: codec@11000000 {
192 compatible = "samsung,mfc-v7";
193 reg = <0x11000000 0x10000>;
194 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clock CLK_MFC>;
197 power-domains = <&mfc_pd>;
198 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
199 iommu-names = "left", "right";
202 mmc_0: mmc@12200000 {
203 compatible = "samsung,exynos5420-dw-mshc-smu";
204 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
207 reg = <0x12200000 0x2000>;
208 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
209 clock-names = "biu", "ciu";
214 mmc_1: mmc@12210000 {
215 compatible = "samsung,exynos5420-dw-mshc-smu";
216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
217 #address-cells = <1>;
219 reg = <0x12210000 0x2000>;
220 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
221 clock-names = "biu", "ciu";
226 mmc_2: mmc@12220000 {
227 compatible = "samsung,exynos5420-dw-mshc";
228 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
229 #address-cells = <1>;
231 reg = <0x12220000 0x1000>;
232 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
233 clock-names = "biu", "ciu";
238 nocp_mem0_0: nocp@10ca1000 {
239 compatible = "samsung,exynos5420-nocp";
240 reg = <0x10CA1000 0x200>;
244 nocp_mem0_1: nocp@10ca1400 {
245 compatible = "samsung,exynos5420-nocp";
246 reg = <0x10CA1400 0x200>;
250 nocp_mem1_0: nocp@10ca1800 {
251 compatible = "samsung,exynos5420-nocp";
252 reg = <0x10CA1800 0x200>;
256 nocp_mem1_1: nocp@10ca1c00 {
257 compatible = "samsung,exynos5420-nocp";
258 reg = <0x10CA1C00 0x200>;
262 nocp_g3d_0: nocp@11a51000 {
263 compatible = "samsung,exynos5420-nocp";
264 reg = <0x11A51000 0x200>;
268 nocp_g3d_1: nocp@11a51400 {
269 compatible = "samsung,exynos5420-nocp";
270 reg = <0x11A51400 0x200>;
274 gsc_pd: power-domain@10044000 {
275 compatible = "samsung,exynos4210-pd";
276 reg = <0x10044000 0x20>;
277 #power-domain-cells = <0>;
279 clocks = <&clock CLK_FIN_PLL>,
280 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
281 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
282 clock-names = "oscclk", "clk0", "asb0", "asb1";
285 isp_pd: power-domain@10044020 {
286 compatible = "samsung,exynos4210-pd";
287 reg = <0x10044020 0x20>;
288 #power-domain-cells = <0>;
292 mfc_pd: power-domain@10044060 {
293 compatible = "samsung,exynos4210-pd";
294 reg = <0x10044060 0x20>;
295 clocks = <&clock CLK_FIN_PLL>,
296 <&clock CLK_MOUT_USER_ACLK333>,
297 <&clock CLK_ACLK333>;
298 clock-names = "oscclk", "clk0","asb0";
299 #power-domain-cells = <0>;
303 msc_pd: power-domain@10044120 {
304 compatible = "samsung,exynos4210-pd";
305 reg = <0x10044120 0x20>;
306 #power-domain-cells = <0>;
310 disp_pd: power-domain@100440c0 {
311 compatible = "samsung,exynos4210-pd";
312 reg = <0x100440C0 0x20>;
313 #power-domain-cells = <0>;
315 clocks = <&clock CLK_FIN_PLL>,
316 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
317 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
318 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
319 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
320 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
323 mau_pd: power-domain@100440e0 {
324 compatible = "samsung,exynos4210-pd";
325 reg = <0x100440E0 0x20>;
326 #power-domain-cells = <0>;
330 pinctrl_0: pinctrl@13400000 {
331 compatible = "samsung,exynos5420-pinctrl";
332 reg = <0x13400000 0x1000>;
333 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
335 wakeup-interrupt-controller {
336 compatible = "samsung,exynos4210-wakeup-eint";
337 interrupt-parent = <&gic>;
338 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
342 pinctrl_1: pinctrl@13410000 {
343 compatible = "samsung,exynos5420-pinctrl";
344 reg = <0x13410000 0x1000>;
345 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
348 pinctrl_2: pinctrl@14000000 {
349 compatible = "samsung,exynos5420-pinctrl";
350 reg = <0x14000000 0x1000>;
351 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
354 pinctrl_3: pinctrl@14010000 {
355 compatible = "samsung,exynos5420-pinctrl";
356 reg = <0x14010000 0x1000>;
357 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
360 pinctrl_4: pinctrl@3860000 {
361 compatible = "samsung,exynos5420-pinctrl";
362 reg = <0x03860000 0x1000>;
363 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
364 power-domains = <&mau_pd>;
368 #address-cells = <1>;
370 compatible = "simple-bus";
371 interrupt-parent = <&gic>;
375 compatible = "arm,pl330", "arm,primecell";
376 reg = <0x03880000 0x1000>;
377 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clock_audss EXYNOS_ADMA>;
379 clock-names = "apb_pclk";
382 #dma-requests = <16>;
383 power-domains = <&mau_pd>;
386 pdma0: pdma@121a0000 {
387 compatible = "arm,pl330", "arm,primecell";
388 reg = <0x121A0000 0x1000>;
389 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clock CLK_PDMA0>;
391 clock-names = "apb_pclk";
394 #dma-requests = <32>;
397 pdma1: pdma@121b0000 {
398 compatible = "arm,pl330", "arm,primecell";
399 reg = <0x121B0000 0x1000>;
400 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&clock CLK_PDMA1>;
402 clock-names = "apb_pclk";
405 #dma-requests = <32>;
408 mdma0: mdma@10800000 {
409 compatible = "arm,pl330", "arm,primecell";
410 reg = <0x10800000 0x1000>;
411 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clock CLK_MDMA0>;
413 clock-names = "apb_pclk";
419 mdma1: mdma@11c10000 {
420 compatible = "arm,pl330", "arm,primecell";
421 reg = <0x11C10000 0x1000>;
422 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&clock CLK_MDMA1>;
424 clock-names = "apb_pclk";
429 * MDMA1 can support both secure and non-secure
430 * AXI transactions. When this is enabled in
431 * the kernel for boards that run in secure
432 * mode, we are getting imprecise external
433 * aborts causing the kernel to oops.
440 compatible = "samsung,exynos5420-i2s";
441 reg = <0x03830000 0x100>;
445 dma-names = "tx", "rx", "tx-sec";
446 clocks = <&clock_audss EXYNOS_I2S_BUS>,
447 <&clock_audss EXYNOS_I2S_BUS>,
448 <&clock_audss EXYNOS_SCLK_I2S>;
449 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
451 clock-output-names = "i2s_cdclk0";
452 #sound-dai-cells = <1>;
453 samsung,idma-addr = <0x03000000>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&i2s0_bus>;
456 power-domains = <&mau_pd>;
461 compatible = "samsung,exynos5420-i2s";
462 reg = <0x12D60000 0x100>;
465 dma-names = "tx", "rx";
466 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
467 clock-names = "iis", "i2s_opclk0";
469 clock-output-names = "i2s_cdclk1";
470 #sound-dai-cells = <1>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2s1_bus>;
477 compatible = "samsung,exynos5420-i2s";
478 reg = <0x12D70000 0x100>;
481 dma-names = "tx", "rx";
482 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
483 clock-names = "iis", "i2s_opclk0";
485 clock-output-names = "i2s_cdclk2";
486 #sound-dai-cells = <1>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&i2s2_bus>;
492 spi_0: spi@12d20000 {
493 compatible = "samsung,exynos4210-spi";
494 reg = <0x12d20000 0x100>;
495 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
498 dma-names = "tx", "rx";
499 #address-cells = <1>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&spi0_bus>;
503 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
504 clock-names = "spi", "spi_busclk0";
508 spi_1: spi@12d30000 {
509 compatible = "samsung,exynos4210-spi";
510 reg = <0x12d30000 0x100>;
511 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
514 dma-names = "tx", "rx";
515 #address-cells = <1>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&spi1_bus>;
519 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
520 clock-names = "spi", "spi_busclk0";
524 spi_2: spi@12d40000 {
525 compatible = "samsung,exynos4210-spi";
526 reg = <0x12d40000 0x100>;
527 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
530 dma-names = "tx", "rx";
531 #address-cells = <1>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&spi2_bus>;
535 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
536 clock-names = "spi", "spi_busclk0";
540 dp_phy: dp-video-phy {
541 compatible = "samsung,exynos5420-dp-video-phy";
542 samsung,pmu-syscon = <&pmu_system_controller>;
546 mipi_phy: mipi-video-phy {
547 compatible = "samsung,s5pv210-mipi-video-phy";
548 syscon = <&pmu_system_controller>;
553 compatible = "samsung,exynos5410-mipi-dsi";
554 reg = <0x14500000 0x10000>;
555 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
556 phys = <&mipi_phy 1>;
558 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
559 clock-names = "bus_clk", "pll_clk";
560 #address-cells = <1>;
566 compatible = "samsung,exynos-adc-v2";
567 reg = <0x12D10000 0x100>;
568 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&clock CLK_TSADC>;
571 #io-channel-cells = <1>;
573 samsung,syscon-phandle = <&pmu_system_controller>;
577 hsi2c_8: i2c@12e00000 {
578 compatible = "samsung,exynos5250-hsi2c";
579 reg = <0x12E00000 0x1000>;
580 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
581 #address-cells = <1>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c8_hs_bus>;
585 clocks = <&clock CLK_USI4>;
586 clock-names = "hsi2c";
590 hsi2c_9: i2c@12e10000 {
591 compatible = "samsung,exynos5250-hsi2c";
592 reg = <0x12E10000 0x1000>;
593 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
594 #address-cells = <1>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c9_hs_bus>;
598 clocks = <&clock CLK_USI5>;
599 clock-names = "hsi2c";
603 hsi2c_10: i2c@12e20000 {
604 compatible = "samsung,exynos5250-hsi2c";
605 reg = <0x12E20000 0x1000>;
606 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
607 #address-cells = <1>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&i2c10_hs_bus>;
611 clocks = <&clock CLK_USI6>;
612 clock-names = "hsi2c";
616 hdmi: hdmi@14530000 {
617 compatible = "samsung,exynos5420-hdmi";
618 reg = <0x14530000 0x70000>;
619 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
621 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
622 <&clock CLK_MOUT_HDMI>;
623 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
624 "sclk_hdmiphy", "mout_hdmi";
626 samsung,syscon-phandle = <&pmu_system_controller>;
628 power-domains = <&disp_pd>;
629 #sound-dai-cells = <0>;
632 hdmiphy: hdmiphy@145d0000 {
633 reg = <0x145D0000 0x20>;
636 hdmicec: cec@101b0000 {
637 compatible = "samsung,s5p-cec";
638 reg = <0x101B0000 0x200>;
639 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&clock CLK_HDMI_CEC>;
641 clock-names = "hdmicec";
642 samsung,syscon-phandle = <&pmu_system_controller>;
643 hdmi-phandle = <&hdmi>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&hdmi_cec>;
649 mixer: mixer@14450000 {
650 compatible = "samsung,exynos5420-mixer";
651 reg = <0x14450000 0x10000>;
652 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
654 <&clock CLK_SCLK_HDMI>;
655 clock-names = "mixer", "hdmi", "sclk_hdmi";
656 power-domains = <&disp_pd>;
657 iommus = <&sysmmu_tv>;
661 rotator: rotator@11c00000 {
662 compatible = "samsung,exynos5250-rotator";
663 reg = <0x11C00000 0x64>;
664 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&clock CLK_ROTATOR>;
666 clock-names = "rotator";
667 iommus = <&sysmmu_rotator>;
670 gsc_0: video-scaler@13e00000 {
671 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
672 reg = <0x13e00000 0x1000>;
673 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&clock CLK_GSCL0>;
675 clock-names = "gscl";
676 power-domains = <&gsc_pd>;
677 iommus = <&sysmmu_gscl0>;
680 gsc_1: video-scaler@13e10000 {
681 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
682 reg = <0x13e10000 0x1000>;
683 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&clock CLK_GSCL1>;
685 clock-names = "gscl";
686 power-domains = <&gsc_pd>;
687 iommus = <&sysmmu_gscl1>;
690 jpeg_0: jpeg@11f50000 {
691 compatible = "samsung,exynos5420-jpeg";
692 reg = <0x11F50000 0x1000>;
693 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
694 clock-names = "jpeg";
695 clocks = <&clock CLK_JPEG>;
696 iommus = <&sysmmu_jpeg0>;
699 jpeg_1: jpeg@11f60000 {
700 compatible = "samsung,exynos5420-jpeg";
701 reg = <0x11F60000 0x1000>;
702 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
703 clock-names = "jpeg";
704 clocks = <&clock CLK_JPEG2>;
705 iommus = <&sysmmu_jpeg1>;
708 pmu_system_controller: system-controller@10040000 {
709 compatible = "samsung,exynos5420-pmu", "syscon";
710 reg = <0x10040000 0x5000>;
711 clock-names = "clkout16";
712 clocks = <&clock CLK_FIN_PLL>;
714 interrupt-controller;
715 #interrupt-cells = <3>;
716 interrupt-parent = <&gic>;
719 tmu_cpu0: tmu@10060000 {
720 compatible = "samsung,exynos5420-tmu";
721 reg = <0x10060000 0x100>;
722 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clock CLK_TMU>;
724 clock-names = "tmu_apbif";
725 #include "exynos5420-tmu-sensor-conf.dtsi"
728 tmu_cpu1: tmu@10064000 {
729 compatible = "samsung,exynos5420-tmu";
730 reg = <0x10064000 0x100>;
731 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clock CLK_TMU>;
733 clock-names = "tmu_apbif";
734 #include "exynos5420-tmu-sensor-conf.dtsi"
737 tmu_cpu2: tmu@10068000 {
738 compatible = "samsung,exynos5420-tmu-ext-triminfo";
739 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
740 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
742 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
743 #include "exynos5420-tmu-sensor-conf.dtsi"
746 tmu_cpu3: tmu@1006c000 {
747 compatible = "samsung,exynos5420-tmu-ext-triminfo";
748 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
749 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
751 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
752 #include "exynos5420-tmu-sensor-conf.dtsi"
755 tmu_gpu: tmu@100a0000 {
756 compatible = "samsung,exynos5420-tmu-ext-triminfo";
757 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
758 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
760 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
761 #include "exynos5420-tmu-sensor-conf.dtsi"
764 sysmmu_g2dr: sysmmu@0x10A60000 {
765 compatible = "samsung,exynos-sysmmu";
766 reg = <0x10A60000 0x1000>;
767 interrupt-parent = <&combiner>;
769 clock-names = "sysmmu", "master";
770 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
774 sysmmu_g2dw: sysmmu@0x10A70000 {
775 compatible = "samsung,exynos-sysmmu";
776 reg = <0x10A70000 0x1000>;
777 interrupt-parent = <&combiner>;
779 clock-names = "sysmmu", "master";
780 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
784 sysmmu_tv: sysmmu@0x14650000 {
785 compatible = "samsung,exynos-sysmmu";
786 reg = <0x14650000 0x1000>;
787 interrupt-parent = <&combiner>;
789 clock-names = "sysmmu", "master";
790 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
791 power-domains = <&disp_pd>;
795 sysmmu_gscl0: sysmmu@0x13E80000 {
796 compatible = "samsung,exynos-sysmmu";
797 reg = <0x13E80000 0x1000>;
798 interrupt-parent = <&combiner>;
800 clock-names = "sysmmu", "master";
801 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
802 power-domains = <&gsc_pd>;
806 sysmmu_gscl1: sysmmu@0x13E90000 {
807 compatible = "samsung,exynos-sysmmu";
808 reg = <0x13E90000 0x1000>;
809 interrupt-parent = <&combiner>;
811 clock-names = "sysmmu", "master";
812 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
813 power-domains = <&gsc_pd>;
817 sysmmu_scaler0r: sysmmu@0x12880000 {
818 compatible = "samsung,exynos-sysmmu";
819 reg = <0x12880000 0x1000>;
820 interrupt-parent = <&combiner>;
822 clock-names = "sysmmu", "master";
823 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
827 sysmmu_scaler1r: sysmmu@0x12890000 {
828 compatible = "samsung,exynos-sysmmu";
829 reg = <0x12890000 0x1000>;
830 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
831 clock-names = "sysmmu", "master";
832 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
836 sysmmu_scaler2r: sysmmu@0x128A0000 {
837 compatible = "samsung,exynos-sysmmu";
838 reg = <0x128A0000 0x1000>;
839 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
840 clock-names = "sysmmu", "master";
841 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
845 sysmmu_scaler0w: sysmmu@0x128C0000 {
846 compatible = "samsung,exynos-sysmmu";
847 reg = <0x128C0000 0x1000>;
848 interrupt-parent = <&combiner>;
850 clock-names = "sysmmu", "master";
851 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
855 sysmmu_scaler1w: sysmmu@0x128D0000 {
856 compatible = "samsung,exynos-sysmmu";
857 reg = <0x128D0000 0x1000>;
858 interrupt-parent = <&combiner>;
860 clock-names = "sysmmu", "master";
861 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
865 sysmmu_scaler2w: sysmmu@0x128E0000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x128E0000 0x1000>;
868 interrupt-parent = <&combiner>;
870 clock-names = "sysmmu", "master";
871 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
875 sysmmu_rotator: sysmmu@0x11D40000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x11D40000 0x1000>;
878 interrupt-parent = <&combiner>;
880 clock-names = "sysmmu", "master";
881 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
885 sysmmu_jpeg0: sysmmu@0x11F10000 {
886 compatible = "samsung,exynos-sysmmu";
887 reg = <0x11F10000 0x1000>;
888 interrupt-parent = <&combiner>;
890 clock-names = "sysmmu", "master";
891 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
895 sysmmu_jpeg1: sysmmu@0x11F20000 {
896 compatible = "samsung,exynos-sysmmu";
897 reg = <0x11F20000 0x1000>;
898 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
899 clock-names = "sysmmu", "master";
900 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
904 sysmmu_mfc_l: sysmmu@0x11200000 {
905 compatible = "samsung,exynos-sysmmu";
906 reg = <0x11200000 0x1000>;
907 interrupt-parent = <&combiner>;
909 clock-names = "sysmmu", "master";
910 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
911 power-domains = <&mfc_pd>;
915 sysmmu_mfc_r: sysmmu@0x11210000 {
916 compatible = "samsung,exynos-sysmmu";
917 reg = <0x11210000 0x1000>;
918 interrupt-parent = <&combiner>;
920 clock-names = "sysmmu", "master";
921 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
922 power-domains = <&mfc_pd>;
926 sysmmu_fimd1_0: sysmmu@0x14640000 {
927 compatible = "samsung,exynos-sysmmu";
928 reg = <0x14640000 0x1000>;
929 interrupt-parent = <&combiner>;
931 clock-names = "sysmmu", "master";
932 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
933 power-domains = <&disp_pd>;
937 sysmmu_fimd1_1: sysmmu@0x14680000 {
938 compatible = "samsung,exynos-sysmmu";
939 reg = <0x14680000 0x1000>;
940 interrupt-parent = <&combiner>;
942 clock-names = "sysmmu", "master";
943 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
944 power-domains = <&disp_pd>;
948 bus_wcore: bus_wcore {
949 compatible = "samsung,exynos-bus";
950 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
952 operating-points-v2 = <&bus_wcore_opp_table>;
957 compatible = "samsung,exynos-bus";
958 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
960 operating-points-v2 = <&bus_noc_opp_table>;
964 bus_fsys_apb: bus_fsys_apb {
965 compatible = "samsung,exynos-bus";
966 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
968 operating-points-v2 = <&bus_fsys_apb_opp_table>;
973 compatible = "samsung,exynos-bus";
974 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
976 operating-points-v2 = <&bus_fsys_apb_opp_table>;
980 bus_fsys2: bus_fsys2 {
981 compatible = "samsung,exynos-bus";
982 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
984 operating-points-v2 = <&bus_fsys2_opp_table>;
989 compatible = "samsung,exynos-bus";
990 clocks = <&clock CLK_DOUT_ACLK333>;
992 operating-points-v2 = <&bus_mfc_opp_table>;
997 compatible = "samsung,exynos-bus";
998 clocks = <&clock CLK_DOUT_ACLK266>;
1000 operating-points-v2 = <&bus_gen_opp_table>;
1001 status = "disabled";
1004 bus_peri: bus_peri {
1005 compatible = "samsung,exynos-bus";
1006 clocks = <&clock CLK_DOUT_ACLK66>;
1007 clock-names = "bus";
1008 operating-points-v2 = <&bus_peri_opp_table>;
1009 status = "disabled";
1013 compatible = "samsung,exynos-bus";
1014 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1015 clock-names = "bus";
1016 operating-points-v2 = <&bus_g2d_opp_table>;
1017 status = "disabled";
1020 bus_g2d_acp: bus_g2d_acp {
1021 compatible = "samsung,exynos-bus";
1022 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1023 clock-names = "bus";
1024 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1025 status = "disabled";
1028 bus_jpeg: bus_jpeg {
1029 compatible = "samsung,exynos-bus";
1030 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1031 clock-names = "bus";
1032 operating-points-v2 = <&bus_jpeg_opp_table>;
1033 status = "disabled";
1036 bus_jpeg_apb: bus_jpeg_apb {
1037 compatible = "samsung,exynos-bus";
1038 clocks = <&clock CLK_DOUT_ACLK166>;
1039 clock-names = "bus";
1040 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1041 status = "disabled";
1044 bus_disp1_fimd: bus_disp1_fimd {
1045 compatible = "samsung,exynos-bus";
1046 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1047 clock-names = "bus";
1048 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1049 status = "disabled";
1052 bus_disp1: bus_disp1 {
1053 compatible = "samsung,exynos-bus";
1054 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1055 clock-names = "bus";
1056 operating-points-v2 = <&bus_disp1_opp_table>;
1057 status = "disabled";
1060 bus_gscl_scaler: bus_gscl_scaler {
1061 compatible = "samsung,exynos-bus";
1062 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1063 clock-names = "bus";
1064 operating-points-v2 = <&bus_gscl_opp_table>;
1065 status = "disabled";
1068 bus_mscl: bus_mscl {
1069 compatible = "samsung,exynos-bus";
1070 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1071 clock-names = "bus";
1072 operating-points-v2 = <&bus_mscl_opp_table>;
1073 status = "disabled";
1076 bus_wcore_opp_table: opp_table2 {
1077 compatible = "operating-points-v2";
1080 opp-hz = /bits/ 64 <84000000>;
1081 opp-microvolt = <925000>;
1084 opp-hz = /bits/ 64 <111000000>;
1085 opp-microvolt = <950000>;
1088 opp-hz = /bits/ 64 <222000000>;
1089 opp-microvolt = <950000>;
1092 opp-hz = /bits/ 64 <333000000>;
1093 opp-microvolt = <950000>;
1096 opp-hz = /bits/ 64 <400000000>;
1097 opp-microvolt = <987500>;
1101 bus_noc_opp_table: opp_table3 {
1102 compatible = "operating-points-v2";
1105 opp-hz = /bits/ 64 <67000000>;
1108 opp-hz = /bits/ 64 <75000000>;
1111 opp-hz = /bits/ 64 <86000000>;
1114 opp-hz = /bits/ 64 <100000000>;
1118 bus_fsys_apb_opp_table: opp_table4 {
1119 compatible = "operating-points-v2";
1123 opp-hz = /bits/ 64 <100000000>;
1126 opp-hz = /bits/ 64 <200000000>;
1130 bus_fsys2_opp_table: opp_table5 {
1131 compatible = "operating-points-v2";
1134 opp-hz = /bits/ 64 <75000000>;
1137 opp-hz = /bits/ 64 <100000000>;
1140 opp-hz = /bits/ 64 <150000000>;
1144 bus_mfc_opp_table: opp_table6 {
1145 compatible = "operating-points-v2";
1148 opp-hz = /bits/ 64 <96000000>;
1151 opp-hz = /bits/ 64 <111000000>;
1154 opp-hz = /bits/ 64 <167000000>;
1157 opp-hz = /bits/ 64 <222000000>;
1160 opp-hz = /bits/ 64 <333000000>;
1164 bus_gen_opp_table: opp_table7 {
1165 compatible = "operating-points-v2";
1168 opp-hz = /bits/ 64 <89000000>;
1171 opp-hz = /bits/ 64 <133000000>;
1174 opp-hz = /bits/ 64 <178000000>;
1177 opp-hz = /bits/ 64 <267000000>;
1181 bus_peri_opp_table: opp_table8 {
1182 compatible = "operating-points-v2";
1185 opp-hz = /bits/ 64 <67000000>;
1189 bus_g2d_opp_table: opp_table9 {
1190 compatible = "operating-points-v2";
1193 opp-hz = /bits/ 64 <84000000>;
1196 opp-hz = /bits/ 64 <167000000>;
1199 opp-hz = /bits/ 64 <222000000>;
1202 opp-hz = /bits/ 64 <300000000>;
1205 opp-hz = /bits/ 64 <333000000>;
1209 bus_g2d_acp_opp_table: opp_table10 {
1210 compatible = "operating-points-v2";
1213 opp-hz = /bits/ 64 <67000000>;
1216 opp-hz = /bits/ 64 <133000000>;
1219 opp-hz = /bits/ 64 <178000000>;
1222 opp-hz = /bits/ 64 <267000000>;
1226 bus_jpeg_opp_table: opp_table11 {
1227 compatible = "operating-points-v2";
1230 opp-hz = /bits/ 64 <75000000>;
1233 opp-hz = /bits/ 64 <150000000>;
1236 opp-hz = /bits/ 64 <200000000>;
1239 opp-hz = /bits/ 64 <300000000>;
1243 bus_jpeg_apb_opp_table: opp_table12 {
1244 compatible = "operating-points-v2";
1247 opp-hz = /bits/ 64 <84000000>;
1250 opp-hz = /bits/ 64 <111000000>;
1253 opp-hz = /bits/ 64 <134000000>;
1256 opp-hz = /bits/ 64 <167000000>;
1260 bus_disp1_fimd_opp_table: opp_table13 {
1261 compatible = "operating-points-v2";
1264 opp-hz = /bits/ 64 <120000000>;
1267 opp-hz = /bits/ 64 <200000000>;
1271 bus_disp1_opp_table: opp_table14 {
1272 compatible = "operating-points-v2";
1275 opp-hz = /bits/ 64 <120000000>;
1278 opp-hz = /bits/ 64 <200000000>;
1281 opp-hz = /bits/ 64 <300000000>;
1285 bus_gscl_opp_table: opp_table15 {
1286 compatible = "operating-points-v2";
1289 opp-hz = /bits/ 64 <150000000>;
1292 opp-hz = /bits/ 64 <200000000>;
1295 opp-hz = /bits/ 64 <300000000>;
1299 bus_mscl_opp_table: opp_table16 {
1300 compatible = "operating-points-v2";
1303 opp-hz = /bits/ 64 <84000000>;
1306 opp-hz = /bits/ 64 <167000000>;
1309 opp-hz = /bits/ 64 <222000000>;
1312 opp-hz = /bits/ 64 <333000000>;
1315 opp-hz = /bits/ 64 <400000000>;
1321 cpu0_thermal: cpu0-thermal {
1322 thermal-sensors = <&tmu_cpu0>;
1323 #include "exynos5420-trip-points.dtsi"
1325 cpu1_thermal: cpu1-thermal {
1326 thermal-sensors = <&tmu_cpu1>;
1327 #include "exynos5420-trip-points.dtsi"
1329 cpu2_thermal: cpu2-thermal {
1330 thermal-sensors = <&tmu_cpu2>;
1331 #include "exynos5420-trip-points.dtsi"
1333 cpu3_thermal: cpu3-thermal {
1334 thermal-sensors = <&tmu_cpu3>;
1335 #include "exynos5420-trip-points.dtsi"
1337 gpu_thermal: gpu-thermal {
1338 thermal-sensors = <&tmu_gpu>;
1339 #include "exynos5420-trip-points.dtsi"
1345 clocks = <&clock CLK_DP1>;
1349 power-domains = <&disp_pd>;
1353 compatible = "samsung,exynos5420-fimd";
1354 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1355 clock-names = "sclk_fimd", "fimd";
1356 power-domains = <&disp_pd>;
1357 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1358 iommu-names = "m0", "m1";
1362 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1363 clocks = <&clock CLK_G2D>;
1364 clock-names = "fimg2d";
1369 clocks = <&clock CLK_I2C0>;
1370 clock-names = "i2c";
1371 pinctrl-names = "default";
1372 pinctrl-0 = <&i2c0_bus>;
1376 clocks = <&clock CLK_I2C1>;
1377 clock-names = "i2c";
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&i2c1_bus>;
1383 clocks = <&clock CLK_I2C2>;
1384 clock-names = "i2c";
1385 pinctrl-names = "default";
1386 pinctrl-0 = <&i2c2_bus>;
1390 clocks = <&clock CLK_I2C3>;
1391 clock-names = "i2c";
1392 pinctrl-names = "default";
1393 pinctrl-0 = <&i2c3_bus>;
1397 clocks = <&clock CLK_USI0>;
1398 clock-names = "hsi2c";
1399 pinctrl-names = "default";
1400 pinctrl-0 = <&i2c4_hs_bus>;
1404 clocks = <&clock CLK_USI1>;
1405 clock-names = "hsi2c";
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&i2c5_hs_bus>;
1411 clocks = <&clock CLK_USI2>;
1412 clock-names = "hsi2c";
1413 pinctrl-names = "default";
1414 pinctrl-0 = <&i2c6_hs_bus>;
1418 clocks = <&clock CLK_USI3>;
1419 clock-names = "hsi2c";
1420 pinctrl-names = "default";
1421 pinctrl-0 = <&i2c7_hs_bus>;
1425 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1426 clock-names = "fin_pll", "mct";
1430 clocks = <&clock CLK_SSS>;
1431 clock-names = "secss";
1435 clocks = <&clock CLK_PWM>;
1436 clock-names = "timers";
1440 clocks = <&clock CLK_RTC>;
1441 clock-names = "rtc";
1442 interrupt-parent = <&pmu_system_controller>;
1443 status = "disabled";
1447 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1448 clock-names = "uart", "clk_uart_baud0";
1449 dmas = <&pdma0 13>, <&pdma0 14>;
1450 dma-names = "rx", "tx";
1454 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1455 clock-names = "uart", "clk_uart_baud0";
1456 dmas = <&pdma1 15>, <&pdma1 16>;
1457 dma-names = "rx", "tx";
1461 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1462 clock-names = "uart", "clk_uart_baud0";
1463 dmas = <&pdma0 15>, <&pdma0 16>;
1464 dma-names = "rx", "tx";
1468 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1469 clock-names = "uart", "clk_uart_baud0";
1470 dmas = <&pdma1 17>, <&pdma1 18>;
1471 dma-names = "rx", "tx";
1475 clocks = <&clock CLK_SSS>;
1476 clock-names = "secss";
1480 clocks = <&clock CLK_SSS>;
1481 clock-names = "secss";
1485 clocks = <&clock CLK_USBD300>;
1486 clock-names = "usbdrd30";
1490 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1491 clock-names = "phy", "ref";
1492 samsung,pmu-syscon = <&pmu_system_controller>;
1496 clocks = <&clock CLK_USBD301>;
1497 clock-names = "usbdrd30";
1501 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1506 clock-names = "phy", "ref";
1507 samsung,pmu-syscon = <&pmu_system_controller>;
1511 clocks = <&clock CLK_USBH20>;
1512 clock-names = "usbhost";
1516 clocks = <&clock CLK_USBH20>;
1517 clock-names = "usbhost";
1521 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1522 clock-names = "phy", "ref";
1523 samsung,sysreg-phandle = <&sysreg_system_controller>;
1524 samsung,pmureg-phandle = <&pmu_system_controller>;
1528 clocks = <&clock CLK_WDT>;
1529 clock-names = "watchdog";
1530 samsung,syscon-phandle = <&pmu_system_controller>;
1533 #include "exynos5420-pinctrl.dtsi"