arch/arm/boot/dts/exynos5420.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos5420 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung Exynos5420 SoC device nodes are listed in this file.
   9  * Exynos5420 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  */
  12
  13 #include "exynos54xx.dtsi"
  14 #include <dt-bindings/clock/exynos5420.h>
  15 #include <dt-bindings/clock/exynos-audss-clk.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         compatible = "samsung,exynos5420", "samsung,exynos5";
  20
  21         aliases {
  22                 mshc0 = &mmc_0;
  23                 mshc1 = &mmc_1;
  24                 mshc2 = &mmc_2;
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 pinctrl4 = &pinctrl_4;
  30                 i2c8 = &hsi2c_8;
  31                 i2c9 = &hsi2c_9;
  32                 i2c10 = &hsi2c_10;
  33                 gsc0 = &gsc_0;
  34                 gsc1 = &gsc_1;
  35                 spi0 = &spi_0;
  36                 spi1 = &spi_1;
  37                 spi2 = &spi_2;
  38         };
  39
  40         bus_disp1: bus-disp1 {
  41                 compatible = "samsung,exynos-bus";
  42                 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
  43                 clock-names = "bus";
  44                 status = "disabled";
  45         };
  46
  47         bus_disp1_fimd: bus-disp1-fimd {
  48                 compatible = "samsung,exynos-bus";
  49                 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
  50                 clock-names = "bus";
  51                 status = "disabled";
  52         };
  53
  54         bus_fsys: bus-fsys {
  55                 compatible = "samsung,exynos-bus";
  56                 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
  57                 clock-names = "bus";
  58                 status = "disabled";
  59         };
  60
  61         bus_fsys2: bus-fsys2 {
  62                 compatible = "samsung,exynos-bus";
  63                 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
  64                 clock-names = "bus";
  65                 status = "disabled";
  66         };
  67
  68         bus_fsys_apb: bus-fsys-apb {
  69                 compatible = "samsung,exynos-bus";
  70                 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
  71                 clock-names = "bus";
  72                 status = "disabled";
  73         };
  74
  75         bus_g2d: bus-g2d {
  76                 compatible = "samsung,exynos-bus";
  77                 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
  78                 clock-names = "bus";
  79                 status = "disabled";
  80         };
  81
  82         bus_g2d_acp: bus-g2d-acp {
  83                 compatible = "samsung,exynos-bus";
  84                 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
  85                 clock-names = "bus";
  86                 status = "disabled";
  87         };
  88         bus_gen: bus-gen {
  89                 compatible = "samsung,exynos-bus";
  90                 clocks = <&clock CLK_DOUT_ACLK266>;
  91                 clock-names = "bus";
  92                 status = "disabled";
  93         };
  94
  95         bus_gscl_scaler: bus-gscl-scaler {
  96                 compatible = "samsung,exynos-bus";
  97                 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
  98                 clock-names = "bus";
  99                 status = "disabled";
 100         };
 101
 102         bus_jpeg: bus-jpeg {
 103                 compatible = "samsung,exynos-bus";
 104                 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
 105                 clock-names = "bus";
 106                 status = "disabled";
 107         };
 108
 109         bus_jpeg_apb: bus-jpeg-apb {
 110                 compatible = "samsung,exynos-bus";
 111                 clocks = <&clock CLK_DOUT_ACLK166>;
 112                 clock-names = "bus";
 113                 status = "disabled";
 114         };
 115
 116         bus_mfc: bus-mfc {
 117                 compatible = "samsung,exynos-bus";
 118                 clocks = <&clock CLK_DOUT_ACLK333>;
 119                 clock-names = "bus";
 120                 status = "disabled";
 121         };
 122
 123         bus_mscl: bus-mscl {
 124                 compatible = "samsung,exynos-bus";
 125                 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
 126                 clock-names = "bus";
 127                 status = "disabled";
 128         };
 129
 130         bus_noc: bus-noc {
 131                 compatible = "samsung,exynos-bus";
 132                 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
 133                 clock-names = "bus";
 134                 status = "disabled";
 135         };
 136
 137         bus_peri: bus-peri {
 138                 compatible = "samsung,exynos-bus";
 139                 clocks = <&clock CLK_DOUT_ACLK66>;
 140                 clock-names = "bus";
 141                 status = "disabled";
 142         };
 143
 144         bus_wcore: bus-wcore {
 145                 compatible = "samsung,exynos-bus";
 146                 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
 147                 clock-names = "bus";
 148                 status = "disabled";
 149         };
 150
 151         /*
 152          * The 'cpus' node is not present here but instead it is provided
 153          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
 154          */
 155
 156         cluster_a15_opp_table: opp-table-0 {
 157                 compatible = "operating-points-v2";
 158                 opp-shared;
 159
 160                 opp-1800000000 {
 161                         opp-hz = /bits/ 64 <1800000000>;
 162                         opp-microvolt = <1250000 1250000 1500000>;
 163                         clock-latency-ns = <140000>;
 164                 };
 165                 opp-1700000000 {
 166                         opp-hz = /bits/ 64 <1700000000>;
 167                         opp-microvolt = <1212500 1212500 1500000>;
 168                         clock-latency-ns = <140000>;
 169                 };
 170                 opp-1600000000 {
 171                         opp-hz = /bits/ 64 <1600000000>;
 172                         opp-microvolt = <1175000 1175000 1500000>;
 173                         clock-latency-ns = <140000>;
 174                 };
 175                 opp-1500000000 {
 176                         opp-hz = /bits/ 64 <1500000000>;
 177                         opp-microvolt = <1137500 1137500 1500000>;
 178                         clock-latency-ns = <140000>;
 179                 };
 180                 opp-1400000000 {
 181                         opp-hz = /bits/ 64 <1400000000>;
 182                         opp-microvolt = <1112500 1112500 1500000>;
 183                         clock-latency-ns = <140000>;
 184                 };
 185                 opp-1300000000 {
 186                         opp-hz = /bits/ 64 <1300000000>;
 187                         opp-microvolt = <1062500 1062500 1500000>;
 188                         clock-latency-ns = <140000>;
 189                 };
 190                 opp-1200000000 {
 191                         opp-hz = /bits/ 64 <1200000000>;
 192                         opp-microvolt = <1037500 1037500 1500000>;
 193                         clock-latency-ns = <140000>;
 194                 };
 195                 opp-1100000000 {
 196                         opp-hz = /bits/ 64 <1100000000>;
 197                         opp-microvolt = <1012500 1012500 1500000>;
 198                         clock-latency-ns = <140000>;
 199                 };
 200                 opp-1000000000 {
 201                         opp-hz = /bits/ 64 <1000000000>;
 202                         opp-microvolt = < 987500 987500 1500000>;
 203                         clock-latency-ns = <140000>;
 204                 };
 205                 opp-900000000 {
 206                         opp-hz = /bits/ 64 <900000000>;
 207                         opp-microvolt = < 962500 962500 1500000>;
 208                         clock-latency-ns = <140000>;
 209                 };
 210                 opp-800000000 {
 211                         opp-hz = /bits/ 64 <800000000>;
 212                         opp-microvolt = < 937500 937500 1500000>;
 213                         clock-latency-ns = <140000>;
 214                 };
 215                 opp-700000000 {
 216                         opp-hz = /bits/ 64 <700000000>;
 217                         opp-microvolt = < 912500 912500 1500000>;
 218                         clock-latency-ns = <140000>;
 219                 };
 220         };
 221
 222         cluster_a7_opp_table: opp-table-1 {
 223                 compatible = "operating-points-v2";
 224                 opp-shared;
 225
 226                 opp-1300000000 {
 227                         opp-hz = /bits/ 64 <1300000000>;
 228                         opp-microvolt = <1275000>;
 229                         clock-latency-ns = <140000>;
 230                 };
 231                 opp-1200000000 {
 232                         opp-hz = /bits/ 64 <1200000000>;
 233                         opp-microvolt = <1212500>;
 234                         clock-latency-ns = <140000>;
 235                 };
 236                 opp-1100000000 {
 237                         opp-hz = /bits/ 64 <1100000000>;
 238                         opp-microvolt = <1162500>;
 239                         clock-latency-ns = <140000>;
 240                 };
 241                 opp-1000000000 {
 242                         opp-hz = /bits/ 64 <1000000000>;
 243                         opp-microvolt = <1112500>;
 244                         clock-latency-ns = <140000>;
 245                 };
 246                 opp-900000000 {
 247                         opp-hz = /bits/ 64 <900000000>;
 248                         opp-microvolt = <1062500>;
 249                         clock-latency-ns = <140000>;
 250                 };
 251                 opp-800000000 {
 252                         opp-hz = /bits/ 64 <800000000>;
 253                         opp-microvolt = <1025000>;
 254                         clock-latency-ns = <140000>;
 255                 };
 256                 opp-700000000 {
 257                         opp-hz = /bits/ 64 <700000000>;
 258                         opp-microvolt = <975000>;
 259                         clock-latency-ns = <140000>;
 260                 };
 261                 opp-600000000 {
 262                         opp-hz = /bits/ 64 <600000000>;
 263                         opp-microvolt = <937500>;
 264                         clock-latency-ns = <140000>;
 265                 };
 266         };
 267
 268         soc: soc {
 269                 cci: cci@10d20000 {
 270                         compatible = "arm,cci-400";
 271                         #address-cells = <1>;
 272                         #size-cells = <1>;
 273                         reg = <0x10d20000 0x1000>;
 274                         ranges = <0x0 0x10d20000 0x6000>;
 275
 276                         cci_control0: slave-if@4000 {
 277                                 compatible = "arm,cci-400-ctrl-if";
 278                                 interface-type = "ace";
 279                                 reg = <0x4000 0x1000>;
 280                         };
 281                         cci_control1: slave-if@5000 {
 282                                 compatible = "arm,cci-400-ctrl-if";
 283                                 interface-type = "ace";
 284                                 reg = <0x5000 0x1000>;
 285                         };
 286                 };
 287
 288                 clock: clock-controller@10010000 {
 289                         compatible = "samsung,exynos5420-clock", "syscon";
 290                         reg = <0x10010000 0x30000>;
 291                         #clock-cells = <1>;
 292                 };
 293
 294                 clock_audss: audss-clock-controller@3810000 {
 295                         compatible = "samsung,exynos5420-audss-clock";
 296                         reg = <0x03810000 0x0c>;
 297                         #clock-cells = <1>;
 298                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 299                                  <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 300                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 301                         power-domains = <&mau_pd>;
 302                 };
 303
 304                 mfc: codec@11000000 {
 305                         compatible = "samsung,mfc-v7";
 306                         reg = <0x11000000 0x10000>;
 307                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 308                         clocks = <&clock CLK_MFC>;
 309                         clock-names = "mfc";
 310                         power-domains = <&mfc_pd>;
 311                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 312                         iommu-names = "left", "right";
 313                 };
 314
 315                 mmc_0: mmc@12200000 {
 316                         compatible = "samsung,exynos5420-dw-mshc-smu";
 317                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                         reg = <0x12200000 0x2000>;
 321                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 322                         clock-names = "biu", "ciu";
 323                         fifo-depth = <0x40>;
 324                         status = "disabled";
 325                 };
 326
 327                 mmc_1: mmc@12210000 {
 328                         compatible = "samsung,exynos5420-dw-mshc-smu";
 329                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         reg = <0x12210000 0x2000>;
 333                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 334                         clock-names = "biu", "ciu";
 335                         fifo-depth = <0x40>;
 336                         status = "disabled";
 337                 };
 338
 339                 mmc_2: mmc@12220000 {
 340                         compatible = "samsung,exynos5420-dw-mshc";
 341                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         reg = <0x12220000 0x1000>;
 345                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 346                         clock-names = "biu", "ciu";
 347                         fifo-depth = <0x40>;
 348                         status = "disabled";
 349                 };
 350
 351                 dmc: memory-controller@10c20000 {
 352                         compatible = "samsung,exynos5422-dmc";
 353                         reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
 354                         clocks = <&clock CLK_FOUT_SPLL>,
 355                                  <&clock CLK_MOUT_SCLK_SPLL>,
 356                                  <&clock CLK_FF_DOUT_SPLL2>,
 357                                  <&clock CLK_FOUT_BPLL>,
 358                                  <&clock CLK_MOUT_BPLL>,
 359                                  <&clock CLK_SCLK_BPLL>,
 360                                  <&clock CLK_MOUT_MX_MSPLL_CCORE>,
 361                                  <&clock CLK_MOUT_MCLK_CDREX>;
 362                         clock-names = "fout_spll",
 363                                       "mout_sclk_spll",
 364                                       "ff_dout_spll2",
 365                                       "fout_bpll",
 366                                       "mout_bpll",
 367                                       "sclk_bpll",
 368                                       "mout_mx_mspll_ccore",
 369                                       "mout_mclk_cdrex";
 370                         samsung,syscon-clk = <&clock>;
 371                         status = "disabled";
 372                 };
 373
 374                 nocp_mem0_0: nocp@10ca1000 {
 375                         compatible = "samsung,exynos5420-nocp";
 376                         reg = <0x10ca1000 0x200>;
 377                         status = "disabled";
 378                 };
 379
 380                 nocp_mem0_1: nocp@10ca1400 {
 381                         compatible = "samsung,exynos5420-nocp";
 382                         reg = <0x10ca1400 0x200>;
 383                         status = "disabled";
 384                 };
 385
 386                 nocp_mem1_0: nocp@10ca1800 {
 387                         compatible = "samsung,exynos5420-nocp";
 388                         reg = <0x10ca1800 0x200>;
 389                         status = "disabled";
 390                 };
 391
 392                 nocp_mem1_1: nocp@10ca1c00 {
 393                         compatible = "samsung,exynos5420-nocp";
 394                         reg = <0x10ca1c00 0x200>;
 395                         status = "disabled";
 396                 };
 397
 398                 nocp_g3d_0: nocp@11a51000 {
 399                         compatible = "samsung,exynos5420-nocp";
 400                         reg = <0x11a51000 0x200>;
 401                         status = "disabled";
 402                 };
 403
 404                 nocp_g3d_1: nocp@11a51400 {
 405                         compatible = "samsung,exynos5420-nocp";
 406                         reg = <0x11a51400 0x200>;
 407                         status = "disabled";
 408                 };
 409
 410                 ppmu_dmc0_0: ppmu@10d00000 {
 411                         compatible = "samsung,exynos-ppmu";
 412                         reg = <0x10d00000 0x2000>;
 413                         clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
 414                         clock-names = "ppmu";
 415                         events {
 416                                 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
 417                                         event-name = "ppmu-event3-dmc0-0";
 418                                 };
 419                         };
 420                 };
 421
 422                 ppmu_dmc0_1: ppmu@10d10000 {
 423                         compatible = "samsung,exynos-ppmu";
 424                         reg = <0x10d10000 0x2000>;
 425                         clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
 426                         clock-names = "ppmu";
 427                         events {
 428                                 ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
 429                                         event-name = "ppmu-event3-dmc0-1";
 430                                 };
 431                         };
 432                 };
 433
 434                 ppmu_dmc1_0: ppmu@10d60000 {
 435                         compatible = "samsung,exynos-ppmu";
 436                         reg = <0x10d60000 0x2000>;
 437                         clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
 438                         clock-names = "ppmu";
 439                         events {
 440                                 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
 441                                         event-name = "ppmu-event3-dmc1-0";
 442                                 };
 443                         };
 444                 };
 445
 446                 ppmu_dmc1_1: ppmu@10d70000 {
 447                         compatible = "samsung,exynos-ppmu";
 448                         reg = <0x10d70000 0x2000>;
 449                         clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
 450                         clock-names = "ppmu";
 451                         events {
 452                                 ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
 453                                         event-name = "ppmu-event3-dmc1-1";
 454                                 };
 455                         };
 456                 };
 457
 458                 gsc_pd: power-domain@10044000 {
 459                         compatible = "samsung,exynos4210-pd";
 460                         reg = <0x10044000 0x20>;
 461                         #power-domain-cells = <0>;
 462                         label = "GSC";
 463                 };
 464
 465                 isp_pd: power-domain@10044020 {
 466                         compatible = "samsung,exynos4210-pd";
 467                         reg = <0x10044020 0x20>;
 468                         #power-domain-cells = <0>;
 469                         label = "ISP";
 470                 };
 471
 472                 mfc_pd: power-domain@10044060 {
 473                         compatible = "samsung,exynos4210-pd";
 474                         reg = <0x10044060 0x20>;
 475                         #power-domain-cells = <0>;
 476                         label = "MFC";
 477                 };
 478
 479                 g3d_pd: power-domain@10044080 {
 480                         compatible = "samsung,exynos4210-pd";
 481                         reg = <0x10044080 0x20>;
 482                         #power-domain-cells = <0>;
 483                         label = "G3D";
 484                 };
 485
 486                 disp_pd: power-domain@100440c0 {
 487                         compatible = "samsung,exynos4210-pd";
 488                         reg = <0x100440c0 0x20>;
 489                         #power-domain-cells = <0>;
 490                         label = "DISP";
 491                 };
 492
 493                 mau_pd: power-domain@100440e0 {
 494                         compatible = "samsung,exynos4210-pd";
 495                         reg = <0x100440e0 0x20>;
 496                         #power-domain-cells = <0>;
 497                         label = "MAU";
 498                 };
 499
 500                 msc_pd: power-domain@10044120 {
 501                         compatible = "samsung,exynos4210-pd";
 502                         reg = <0x10044120 0x20>;
 503                         #power-domain-cells = <0>;
 504                         label = "MSC";
 505                 };
 506
 507                 pinctrl_0: pinctrl@13400000 {
 508                         compatible = "samsung,exynos5420-pinctrl";
 509                         reg = <0x13400000 0x1000>;
 510                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 511
 512                         wakeup-interrupt-controller {
 513                                 compatible = "samsung,exynos4210-wakeup-eint";
 514                                 interrupt-parent = <&gic>;
 515                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 516                         };
 517                 };
 518
 519                 pinctrl_1: pinctrl@13410000 {
 520                         compatible = "samsung,exynos5420-pinctrl";
 521                         reg = <0x13410000 0x1000>;
 522                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 523                 };
 524
 525                 pinctrl_2: pinctrl@14000000 {
 526                         compatible = "samsung,exynos5420-pinctrl";
 527                         reg = <0x14000000 0x1000>;
 528                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 529                 };
 530
 531                 pinctrl_3: pinctrl@14010000 {
 532                         compatible = "samsung,exynos5420-pinctrl";
 533                         reg = <0x14010000 0x1000>;
 534                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 535                 };
 536
 537                 pinctrl_4: pinctrl@3860000 {
 538                         compatible = "samsung,exynos5420-pinctrl";
 539                         reg = <0x03860000 0x1000>;
 540                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 541                         power-domains = <&mau_pd>;
 542                 };
 543
 544                 adma: dma-controller@3880000 {
 545                         compatible = "arm,pl330", "arm,primecell";
 546                         reg = <0x03880000 0x1000>;
 547                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&clock_audss EXYNOS_ADMA>;
 549                         clock-names = "apb_pclk";
 550                         #dma-cells = <1>;
 551                         power-domains = <&mau_pd>;
 552                 };
 553
 554                 pdma0: dma-controller@121a0000 {
 555                         compatible = "arm,pl330", "arm,primecell";
 556                         reg = <0x121a0000 0x1000>;
 557                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 558                         clocks = <&clock CLK_PDMA0>;
 559                         clock-names = "apb_pclk";
 560                         #dma-cells = <1>;
 561                 };
 562
 563                 pdma1: dma-controller@121b0000 {
 564                         compatible = "arm,pl330", "arm,primecell";
 565                         reg = <0x121b0000 0x1000>;
 566                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&clock CLK_PDMA1>;
 568                         clock-names = "apb_pclk";
 569                         #dma-cells = <1>;
 570                 };
 571
 572                 mdma0: dma-controller@10800000 {
 573                         compatible = "arm,pl330", "arm,primecell";
 574                         reg = <0x10800000 0x1000>;
 575                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&clock CLK_MDMA0>;
 577                         clock-names = "apb_pclk";
 578                         #dma-cells = <1>;
 579                 };
 580
 581                 mdma1: dma-controller@11c10000 {
 582                         compatible = "arm,pl330", "arm,primecell";
 583                         reg = <0x11c10000 0x1000>;
 584                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 585                         clocks = <&clock CLK_MDMA1>;
 586                         clock-names = "apb_pclk";
 587                         #dma-cells = <1>;
 588                         /*
 589                          * MDMA1 can support both secure and non-secure
 590                          * AXI transactions. When this is enabled in
 591                          * the kernel for boards that run in secure
 592                          * mode, we are getting imprecise external
 593                          * aborts causing the kernel to oops.
 594                          */
 595                         status = "disabled";
 596                 };
 597
 598                 i2s0: i2s@3830000 {
 599                         compatible = "samsung,exynos5420-i2s";
 600                         reg = <0x03830000 0x100>;
 601                         dmas = <&adma 0>,
 602                                 <&adma 2>,
 603                                 <&adma 1>;
 604                         dma-names = "tx", "rx", "tx-sec";
 605                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 606                                 <&clock_audss EXYNOS_I2S_BUS>,
 607                                 <&clock_audss EXYNOS_SCLK_I2S>;
 608                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 609                         #clock-cells = <1>;
 610                         clock-output-names = "i2s_cdclk0";
 611                         #sound-dai-cells = <1>;
 612                         samsung,idma-addr = <0x03000000>;
 613                         pinctrl-names = "default";
 614                         pinctrl-0 = <&i2s0_bus>;
 615                         power-domains = <&mau_pd>;
 616                         status = "disabled";
 617                 };
 618
 619                 i2s1: i2s@12d60000 {
 620                         compatible = "samsung,exynos5420-i2s";
 621                         reg = <0x12d60000 0x100>;
 622                         dmas = <&pdma1 12>,
 623                                 <&pdma1 11>;
 624                         dma-names = "tx", "rx";
 625                         clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 626                         clock-names = "iis", "i2s_opclk0";
 627                         #clock-cells = <1>;
 628                         clock-output-names = "i2s_cdclk1";
 629                         #sound-dai-cells = <1>;
 630                         pinctrl-names = "default";
 631                         pinctrl-0 = <&i2s1_bus>;
 632                         status = "disabled";
 633                 };
 634
 635                 i2s2: i2s@12d70000 {
 636                         compatible = "samsung,exynos5420-i2s";
 637                         reg = <0x12d70000 0x100>;
 638                         dmas = <&pdma0 12>,
 639                                 <&pdma0 11>;
 640                         dma-names = "tx", "rx";
 641                         clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 642                         clock-names = "iis", "i2s_opclk0";
 643                         #clock-cells = <1>;
 644                         clock-output-names = "i2s_cdclk2";
 645                         #sound-dai-cells = <1>;
 646                         pinctrl-names = "default";
 647                         pinctrl-0 = <&i2s2_bus>;
 648                         status = "disabled";
 649                 };
 650
 651                 spi_0: spi@12d20000 {
 652                         compatible = "samsung,exynos4210-spi";
 653                         reg = <0x12d20000 0x100>;
 654                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 655                         dmas = <&pdma0 5
 656                                 &pdma0 4>;
 657                         dma-names = "tx", "rx";
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                         pinctrl-names = "default";
 661                         pinctrl-0 = <&spi0_bus>;
 662                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 663                         clock-names = "spi", "spi_busclk0";
 664                         status = "disabled";
 665                 };
 666
 667                 spi_1: spi@12d30000 {
 668                         compatible = "samsung,exynos4210-spi";
 669                         reg = <0x12d30000 0x100>;
 670                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 671                         dmas = <&pdma1 5
 672                                 &pdma1 4>;
 673                         dma-names = "tx", "rx";
 674                         #address-cells = <1>;
 675                         #size-cells = <0>;
 676                         pinctrl-names = "default";
 677                         pinctrl-0 = <&spi1_bus>;
 678                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 679                         clock-names = "spi", "spi_busclk0";
 680                         status = "disabled";
 681                 };
 682
 683                 spi_2: spi@12d40000 {
 684                         compatible = "samsung,exynos4210-spi";
 685                         reg = <0x12d40000 0x100>;
 686                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 687                         dmas = <&pdma0 7
 688                                 &pdma0 6>;
 689                         dma-names = "tx", "rx";
 690                         #address-cells = <1>;
 691                         #size-cells = <0>;
 692                         pinctrl-names = "default";
 693                         pinctrl-0 = <&spi2_bus>;
 694                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 695                         clock-names = "spi", "spi_busclk0";
 696                         status = "disabled";
 697                 };
 698
 699                 dp_phy: dp-video-phy {
 700                         compatible = "samsung,exynos5420-dp-video-phy";
 701                         samsung,pmu-syscon = <&pmu_system_controller>;
 702                         #phy-cells = <0>;
 703                 };
 704
 705                 mipi_phy: mipi-video-phy {
 706                         compatible = "samsung,exynos5420-mipi-video-phy";
 707                         syscon = <&pmu_system_controller>;
 708                         #phy-cells = <1>;
 709                 };
 710
 711                 dsi: dsi@14500000 {
 712                         compatible = "samsung,exynos5410-mipi-dsi";
 713                         reg = <0x14500000 0x10000>;
 714                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 715                         phys = <&mipi_phy 1>;
 716                         phy-names = "dsim";
 717                         clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 718                         clock-names = "bus_clk", "pll_clk";
 719                         #address-cells = <1>;
 720                         #size-cells = <0>;
 721                         status = "disabled";
 722                 };
 723
 724                 hsi2c_8: i2c@12e00000 {
 725                         compatible = "samsung,exynos5250-hsi2c";
 726                         reg = <0x12e00000 0x1000>;
 727                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 728                         #address-cells = <1>;
 729                         #size-cells = <0>;
 730                         pinctrl-names = "default";
 731                         pinctrl-0 = <&i2c8_hs_bus>;
 732                         clocks = <&clock CLK_USI4>;
 733                         clock-names = "hsi2c";
 734                         status = "disabled";
 735                 };
 736
 737                 hsi2c_9: i2c@12e10000 {
 738                         compatible = "samsung,exynos5250-hsi2c";
 739                         reg = <0x12e10000 0x1000>;
 740                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 741                         #address-cells = <1>;
 742                         #size-cells = <0>;
 743                         pinctrl-names = "default";
 744                         pinctrl-0 = <&i2c9_hs_bus>;
 745                         clocks = <&clock CLK_USI5>;
 746                         clock-names = "hsi2c";
 747                         status = "disabled";
 748                 };
 749
 750                 hsi2c_10: i2c@12e20000 {
 751                         compatible = "samsung,exynos5250-hsi2c";
 752                         reg = <0x12e20000 0x1000>;
 753                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         pinctrl-names = "default";
 757                         pinctrl-0 = <&i2c10_hs_bus>;
 758                         clocks = <&clock CLK_USI6>;
 759                         clock-names = "hsi2c";
 760                         status = "disabled";
 761                 };
 762
 763                 hdmi: hdmi@14530000 {
 764                         compatible = "samsung,exynos5420-hdmi";
 765                         reg = <0x14530000 0x70000>;
 766                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 767                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 768                                  <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 769                                  <&clock CLK_MOUT_HDMI>;
 770                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 771                                 "sclk_hdmiphy", "mout_hdmi";
 772                         phy = <&hdmiphy>;
 773                         samsung,syscon-phandle = <&pmu_system_controller>;
 774                         status = "disabled";
 775                         power-domains = <&disp_pd>;
 776                         #sound-dai-cells = <0>;
 777                 };
 778
 779                 hdmiphy: hdmi-phy@145d0000 {
 780                         reg = <0x145d0000 0x20>;
 781                 };
 782
 783                 hdmicec: cec@101b0000 {
 784                         compatible = "samsung,s5p-cec";
 785                         reg = <0x101b0000 0x200>;
 786                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 787                         clocks = <&clock CLK_HDMI_CEC>;
 788                         clock-names = "hdmicec";
 789                         samsung,syscon-phandle = <&pmu_system_controller>;
 790                         hdmi-phandle = <&hdmi>;
 791                         pinctrl-names = "default";
 792                         pinctrl-0 = <&hdmi_cec>;
 793                         status = "disabled";
 794                 };
 795
 796                 mixer: mixer@14450000 {
 797                         compatible = "samsung,exynos5420-mixer";
 798                         reg = <0x14450000 0x10000>;
 799                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 800                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 801                                  <&clock CLK_SCLK_HDMI>;
 802                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 803                         power-domains = <&disp_pd>;
 804                         iommus = <&sysmmu_tv>;
 805                         status = "disabled";
 806                 };
 807
 808                 rotator: rotator@11c00000 {
 809                         compatible = "samsung,exynos5250-rotator";
 810                         reg = <0x11c00000 0x64>;
 811                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&clock CLK_ROTATOR>;
 813                         clock-names = "rotator";
 814                         iommus = <&sysmmu_rotator>;
 815                 };
 816
 817                 gsc_0: video-scaler@13e00000 {
 818                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 819                         reg = <0x13e00000 0x1000>;
 820                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 821                         clocks = <&clock CLK_GSCL0>;
 822                         clock-names = "gscl";
 823                         power-domains = <&gsc_pd>;
 824                         iommus = <&sysmmu_gscl0>;
 825                 };
 826
 827                 gsc_1: video-scaler@13e10000 {
 828                         compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
 829                         reg = <0x13e10000 0x1000>;
 830                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 831                         clocks = <&clock CLK_GSCL1>;
 832                         clock-names = "gscl";
 833                         power-domains = <&gsc_pd>;
 834                         iommus = <&sysmmu_gscl1>;
 835                 };
 836
 837                 gpu: gpu@11800000 {
 838                         compatible = "samsung,exynos5420-mali", "arm,mali-t628";
 839                         reg = <0x11800000 0x5000>;
 840                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 841                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 842                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 843                         interrupt-names = "job", "mmu", "gpu";
 844
 845                         clocks = <&clock CLK_G3D>;
 846                         clock-names = "core";
 847                         power-domains = <&g3d_pd>;
 848                         operating-points-v2 = <&gpu_opp_table>;
 849
 850                         status = "disabled";
 851                         #cooling-cells = <2>;
 852
 853                         gpu_opp_table: opp-table {
 854                                 compatible = "operating-points-v2";
 855
 856                                 opp-177000000 {
 857                                         opp-hz = /bits/ 64 <177000000>;
 858                                         opp-microvolt = <812500>;
 859                                 };
 860                                 opp-266000000 {
 861                                         opp-hz = /bits/ 64 <266000000>;
 862                                         opp-microvolt = <862500>;
 863                                 };
 864                                 opp-350000000 {
 865                                         opp-hz = /bits/ 64 <350000000>;
 866                                         opp-microvolt = <912500>;
 867                                 };
 868                                 opp-420000000 {
 869                                         opp-hz = /bits/ 64 <420000000>;
 870                                         opp-microvolt = <962500>;
 871                                 };
 872                                 opp-480000000 {
 873                                         opp-hz = /bits/ 64 <480000000>;
 874                                         opp-microvolt = <1000000>;
 875                                 };
 876                                 opp-543000000 {
 877                                         opp-hz = /bits/ 64 <543000000>;
 878                                         opp-microvolt = <1037500>;
 879                                 };
 880                                 opp-600000000 {
 881                                         opp-hz = /bits/ 64 <600000000>;
 882                                         opp-microvolt = <1150000>;
 883                                 };
 884                         };
 885                 };
 886
 887                 scaler_0: scaler@12800000 {
 888                         compatible = "samsung,exynos5420-scaler";
 889                         reg = <0x12800000 0x1294>;
 890                         interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
 891                         clocks = <&clock CLK_MSCL0>;
 892                         clock-names = "mscl";
 893                         power-domains = <&msc_pd>;
 894                         iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
 895                 };
 896
 897                 scaler_1: scaler@12810000 {
 898                         compatible = "samsung,exynos5420-scaler";
 899                         reg = <0x12810000 0x1294>;
 900                         interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
 901                         clocks = <&clock CLK_MSCL1>;
 902                         clock-names = "mscl";
 903                         power-domains = <&msc_pd>;
 904                         iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
 905                 };
 906
 907                 scaler_2: scaler@12820000 {
 908                         compatible = "samsung,exynos5420-scaler";
 909                         reg = <0x12820000 0x1294>;
 910                         interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&clock CLK_MSCL2>;
 912                         clock-names = "mscl";
 913                         power-domains = <&msc_pd>;
 914                         iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
 915                 };
 916
 917                 jpeg_0: jpeg@11f50000 {
 918                         compatible = "samsung,exynos5420-jpeg";
 919                         reg = <0x11f50000 0x1000>;
 920                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 921                         clock-names = "jpeg";
 922                         clocks = <&clock CLK_JPEG>;
 923                         iommus = <&sysmmu_jpeg0>;
 924                 };
 925
 926                 jpeg_1: jpeg@11f60000 {
 927                         compatible = "samsung,exynos5420-jpeg";
 928                         reg = <0x11f60000 0x1000>;
 929                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 930                         clock-names = "jpeg";
 931                         clocks = <&clock CLK_JPEG2>;
 932                         iommus = <&sysmmu_jpeg1>;
 933                 };
 934
 935                 pmu_system_controller: system-controller@10040000 {
 936                         compatible = "samsung,exynos5420-pmu", "syscon";
 937                         reg = <0x10040000 0x5000>;
 938                         clock-names = "clkout16";
 939                         clocks = <&clock CLK_FIN_PLL>;
 940                         #clock-cells = <1>;
 941                         interrupt-controller;
 942                         #interrupt-cells = <3>;
 943                         interrupt-parent = <&gic>;
 944                 };
 945
 946                 tmu_cpu0: tmu@10060000 {
 947                         compatible = "samsung,exynos5420-tmu";
 948                         reg = <0x10060000 0x100>;
 949                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 950                         clocks = <&clock CLK_TMU>;
 951                         clock-names = "tmu_apbif";
 952                         #thermal-sensor-cells = <0>;
 953                 };
 954
 955                 tmu_cpu1: tmu@10064000 {
 956                         compatible = "samsung,exynos5420-tmu";
 957                         reg = <0x10064000 0x100>;
 958                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 959                         clocks = <&clock CLK_TMU>;
 960                         clock-names = "tmu_apbif";
 961                         #thermal-sensor-cells = <0>;
 962                 };
 963
 964                 tmu_cpu2: tmu@10068000 {
 965                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 966                         reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 967                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 968                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 969                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 970                         #thermal-sensor-cells = <0>;
 971                 };
 972
 973                 tmu_cpu3: tmu@1006c000 {
 974                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 975                         reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 976                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 977                         clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 978                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 979                         #thermal-sensor-cells = <0>;
 980                 };
 981
 982                 tmu_gpu: tmu@100a0000 {
 983                         compatible = "samsung,exynos5420-tmu-ext-triminfo";
 984                         reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 985                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 986                         clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 987                         clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 988                         #thermal-sensor-cells = <0>;
 989                 };
 990
 991                 sysmmu_g2dr: sysmmu@10a60000 {
 992                         compatible = "samsung,exynos-sysmmu";
 993                         reg = <0x10a60000 0x1000>;
 994                         interrupt-parent = <&combiner>;
 995                         interrupts = <24 5>;
 996                         clock-names = "sysmmu", "master";
 997                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 998                         #iommu-cells = <0>;
 999                 };
1000
1001                 sysmmu_g2dw: sysmmu@10a70000 {
1002                         compatible = "samsung,exynos-sysmmu";
1003                         reg = <0x10a70000 0x1000>;
1004                         interrupt-parent = <&combiner>;
1005                         interrupts = <22 2>;
1006                         clock-names = "sysmmu", "master";
1007                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1008                         #iommu-cells = <0>;
1009                 };
1010
1011                 sysmmu_tv: sysmmu@14650000 {
1012                         compatible = "samsung,exynos-sysmmu";
1013                         reg = <0x14650000 0x1000>;
1014                         interrupt-parent = <&combiner>;
1015                         interrupts = <7 4>;
1016                         clock-names = "sysmmu", "master";
1017                         clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1018                         power-domains = <&disp_pd>;
1019                         #iommu-cells = <0>;
1020                 };
1021
1022                 sysmmu_gscl0: sysmmu@13e80000 {
1023                         compatible = "samsung,exynos-sysmmu";
1024                         reg = <0x13e80000 0x1000>;
1025                         interrupt-parent = <&combiner>;
1026                         interrupts = <2 0>;
1027                         clock-names = "sysmmu", "master";
1028                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1029                         power-domains = <&gsc_pd>;
1030                         #iommu-cells = <0>;
1031                 };
1032
1033                 sysmmu_gscl1: sysmmu@13e90000 {
1034                         compatible = "samsung,exynos-sysmmu";
1035                         reg = <0x13e90000 0x1000>;
1036                         interrupt-parent = <&combiner>;
1037                         interrupts = <2 2>;
1038                         clock-names = "sysmmu", "master";
1039                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1040                         power-domains = <&gsc_pd>;
1041                         #iommu-cells = <0>;
1042                 };
1043
1044                 sysmmu_scaler0r: sysmmu@12880000 {
1045                         compatible = "samsung,exynos-sysmmu";
1046                         reg = <0x12880000 0x1000>;
1047                         interrupt-parent = <&combiner>;
1048                         interrupts = <22 4>;
1049                         clock-names = "sysmmu", "master";
1050                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1051                         power-domains = <&msc_pd>;
1052                         #iommu-cells = <0>;
1053                 };
1054
1055                 sysmmu_scaler1r: sysmmu@12890000 {
1056                         compatible = "samsung,exynos-sysmmu";
1057                         reg = <0x12890000 0x1000>;
1058                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1059                         clock-names = "sysmmu", "master";
1060                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1061                         power-domains = <&msc_pd>;
1062                         #iommu-cells = <0>;
1063                 };
1064
1065                 sysmmu_scaler2r: sysmmu@128a0000 {
1066                         compatible = "samsung,exynos-sysmmu";
1067                         reg = <0x128a0000 0x1000>;
1068                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1069                         clock-names = "sysmmu", "master";
1070                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1071                         power-domains = <&msc_pd>;
1072                         #iommu-cells = <0>;
1073                 };
1074
1075                 sysmmu_scaler0w: sysmmu@128c0000 {
1076                         compatible = "samsung,exynos-sysmmu";
1077                         reg = <0x128c0000 0x1000>;
1078                         interrupt-parent = <&combiner>;
1079                         interrupts = <27 2>;
1080                         clock-names = "sysmmu", "master";
1081                         clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1082                         power-domains = <&msc_pd>;
1083                         #iommu-cells = <0>;
1084                 };
1085
1086                 sysmmu_scaler1w: sysmmu@128d0000 {
1087                         compatible = "samsung,exynos-sysmmu";
1088                         reg = <0x128d0000 0x1000>;
1089                         interrupt-parent = <&combiner>;
1090                         interrupts = <22 6>;
1091                         clock-names = "sysmmu", "master";
1092                         clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1093                         power-domains = <&msc_pd>;
1094                         #iommu-cells = <0>;
1095                 };
1096
1097                 sysmmu_scaler2w: sysmmu@128e0000 {
1098                         compatible = "samsung,exynos-sysmmu";
1099                         reg = <0x128e0000 0x1000>;
1100                         interrupt-parent = <&combiner>;
1101                         interrupts = <19 6>;
1102                         clock-names = "sysmmu", "master";
1103                         clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1104                         power-domains = <&msc_pd>;
1105                         #iommu-cells = <0>;
1106                 };
1107
1108                 sysmmu_rotator: sysmmu@11d40000 {
1109                         compatible = "samsung,exynos-sysmmu";
1110                         reg = <0x11d40000 0x1000>;
1111                         interrupt-parent = <&combiner>;
1112                         interrupts = <4 0>;
1113                         clock-names = "sysmmu", "master";
1114                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1115                         #iommu-cells = <0>;
1116                 };
1117
1118                 sysmmu_jpeg0: sysmmu@11f10000 {
1119                         compatible = "samsung,exynos-sysmmu";
1120                         reg = <0x11f10000 0x1000>;
1121                         interrupt-parent = <&combiner>;
1122                         interrupts = <4 2>;
1123                         clock-names = "sysmmu", "master";
1124                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1125                         #iommu-cells = <0>;
1126                 };
1127
1128                 sysmmu_jpeg1: sysmmu@11f20000 {
1129                         compatible = "samsung,exynos-sysmmu";
1130                         reg = <0x11f20000 0x1000>;
1131                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1132                         clock-names = "sysmmu", "master";
1133                         clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1134                         #iommu-cells = <0>;
1135                 };
1136
1137                 sysmmu_mfc_l: sysmmu@11200000 {
1138                         compatible = "samsung,exynos-sysmmu";
1139                         reg = <0x11200000 0x1000>;
1140                         interrupt-parent = <&combiner>;
1141                         interrupts = <6 2>;
1142                         clock-names = "sysmmu", "master";
1143                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1144                         power-domains = <&mfc_pd>;
1145                         #iommu-cells = <0>;
1146                 };
1147
1148                 sysmmu_mfc_r: sysmmu@11210000 {
1149                         compatible = "samsung,exynos-sysmmu";
1150                         reg = <0x11210000 0x1000>;
1151                         interrupt-parent = <&combiner>;
1152                         interrupts = <8 5>;
1153                         clock-names = "sysmmu", "master";
1154                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1155                         power-domains = <&mfc_pd>;
1156                         #iommu-cells = <0>;
1157                 };
1158
1159                 sysmmu_fimd1_0: sysmmu@14640000 {
1160                         compatible = "samsung,exynos-sysmmu";
1161                         reg = <0x14640000 0x1000>;
1162                         interrupt-parent = <&combiner>;
1163                         interrupts = <3 2>;
1164                         clock-names = "sysmmu", "master";
1165                         clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1166                         power-domains = <&disp_pd>;
1167                         #iommu-cells = <0>;
1168                 };
1169
1170                 sysmmu_fimd1_1: sysmmu@14680000 {
1171                         compatible = "samsung,exynos-sysmmu";
1172                         reg = <0x14680000 0x1000>;
1173                         interrupt-parent = <&combiner>;
1174                         interrupts = <3 0>;
1175                         clock-names = "sysmmu", "master";
1176                         clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1177                         power-domains = <&disp_pd>;
1178                         #iommu-cells = <0>;
1179                 };
1180         };
1181
1182         thermal-zones {
1183                 cpu0_thermal: cpu0-thermal {
1184                         thermal-sensors = <&tmu_cpu0>;
1185                         #include "exynos5420-trip-points.dtsi"
1186                 };
1187                 cpu1_thermal: cpu1-thermal {
1188                         thermal-sensors = <&tmu_cpu1>;
1189                         #include "exynos5420-trip-points.dtsi"
1190                 };
1191                 cpu2_thermal: cpu2-thermal {
1192                         thermal-sensors = <&tmu_cpu2>;
1193                         #include "exynos5420-trip-points.dtsi"
1194                 };
1195                 cpu3_thermal: cpu3-thermal {
1196                         thermal-sensors = <&tmu_cpu3>;
1197                         #include "exynos5420-trip-points.dtsi"
1198                 };
1199                 gpu_thermal: gpu-thermal {
1200                         thermal-sensors = <&tmu_gpu>;
1201                         #include "exynos5420-trip-points.dtsi"
1202                 };
1203         };
1204 };
1205
1206 &adc {
1207         clocks = <&clock CLK_TSADC>;
1208         clock-names = "adc";
1209         samsung,syscon-phandle = <&pmu_system_controller>;
1210 };
1211
1212 &dp {
1213         clocks = <&clock CLK_DP1>;
1214         clock-names = "dp";
1215         phys = <&dp_phy>;
1216         phy-names = "dp";
1217         power-domains = <&disp_pd>;
1218 };
1219
1220 &fimd {
1221         compatible = "samsung,exynos5420-fimd";
1222         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1223         clock-names = "sclk_fimd", "fimd";
1224         power-domains = <&disp_pd>;
1225         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1226         iommu-names = "m0", "m1";
1227 };
1228
1229 &g2d {
1230         iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1231         clocks = <&clock CLK_G2D>;
1232         clock-names = "fimg2d";
1233         status = "okay";
1234 };
1235
1236 &i2c_0 {
1237         clocks = <&clock CLK_I2C0>;
1238         clock-names = "i2c";
1239         pinctrl-names = "default";
1240         pinctrl-0 = <&i2c0_bus>;
1241 };
1242
1243 &i2c_1 {
1244         clocks = <&clock CLK_I2C1>;
1245         clock-names = "i2c";
1246         pinctrl-names = "default";
1247         pinctrl-0 = <&i2c1_bus>;
1248 };
1249
1250 &i2c_2 {
1251         clocks = <&clock CLK_I2C2>;
1252         clock-names = "i2c";
1253         pinctrl-names = "default";
1254         pinctrl-0 = <&i2c2_bus>;
1255 };
1256
1257 &i2c_3 {
1258         clocks = <&clock CLK_I2C3>;
1259         clock-names = "i2c";
1260         pinctrl-names = "default";
1261         pinctrl-0 = <&i2c3_bus>;
1262 };
1263
1264 &hsi2c_4 {
1265         clocks = <&clock CLK_USI0>;
1266         clock-names = "hsi2c";
1267         pinctrl-names = "default";
1268         pinctrl-0 = <&i2c4_hs_bus>;
1269 };
1270
1271 &hsi2c_5 {
1272         clocks = <&clock CLK_USI1>;
1273         clock-names = "hsi2c";
1274         pinctrl-names = "default";
1275         pinctrl-0 = <&i2c5_hs_bus>;
1276 };
1277
1278 &hsi2c_6 {
1279         clocks = <&clock CLK_USI2>;
1280         clock-names = "hsi2c";
1281         pinctrl-names = "default";
1282         pinctrl-0 = <&i2c6_hs_bus>;
1283 };
1284
1285 &hsi2c_7 {
1286         clocks = <&clock CLK_USI3>;
1287         clock-names = "hsi2c";
1288         pinctrl-names = "default";
1289         pinctrl-0 = <&i2c7_hs_bus>;
1290 };
1291
1292 &mct {
1293         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1294         clock-names = "fin_pll", "mct";
1295 };
1296
1297 &prng {
1298         clocks = <&clock CLK_SSS>;
1299         clock-names = "secss";
1300 };
1301
1302 &pwm {
1303         clocks = <&clock CLK_PWM>;
1304         clock-names = "timers";
1305 };
1306
1307 &rtc {
1308         clocks = <&clock CLK_RTC>;
1309         clock-names = "rtc";
1310         interrupt-parent = <&pmu_system_controller>;
1311         status = "disabled";
1312 };
1313
1314 &serial_0 {
1315         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1316         clock-names = "uart", "clk_uart_baud0";
1317         dmas = <&pdma0 13>, <&pdma0 14>;
1318         dma-names = "rx", "tx";
1319 };
1320
1321 &serial_1 {
1322         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1323         clock-names = "uart", "clk_uart_baud0";
1324         dmas = <&pdma1 15>, <&pdma1 16>;
1325         dma-names = "rx", "tx";
1326 };
1327
1328 &serial_2 {
1329         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1330         clock-names = "uart", "clk_uart_baud0";
1331         dmas = <&pdma0 15>, <&pdma0 16>;
1332         dma-names = "rx", "tx";
1333 };
1334
1335 &serial_3 {
1336         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1337         clock-names = "uart", "clk_uart_baud0";
1338         dmas = <&pdma1 17>, <&pdma1 18>;
1339         dma-names = "rx", "tx";
1340 };
1341
1342 &sss {
1343         clocks = <&clock CLK_SSS>;
1344         clock-names = "secss";
1345 };
1346
1347 &trng {
1348         clocks = <&clock CLK_SSS>;
1349         clock-names = "secss";
1350 };
1351
1352 &usbdrd3_0 {
1353         clocks = <&clock CLK_USBD300>;
1354         clock-names = "usbdrd30";
1355 };
1356
1357 &usbdrd_phy0 {
1358         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1359         clock-names = "phy", "ref";
1360         samsung,pmu-syscon = <&pmu_system_controller>;
1361 };
1362
1363 &usbdrd3_1 {
1364         clocks = <&clock CLK_USBD301>;
1365         clock-names = "usbdrd30";
1366 };
1367
1368 &usbdrd_dwc3_1 {
1369         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1370 };
1371
1372 &usbdrd_phy1 {
1373         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1374         clock-names = "phy", "ref";
1375         samsung,pmu-syscon = <&pmu_system_controller>;
1376 };
1377
1378 &usbhost1 {
1379         clocks = <&clock CLK_USBH20>;
1380         clock-names = "usbhost";
1381 };
1382
1383 &usbhost2 {
1384         clocks = <&clock CLK_USBH20>;
1385         clock-names = "usbhost";
1386 };
1387
1388 &usb2_phy {
1389         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1390         clock-names = "phy", "ref";
1391         samsung,sysreg-phandle = <&sysreg_system_controller>;
1392         samsung,pmureg-phandle = <&pmu_system_controller>;
1393 };
1394
1395 &watchdog {
1396         clocks = <&clock CLK_WDT>;
1397         clock-names = "watchdog";
1398         samsung,syscon-phandle = <&pmu_system_controller>;
1399 };
1400
1401 #include "exynos5420-pinctrl.dtsi"
1402 #include "exynos-syscon-restart.dtsi"