1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5420 SoC device tree source
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung Exynos5420 SoC device nodes are listed in this file.
9 * Exynos5420 based board files can include this file and provide
10 * values for board specfic bindings.
13 #include "exynos54xx.dtsi"
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "samsung,exynos5420", "samsung,exynos5";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
41 * The 'cpus' node is not present here but instead it is provided
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
45 cluster_a15_opp_table: opp-table0 {
46 compatible = "operating-points-v2";
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000 1250000 1500000>;
52 clock-latency-ns = <140000>;
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500 1212500 1500000>;
57 clock-latency-ns = <140000>;
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000 1175000 1500000>;
62 clock-latency-ns = <140000>;
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500 1137500 1500000>;
67 clock-latency-ns = <140000>;
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500 1112500 1500000>;
72 clock-latency-ns = <140000>;
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500 1062500 1500000>;
77 clock-latency-ns = <140000>;
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500 1037500 1500000>;
82 clock-latency-ns = <140000>;
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500 1012500 1500000>;
87 clock-latency-ns = <140000>;
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500 987500 1500000>;
92 clock-latency-ns = <140000>;
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500 962500 1500000>;
97 clock-latency-ns = <140000>;
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500 937500 1500000>;
102 clock-latency-ns = <140000>;
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500 912500 1500000>;
107 clock-latency-ns = <140000>;
111 cluster_a7_opp_table: opp-table1 {
112 compatible = "operating-points-v2";
116 opp-hz = /bits/ 64 <1300000000>;
117 opp-microvolt = <1275000>;
118 clock-latency-ns = <140000>;
121 opp-hz = /bits/ 64 <1200000000>;
122 opp-microvolt = <1212500>;
123 clock-latency-ns = <140000>;
126 opp-hz = /bits/ 64 <1100000000>;
127 opp-microvolt = <1162500>;
128 clock-latency-ns = <140000>;
131 opp-hz = /bits/ 64 <1000000000>;
132 opp-microvolt = <1112500>;
133 clock-latency-ns = <140000>;
136 opp-hz = /bits/ 64 <900000000>;
137 opp-microvolt = <1062500>;
138 clock-latency-ns = <140000>;
141 opp-hz = /bits/ 64 <800000000>;
142 opp-microvolt = <1025000>;
143 clock-latency-ns = <140000>;
146 opp-hz = /bits/ 64 <700000000>;
147 opp-microvolt = <975000>;
148 clock-latency-ns = <140000>;
151 opp-hz = /bits/ 64 <600000000>;
152 opp-microvolt = <937500>;
153 clock-latency-ns = <140000>;
159 compatible = "arm,cci-400";
160 #address-cells = <1>;
162 reg = <0x10d20000 0x1000>;
163 ranges = <0x0 0x10d20000 0x6000>;
165 cci_control0: slave-if@4000 {
166 compatible = "arm,cci-400-ctrl-if";
167 interface-type = "ace";
168 reg = <0x4000 0x1000>;
170 cci_control1: slave-if@5000 {
171 compatible = "arm,cci-400-ctrl-if";
172 interface-type = "ace";
173 reg = <0x5000 0x1000>;
177 clock: clock-controller@10010000 {
178 compatible = "samsung,exynos5420-clock", "syscon";
179 reg = <0x10010000 0x30000>;
183 clock_audss: audss-clock-controller@3810000 {
184 compatible = "samsung,exynos5420-audss-clock";
185 reg = <0x03810000 0x0C>;
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
190 power-domains = <&mau_pd>;
193 mfc: codec@11000000 {
194 compatible = "samsung,mfc-v7";
195 reg = <0x11000000 0x10000>;
196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clock CLK_MFC>;
199 power-domains = <&mfc_pd>;
200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
201 iommu-names = "left", "right";
204 mmc_0: mmc@12200000 {
205 compatible = "samsung,exynos5420-dw-mshc-smu";
206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
209 reg = <0x12200000 0x2000>;
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
211 clock-names = "biu", "ciu";
216 mmc_1: mmc@12210000 {
217 compatible = "samsung,exynos5420-dw-mshc-smu";
218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
219 #address-cells = <1>;
221 reg = <0x12210000 0x2000>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
223 clock-names = "biu", "ciu";
228 mmc_2: mmc@12220000 {
229 compatible = "samsung,exynos5420-dw-mshc";
230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
233 reg = <0x12220000 0x1000>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
235 clock-names = "biu", "ciu";
240 dmc: memory-controller@10c20000 {
241 compatible = "samsung,exynos5422-dmc";
242 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
243 clocks = <&clock CLK_FOUT_SPLL>,
244 <&clock CLK_MOUT_SCLK_SPLL>,
245 <&clock CLK_FF_DOUT_SPLL2>,
246 <&clock CLK_FOUT_BPLL>,
247 <&clock CLK_MOUT_BPLL>,
248 <&clock CLK_SCLK_BPLL>,
249 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
250 <&clock CLK_MOUT_MCLK_CDREX>;
251 clock-names = "fout_spll",
257 "mout_mx_mspll_ccore",
259 samsung,syscon-clk = <&clock>;
263 nocp_mem0_0: nocp@10ca1000 {
264 compatible = "samsung,exynos5420-nocp";
265 reg = <0x10CA1000 0x200>;
269 nocp_mem0_1: nocp@10ca1400 {
270 compatible = "samsung,exynos5420-nocp";
271 reg = <0x10CA1400 0x200>;
275 nocp_mem1_0: nocp@10ca1800 {
276 compatible = "samsung,exynos5420-nocp";
277 reg = <0x10CA1800 0x200>;
281 nocp_mem1_1: nocp@10ca1c00 {
282 compatible = "samsung,exynos5420-nocp";
283 reg = <0x10CA1C00 0x200>;
287 nocp_g3d_0: nocp@11a51000 {
288 compatible = "samsung,exynos5420-nocp";
289 reg = <0x11A51000 0x200>;
293 nocp_g3d_1: nocp@11a51400 {
294 compatible = "samsung,exynos5420-nocp";
295 reg = <0x11A51400 0x200>;
299 ppmu_dmc0_0: ppmu@10d00000 {
300 compatible = "samsung,exynos-ppmu";
301 reg = <0x10d00000 0x2000>;
302 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
303 clock-names = "ppmu";
305 ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
306 event-name = "ppmu-event3-dmc0_0";
311 ppmu_dmc0_1: ppmu@10d10000 {
312 compatible = "samsung,exynos-ppmu";
313 reg = <0x10d10000 0x2000>;
314 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
315 clock-names = "ppmu";
317 ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
318 event-name = "ppmu-event3-dmc0_1";
323 ppmu_dmc1_0: ppmu@10d60000 {
324 compatible = "samsung,exynos-ppmu";
325 reg = <0x10d60000 0x2000>;
326 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
327 clock-names = "ppmu";
329 ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
330 event-name = "ppmu-event3-dmc1_0";
335 ppmu_dmc1_1: ppmu@10d70000 {
336 compatible = "samsung,exynos-ppmu";
337 reg = <0x10d70000 0x2000>;
338 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
339 clock-names = "ppmu";
341 ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
342 event-name = "ppmu-event3-dmc1_1";
347 gsc_pd: power-domain@10044000 {
348 compatible = "samsung,exynos4210-pd";
349 reg = <0x10044000 0x20>;
350 #power-domain-cells = <0>;
354 isp_pd: power-domain@10044020 {
355 compatible = "samsung,exynos4210-pd";
356 reg = <0x10044020 0x20>;
357 #power-domain-cells = <0>;
361 mfc_pd: power-domain@10044060 {
362 compatible = "samsung,exynos4210-pd";
363 reg = <0x10044060 0x20>;
364 #power-domain-cells = <0>;
368 g3d_pd: power-domain@10044080 {
369 compatible = "samsung,exynos4210-pd";
370 reg = <0x10044080 0x20>;
371 #power-domain-cells = <0>;
375 disp_pd: power-domain@100440c0 {
376 compatible = "samsung,exynos4210-pd";
377 reg = <0x100440C0 0x20>;
378 #power-domain-cells = <0>;
382 mau_pd: power-domain@100440e0 {
383 compatible = "samsung,exynos4210-pd";
384 reg = <0x100440E0 0x20>;
385 #power-domain-cells = <0>;
389 msc_pd: power-domain@10044120 {
390 compatible = "samsung,exynos4210-pd";
391 reg = <0x10044120 0x20>;
392 #power-domain-cells = <0>;
396 pinctrl_0: pinctrl@13400000 {
397 compatible = "samsung,exynos5420-pinctrl";
398 reg = <0x13400000 0x1000>;
399 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
401 wakeup-interrupt-controller {
402 compatible = "samsung,exynos4210-wakeup-eint";
403 interrupt-parent = <&gic>;
404 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
408 pinctrl_1: pinctrl@13410000 {
409 compatible = "samsung,exynos5420-pinctrl";
410 reg = <0x13410000 0x1000>;
411 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
414 pinctrl_2: pinctrl@14000000 {
415 compatible = "samsung,exynos5420-pinctrl";
416 reg = <0x14000000 0x1000>;
417 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
420 pinctrl_3: pinctrl@14010000 {
421 compatible = "samsung,exynos5420-pinctrl";
422 reg = <0x14010000 0x1000>;
423 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
426 pinctrl_4: pinctrl@3860000 {
427 compatible = "samsung,exynos5420-pinctrl";
428 reg = <0x03860000 0x1000>;
429 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
430 power-domains = <&mau_pd>;
434 compatible = "arm,pl330", "arm,primecell";
435 reg = <0x03880000 0x1000>;
436 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clock_audss EXYNOS_ADMA>;
438 clock-names = "apb_pclk";
441 #dma-requests = <16>;
442 power-domains = <&mau_pd>;
445 pdma0: pdma@121a0000 {
446 compatible = "arm,pl330", "arm,primecell";
447 reg = <0x121A0000 0x1000>;
448 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clock CLK_PDMA0>;
450 clock-names = "apb_pclk";
453 #dma-requests = <32>;
456 pdma1: pdma@121b0000 {
457 compatible = "arm,pl330", "arm,primecell";
458 reg = <0x121B0000 0x1000>;
459 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clock CLK_PDMA1>;
461 clock-names = "apb_pclk";
464 #dma-requests = <32>;
467 mdma0: mdma@10800000 {
468 compatible = "arm,pl330", "arm,primecell";
469 reg = <0x10800000 0x1000>;
470 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clock CLK_MDMA0>;
472 clock-names = "apb_pclk";
478 mdma1: mdma@11c10000 {
479 compatible = "arm,pl330", "arm,primecell";
480 reg = <0x11C10000 0x1000>;
481 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&clock CLK_MDMA1>;
483 clock-names = "apb_pclk";
488 * MDMA1 can support both secure and non-secure
489 * AXI transactions. When this is enabled in
490 * the kernel for boards that run in secure
491 * mode, we are getting imprecise external
492 * aborts causing the kernel to oops.
498 compatible = "samsung,exynos5420-i2s";
499 reg = <0x03830000 0x100>;
503 dma-names = "tx", "rx", "tx-sec";
504 clocks = <&clock_audss EXYNOS_I2S_BUS>,
505 <&clock_audss EXYNOS_I2S_BUS>,
506 <&clock_audss EXYNOS_SCLK_I2S>;
507 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
509 clock-output-names = "i2s_cdclk0";
510 #sound-dai-cells = <1>;
511 samsung,idma-addr = <0x03000000>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&i2s0_bus>;
514 power-domains = <&mau_pd>;
519 compatible = "samsung,exynos5420-i2s";
520 reg = <0x12D60000 0x100>;
523 dma-names = "tx", "rx";
524 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
525 clock-names = "iis", "i2s_opclk0";
527 clock-output-names = "i2s_cdclk1";
528 #sound-dai-cells = <1>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&i2s1_bus>;
535 compatible = "samsung,exynos5420-i2s";
536 reg = <0x12D70000 0x100>;
539 dma-names = "tx", "rx";
540 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
541 clock-names = "iis", "i2s_opclk0";
543 clock-output-names = "i2s_cdclk2";
544 #sound-dai-cells = <1>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2s2_bus>;
550 spi_0: spi@12d20000 {
551 compatible = "samsung,exynos4210-spi";
552 reg = <0x12d20000 0x100>;
553 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
556 dma-names = "tx", "rx";
557 #address-cells = <1>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&spi0_bus>;
561 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
562 clock-names = "spi", "spi_busclk0";
566 spi_1: spi@12d30000 {
567 compatible = "samsung,exynos4210-spi";
568 reg = <0x12d30000 0x100>;
569 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
572 dma-names = "tx", "rx";
573 #address-cells = <1>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&spi1_bus>;
577 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
578 clock-names = "spi", "spi_busclk0";
582 spi_2: spi@12d40000 {
583 compatible = "samsung,exynos4210-spi";
584 reg = <0x12d40000 0x100>;
585 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
588 dma-names = "tx", "rx";
589 #address-cells = <1>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&spi2_bus>;
593 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
594 clock-names = "spi", "spi_busclk0";
598 dp_phy: dp-video-phy {
599 compatible = "samsung,exynos5420-dp-video-phy";
600 samsung,pmu-syscon = <&pmu_system_controller>;
604 mipi_phy: mipi-video-phy {
605 compatible = "samsung,s5pv210-mipi-video-phy";
606 syscon = <&pmu_system_controller>;
611 compatible = "samsung,exynos5410-mipi-dsi";
612 reg = <0x14500000 0x10000>;
613 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
614 phys = <&mipi_phy 1>;
616 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
617 clock-names = "bus_clk", "pll_clk";
618 #address-cells = <1>;
623 hsi2c_8: i2c@12e00000 {
624 compatible = "samsung,exynos5250-hsi2c";
625 reg = <0x12E00000 0x1000>;
626 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
627 #address-cells = <1>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&i2c8_hs_bus>;
631 clocks = <&clock CLK_USI4>;
632 clock-names = "hsi2c";
636 hsi2c_9: i2c@12e10000 {
637 compatible = "samsung,exynos5250-hsi2c";
638 reg = <0x12E10000 0x1000>;
639 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
640 #address-cells = <1>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&i2c9_hs_bus>;
644 clocks = <&clock CLK_USI5>;
645 clock-names = "hsi2c";
649 hsi2c_10: i2c@12e20000 {
650 compatible = "samsung,exynos5250-hsi2c";
651 reg = <0x12E20000 0x1000>;
652 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
653 #address-cells = <1>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&i2c10_hs_bus>;
657 clocks = <&clock CLK_USI6>;
658 clock-names = "hsi2c";
662 hdmi: hdmi@14530000 {
663 compatible = "samsung,exynos5420-hdmi";
664 reg = <0x14530000 0x70000>;
665 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
667 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
668 <&clock CLK_MOUT_HDMI>;
669 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
670 "sclk_hdmiphy", "mout_hdmi";
672 samsung,syscon-phandle = <&pmu_system_controller>;
674 power-domains = <&disp_pd>;
675 #sound-dai-cells = <0>;
678 hdmiphy: hdmiphy@145d0000 {
679 reg = <0x145D0000 0x20>;
682 hdmicec: cec@101b0000 {
683 compatible = "samsung,s5p-cec";
684 reg = <0x101B0000 0x200>;
685 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&clock CLK_HDMI_CEC>;
687 clock-names = "hdmicec";
688 samsung,syscon-phandle = <&pmu_system_controller>;
689 hdmi-phandle = <&hdmi>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&hdmi_cec>;
695 mixer: mixer@14450000 {
696 compatible = "samsung,exynos5420-mixer";
697 reg = <0x14450000 0x10000>;
698 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
700 <&clock CLK_SCLK_HDMI>;
701 clock-names = "mixer", "hdmi", "sclk_hdmi";
702 power-domains = <&disp_pd>;
703 iommus = <&sysmmu_tv>;
707 rotator: rotator@11c00000 {
708 compatible = "samsung,exynos5250-rotator";
709 reg = <0x11C00000 0x64>;
710 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clock CLK_ROTATOR>;
712 clock-names = "rotator";
713 iommus = <&sysmmu_rotator>;
716 gsc_0: video-scaler@13e00000 {
717 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
718 reg = <0x13e00000 0x1000>;
719 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clock CLK_GSCL0>;
721 clock-names = "gscl";
722 power-domains = <&gsc_pd>;
723 iommus = <&sysmmu_gscl0>;
726 gsc_1: video-scaler@13e10000 {
727 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
728 reg = <0x13e10000 0x1000>;
729 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&clock CLK_GSCL1>;
731 clock-names = "gscl";
732 power-domains = <&gsc_pd>;
733 iommus = <&sysmmu_gscl1>;
737 compatible = "samsung,exynos5420-mali", "arm,mali-t628";
738 reg = <0x11800000 0x5000>;
739 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
742 interrupt-names = "job", "mmu", "gpu";
744 clocks = <&clock CLK_G3D>;
745 clock-names = "core";
746 power-domains = <&g3d_pd>;
747 operating-points-v2 = <&gpu_opp_table>;
750 #cooling-cells = <2>;
752 gpu_opp_table: opp-table {
753 compatible = "operating-points-v2";
756 opp-hz = /bits/ 64 <177000000>;
757 opp-microvolt = <812500>;
760 opp-hz = /bits/ 64 <266000000>;
761 opp-microvolt = <862500>;
764 opp-hz = /bits/ 64 <350000000>;
765 opp-microvolt = <912500>;
768 opp-hz = /bits/ 64 <420000000>;
769 opp-microvolt = <962500>;
772 opp-hz = /bits/ 64 <480000000>;
773 opp-microvolt = <1000000>;
776 opp-hz = /bits/ 64 <543000000>;
777 opp-microvolt = <1037500>;
780 opp-hz = /bits/ 64 <600000000>;
781 opp-microvolt = <1150000>;
786 scaler_0: scaler@12800000 {
787 compatible = "samsung,exynos5420-scaler";
788 reg = <0x12800000 0x1294>;
789 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&clock CLK_MSCL0>;
791 clock-names = "mscl";
792 power-domains = <&msc_pd>;
793 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
796 scaler_1: scaler@12810000 {
797 compatible = "samsung,exynos5420-scaler";
798 reg = <0x12810000 0x1294>;
799 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clock CLK_MSCL1>;
801 clock-names = "mscl";
802 power-domains = <&msc_pd>;
803 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
806 scaler_2: scaler@12820000 {
807 compatible = "samsung,exynos5420-scaler";
808 reg = <0x12820000 0x1294>;
809 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&clock CLK_MSCL2>;
811 clock-names = "mscl";
812 power-domains = <&msc_pd>;
813 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
816 jpeg_0: jpeg@11f50000 {
817 compatible = "samsung,exynos5420-jpeg";
818 reg = <0x11F50000 0x1000>;
819 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
820 clock-names = "jpeg";
821 clocks = <&clock CLK_JPEG>;
822 iommus = <&sysmmu_jpeg0>;
825 jpeg_1: jpeg@11f60000 {
826 compatible = "samsung,exynos5420-jpeg";
827 reg = <0x11F60000 0x1000>;
828 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
829 clock-names = "jpeg";
830 clocks = <&clock CLK_JPEG2>;
831 iommus = <&sysmmu_jpeg1>;
834 pmu_system_controller: system-controller@10040000 {
835 compatible = "samsung,exynos5420-pmu", "syscon";
836 reg = <0x10040000 0x5000>;
837 clock-names = "clkout16";
838 clocks = <&clock CLK_FIN_PLL>;
840 interrupt-controller;
841 #interrupt-cells = <3>;
842 interrupt-parent = <&gic>;
845 tmu_cpu0: tmu@10060000 {
846 compatible = "samsung,exynos5420-tmu";
847 reg = <0x10060000 0x100>;
848 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clock CLK_TMU>;
850 clock-names = "tmu_apbif";
851 #thermal-sensor-cells = <0>;
854 tmu_cpu1: tmu@10064000 {
855 compatible = "samsung,exynos5420-tmu";
856 reg = <0x10064000 0x100>;
857 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&clock CLK_TMU>;
859 clock-names = "tmu_apbif";
860 #thermal-sensor-cells = <0>;
863 tmu_cpu2: tmu@10068000 {
864 compatible = "samsung,exynos5420-tmu-ext-triminfo";
865 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
866 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
868 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
869 #thermal-sensor-cells = <0>;
872 tmu_cpu3: tmu@1006c000 {
873 compatible = "samsung,exynos5420-tmu-ext-triminfo";
874 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
875 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
877 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
878 #thermal-sensor-cells = <0>;
881 tmu_gpu: tmu@100a0000 {
882 compatible = "samsung,exynos5420-tmu-ext-triminfo";
883 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
884 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
886 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
887 #thermal-sensor-cells = <0>;
890 sysmmu_g2dr: sysmmu@10a60000 {
891 compatible = "samsung,exynos-sysmmu";
892 reg = <0x10A60000 0x1000>;
893 interrupt-parent = <&combiner>;
895 clock-names = "sysmmu", "master";
896 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
900 sysmmu_g2dw: sysmmu@10a70000 {
901 compatible = "samsung,exynos-sysmmu";
902 reg = <0x10A70000 0x1000>;
903 interrupt-parent = <&combiner>;
905 clock-names = "sysmmu", "master";
906 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
910 sysmmu_tv: sysmmu@14650000 {
911 compatible = "samsung,exynos-sysmmu";
912 reg = <0x14650000 0x1000>;
913 interrupt-parent = <&combiner>;
915 clock-names = "sysmmu", "master";
916 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
917 power-domains = <&disp_pd>;
921 sysmmu_gscl0: sysmmu@13e80000 {
922 compatible = "samsung,exynos-sysmmu";
923 reg = <0x13E80000 0x1000>;
924 interrupt-parent = <&combiner>;
926 clock-names = "sysmmu", "master";
927 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
928 power-domains = <&gsc_pd>;
932 sysmmu_gscl1: sysmmu@13e90000 {
933 compatible = "samsung,exynos-sysmmu";
934 reg = <0x13E90000 0x1000>;
935 interrupt-parent = <&combiner>;
937 clock-names = "sysmmu", "master";
938 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
939 power-domains = <&gsc_pd>;
943 sysmmu_scaler0r: sysmmu@12880000 {
944 compatible = "samsung,exynos-sysmmu";
945 reg = <0x12880000 0x1000>;
946 interrupt-parent = <&combiner>;
948 clock-names = "sysmmu", "master";
949 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
950 power-domains = <&msc_pd>;
954 sysmmu_scaler1r: sysmmu@12890000 {
955 compatible = "samsung,exynos-sysmmu";
956 reg = <0x12890000 0x1000>;
957 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
958 clock-names = "sysmmu", "master";
959 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
960 power-domains = <&msc_pd>;
964 sysmmu_scaler2r: sysmmu@128a0000 {
965 compatible = "samsung,exynos-sysmmu";
966 reg = <0x128A0000 0x1000>;
967 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
968 clock-names = "sysmmu", "master";
969 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
970 power-domains = <&msc_pd>;
974 sysmmu_scaler0w: sysmmu@128c0000 {
975 compatible = "samsung,exynos-sysmmu";
976 reg = <0x128C0000 0x1000>;
977 interrupt-parent = <&combiner>;
979 clock-names = "sysmmu", "master";
980 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
981 power-domains = <&msc_pd>;
985 sysmmu_scaler1w: sysmmu@128d0000 {
986 compatible = "samsung,exynos-sysmmu";
987 reg = <0x128D0000 0x1000>;
988 interrupt-parent = <&combiner>;
990 clock-names = "sysmmu", "master";
991 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
992 power-domains = <&msc_pd>;
996 sysmmu_scaler2w: sysmmu@128e0000 {
997 compatible = "samsung,exynos-sysmmu";
998 reg = <0x128E0000 0x1000>;
999 interrupt-parent = <&combiner>;
1000 interrupts = <19 6>;
1001 clock-names = "sysmmu", "master";
1002 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1003 power-domains = <&msc_pd>;
1007 sysmmu_rotator: sysmmu@11d40000 {
1008 compatible = "samsung,exynos-sysmmu";
1009 reg = <0x11D40000 0x1000>;
1010 interrupt-parent = <&combiner>;
1012 clock-names = "sysmmu", "master";
1013 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1017 sysmmu_jpeg0: sysmmu@11f10000 {
1018 compatible = "samsung,exynos-sysmmu";
1019 reg = <0x11F10000 0x1000>;
1020 interrupt-parent = <&combiner>;
1022 clock-names = "sysmmu", "master";
1023 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1027 sysmmu_jpeg1: sysmmu@11f20000 {
1028 compatible = "samsung,exynos-sysmmu";
1029 reg = <0x11F20000 0x1000>;
1030 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1031 clock-names = "sysmmu", "master";
1032 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1036 sysmmu_mfc_l: sysmmu@11200000 {
1037 compatible = "samsung,exynos-sysmmu";
1038 reg = <0x11200000 0x1000>;
1039 interrupt-parent = <&combiner>;
1041 clock-names = "sysmmu", "master";
1042 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1043 power-domains = <&mfc_pd>;
1047 sysmmu_mfc_r: sysmmu@11210000 {
1048 compatible = "samsung,exynos-sysmmu";
1049 reg = <0x11210000 0x1000>;
1050 interrupt-parent = <&combiner>;
1052 clock-names = "sysmmu", "master";
1053 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1054 power-domains = <&mfc_pd>;
1058 sysmmu_fimd1_0: sysmmu@14640000 {
1059 compatible = "samsung,exynos-sysmmu";
1060 reg = <0x14640000 0x1000>;
1061 interrupt-parent = <&combiner>;
1063 clock-names = "sysmmu", "master";
1064 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1065 power-domains = <&disp_pd>;
1069 sysmmu_fimd1_1: sysmmu@14680000 {
1070 compatible = "samsung,exynos-sysmmu";
1071 reg = <0x14680000 0x1000>;
1072 interrupt-parent = <&combiner>;
1074 clock-names = "sysmmu", "master";
1075 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1076 power-domains = <&disp_pd>;
1080 bus_wcore: bus-wcore {
1081 compatible = "samsung,exynos-bus";
1082 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1083 clock-names = "bus";
1084 status = "disabled";
1088 compatible = "samsung,exynos-bus";
1089 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1090 clock-names = "bus";
1091 status = "disabled";
1094 bus_fsys_apb: bus-fsys-apb {
1095 compatible = "samsung,exynos-bus";
1096 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1097 clock-names = "bus";
1098 status = "disabled";
1101 bus_fsys: bus-fsys {
1102 compatible = "samsung,exynos-bus";
1103 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1104 clock-names = "bus";
1105 status = "disabled";
1108 bus_fsys2: bus-fsys2 {
1109 compatible = "samsung,exynos-bus";
1110 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1111 clock-names = "bus";
1112 status = "disabled";
1116 compatible = "samsung,exynos-bus";
1117 clocks = <&clock CLK_DOUT_ACLK333>;
1118 clock-names = "bus";
1119 status = "disabled";
1123 compatible = "samsung,exynos-bus";
1124 clocks = <&clock CLK_DOUT_ACLK266>;
1125 clock-names = "bus";
1126 status = "disabled";
1129 bus_peri: bus-peri {
1130 compatible = "samsung,exynos-bus";
1131 clocks = <&clock CLK_DOUT_ACLK66>;
1132 clock-names = "bus";
1133 status = "disabled";
1137 compatible = "samsung,exynos-bus";
1138 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1139 clock-names = "bus";
1140 status = "disabled";
1143 bus_g2d_acp: bus-g2d-acp {
1144 compatible = "samsung,exynos-bus";
1145 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1146 clock-names = "bus";
1147 status = "disabled";
1150 bus_jpeg: bus-jpeg {
1151 compatible = "samsung,exynos-bus";
1152 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1153 clock-names = "bus";
1154 status = "disabled";
1157 bus_jpeg_apb: bus-jpeg-apb {
1158 compatible = "samsung,exynos-bus";
1159 clocks = <&clock CLK_DOUT_ACLK166>;
1160 clock-names = "bus";
1161 status = "disabled";
1164 bus_disp1_fimd: bus-disp1-fimd {
1165 compatible = "samsung,exynos-bus";
1166 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1167 clock-names = "bus";
1168 status = "disabled";
1171 bus_disp1: bus-disp1 {
1172 compatible = "samsung,exynos-bus";
1173 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1174 clock-names = "bus";
1175 status = "disabled";
1178 bus_gscl_scaler: bus-gscl-scaler {
1179 compatible = "samsung,exynos-bus";
1180 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1181 clock-names = "bus";
1182 status = "disabled";
1185 bus_mscl: bus-mscl {
1186 compatible = "samsung,exynos-bus";
1187 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1188 clock-names = "bus";
1189 status = "disabled";
1194 cpu0_thermal: cpu0-thermal {
1195 thermal-sensors = <&tmu_cpu0>;
1196 #include "exynos5420-trip-points.dtsi"
1198 cpu1_thermal: cpu1-thermal {
1199 thermal-sensors = <&tmu_cpu1>;
1200 #include "exynos5420-trip-points.dtsi"
1202 cpu2_thermal: cpu2-thermal {
1203 thermal-sensors = <&tmu_cpu2>;
1204 #include "exynos5420-trip-points.dtsi"
1206 cpu3_thermal: cpu3-thermal {
1207 thermal-sensors = <&tmu_cpu3>;
1208 #include "exynos5420-trip-points.dtsi"
1210 gpu_thermal: gpu-thermal {
1211 thermal-sensors = <&tmu_gpu>;
1212 #include "exynos5420-trip-points.dtsi"
1218 clocks = <&clock CLK_TSADC>;
1219 clock-names = "adc";
1220 samsung,syscon-phandle = <&pmu_system_controller>;
1224 clocks = <&clock CLK_DP1>;
1228 power-domains = <&disp_pd>;
1232 compatible = "samsung,exynos5420-fimd";
1233 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1234 clock-names = "sclk_fimd", "fimd";
1235 power-domains = <&disp_pd>;
1236 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1237 iommu-names = "m0", "m1";
1241 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1242 clocks = <&clock CLK_G2D>;
1243 clock-names = "fimg2d";
1248 clocks = <&clock CLK_I2C0>;
1249 clock-names = "i2c";
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&i2c0_bus>;
1255 clocks = <&clock CLK_I2C1>;
1256 clock-names = "i2c";
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&i2c1_bus>;
1262 clocks = <&clock CLK_I2C2>;
1263 clock-names = "i2c";
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&i2c2_bus>;
1269 clocks = <&clock CLK_I2C3>;
1270 clock-names = "i2c";
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&i2c3_bus>;
1276 clocks = <&clock CLK_USI0>;
1277 clock-names = "hsi2c";
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&i2c4_hs_bus>;
1283 clocks = <&clock CLK_USI1>;
1284 clock-names = "hsi2c";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&i2c5_hs_bus>;
1290 clocks = <&clock CLK_USI2>;
1291 clock-names = "hsi2c";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&i2c6_hs_bus>;
1297 clocks = <&clock CLK_USI3>;
1298 clock-names = "hsi2c";
1299 pinctrl-names = "default";
1300 pinctrl-0 = <&i2c7_hs_bus>;
1304 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1305 clock-names = "fin_pll", "mct";
1309 clocks = <&clock CLK_SSS>;
1310 clock-names = "secss";
1314 clocks = <&clock CLK_PWM>;
1315 clock-names = "timers";
1319 clocks = <&clock CLK_RTC>;
1320 clock-names = "rtc";
1321 interrupt-parent = <&pmu_system_controller>;
1322 status = "disabled";
1326 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1327 clock-names = "uart", "clk_uart_baud0";
1328 dmas = <&pdma0 13>, <&pdma0 14>;
1329 dma-names = "rx", "tx";
1333 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1334 clock-names = "uart", "clk_uart_baud0";
1335 dmas = <&pdma1 15>, <&pdma1 16>;
1336 dma-names = "rx", "tx";
1340 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1341 clock-names = "uart", "clk_uart_baud0";
1342 dmas = <&pdma0 15>, <&pdma0 16>;
1343 dma-names = "rx", "tx";
1347 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1348 clock-names = "uart", "clk_uart_baud0";
1349 dmas = <&pdma1 17>, <&pdma1 18>;
1350 dma-names = "rx", "tx";
1354 clocks = <&clock CLK_SSS>;
1355 clock-names = "secss";
1359 clocks = <&clock CLK_SSS>;
1360 clock-names = "secss";
1364 clocks = <&clock CLK_USBD300>;
1365 clock-names = "usbdrd30";
1369 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1370 clock-names = "phy", "ref";
1371 samsung,pmu-syscon = <&pmu_system_controller>;
1375 clocks = <&clock CLK_USBD301>;
1376 clock-names = "usbdrd30";
1380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1384 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1385 clock-names = "phy", "ref";
1386 samsung,pmu-syscon = <&pmu_system_controller>;
1390 clocks = <&clock CLK_USBH20>;
1391 clock-names = "usbhost";
1395 clocks = <&clock CLK_USBH20>;
1396 clock-names = "usbhost";
1400 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1401 clock-names = "phy", "ref";
1402 samsung,sysreg-phandle = <&sysreg_system_controller>;
1403 samsung,pmureg-phandle = <&pmu_system_controller>;
1407 clocks = <&clock CLK_WDT>;
1408 clock-names = "watchdog";
1409 samsung,syscon-phandle = <&pmu_system_controller>;
1412 #include "exynos5420-pinctrl.dtsi"
1413 #include "exynos-syscon-restart.dtsi"