2 * SAMSUNG EXYNOS5420 SoC device tree source
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
8 * EXYNOS5420 based board files can include this file and provide
9 * values for board specfic bindings.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <dt-bindings/clock/exynos5420.h>
17 #include "exynos5.dtsi"
18 #include "exynos5420-pinctrl.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5420", "samsung,exynos5";
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 pinctrl2 = &pinctrl_2;
32 pinctrl3 = &pinctrl_3;
33 pinctrl4 = &pinctrl_4;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
60 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
68 compatible = "arm,cortex-a15";
70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
76 compatible = "arm,cortex-a15";
78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
84 compatible = "arm,cortex-a15";
86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
92 compatible = "arm,cortex-a7";
94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
100 compatible = "arm,cortex-a7";
102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
108 compatible = "arm,cortex-a7";
110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
116 compatible = "arm,cortex-a7";
118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
150 compatible = "samsung,exynos4210-sysram";
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
160 clock: clock-controller@10010000 {
161 compatible = "samsung,exynos5420-clock";
162 reg = <0x10010000 0x30000>;
166 clock_audss: audss-clock-controller@3810000 {
167 compatible = "samsung,exynos5420-audss-clock";
168 reg = <0x03810000 0x0C>;
170 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
171 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
175 mfc: codec@11000000 {
176 compatible = "samsung,mfc-v7";
177 reg = <0x11000000 0x10000>;
178 interrupts = <0 96 0>;
179 clocks = <&clock CLK_MFC>;
181 power-domains = <&mfc_pd>;
184 mmc_0: mmc@12200000 {
185 compatible = "samsung,exynos5420-dw-mshc-smu";
186 interrupts = <0 75 0>;
187 #address-cells = <1>;
189 reg = <0x12200000 0x2000>;
190 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
191 clock-names = "biu", "ciu";
196 mmc_1: mmc@12210000 {
197 compatible = "samsung,exynos5420-dw-mshc-smu";
198 interrupts = <0 76 0>;
199 #address-cells = <1>;
201 reg = <0x12210000 0x2000>;
202 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
203 clock-names = "biu", "ciu";
208 mmc_2: mmc@12220000 {
209 compatible = "samsung,exynos5420-dw-mshc";
210 interrupts = <0 77 0>;
211 #address-cells = <1>;
213 reg = <0x12220000 0x1000>;
214 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
215 clock-names = "biu", "ciu";
221 compatible = "samsung,exynos4210-mct";
222 reg = <0x101C0000 0x800>;
223 interrupt-controller;
224 #interrups-cells = <1>;
225 interrupt-parent = <&mct_map>;
226 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
227 <8>, <9>, <10>, <11>;
228 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
229 clock-names = "fin_pll", "mct";
232 #interrupt-cells = <1>;
233 #address-cells = <0>;
235 interrupt-map = <0 &combiner 23 3>,
250 gsc_pd: power-domain@10044000 {
251 compatible = "samsung,exynos4210-pd";
252 reg = <0x10044000 0x20>;
253 #power-domain-cells = <0>;
256 isp_pd: power-domain@10044020 {
257 compatible = "samsung,exynos4210-pd";
258 reg = <0x10044020 0x20>;
259 #power-domain-cells = <0>;
262 mfc_pd: power-domain@10044060 {
263 compatible = "samsung,exynos4210-pd";
264 reg = <0x10044060 0x20>;
265 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
266 <&clock CLK_MOUT_USER_ACLK333>;
267 clock-names = "oscclk", "pclk0", "clk0";
268 #power-domain-cells = <0>;
271 msc_pd: power-domain@10044120 {
272 compatible = "samsung,exynos4210-pd";
273 reg = <0x10044120 0x20>;
274 #power-domain-cells = <0>;
277 disp_pd: power-domain@100440C0 {
278 compatible = "samsung,exynos4210-pd";
279 reg = <0x100440C0 0x20>;
280 #power-domain-cells = <0>;
281 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
282 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
283 <&clock CLK_MOUT_SW_ACLK300>,
284 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
285 <&clock CLK_MOUT_SW_ACLK400>,
286 <&clock CLK_MOUT_USER_ACLK400_DISP1>;
287 clock-names = "oscclk", "pclk0", "clk0",
288 "pclk1", "clk1", "pclk2", "clk2";
291 pinctrl_0: pinctrl@13400000 {
292 compatible = "samsung,exynos5420-pinctrl";
293 reg = <0x13400000 0x1000>;
294 interrupts = <0 45 0>;
296 wakeup-interrupt-controller {
297 compatible = "samsung,exynos4210-wakeup-eint";
298 interrupt-parent = <&gic>;
299 interrupts = <0 32 0>;
303 pinctrl_1: pinctrl@13410000 {
304 compatible = "samsung,exynos5420-pinctrl";
305 reg = <0x13410000 0x1000>;
306 interrupts = <0 78 0>;
309 pinctrl_2: pinctrl@14000000 {
310 compatible = "samsung,exynos5420-pinctrl";
311 reg = <0x14000000 0x1000>;
312 interrupts = <0 46 0>;
315 pinctrl_3: pinctrl@14010000 {
316 compatible = "samsung,exynos5420-pinctrl";
317 reg = <0x14010000 0x1000>;
318 interrupts = <0 50 0>;
321 pinctrl_4: pinctrl@03860000 {
322 compatible = "samsung,exynos5420-pinctrl";
323 reg = <0x03860000 0x1000>;
324 interrupts = <0 47 0>;
328 clocks = <&clock CLK_RTC>;
334 #address-cells = <1>;
336 compatible = "arm,amba-bus";
337 interrupt-parent = <&gic>;
340 adma: adma@03880000 {
341 compatible = "arm,pl330", "arm,primecell";
342 reg = <0x03880000 0x1000>;
343 interrupts = <0 110 0>;
344 clocks = <&clock_audss EXYNOS_ADMA>;
345 clock-names = "apb_pclk";
348 #dma-requests = <16>;
351 pdma0: pdma@121A0000 {
352 compatible = "arm,pl330", "arm,primecell";
353 reg = <0x121A0000 0x1000>;
354 interrupts = <0 34 0>;
355 clocks = <&clock CLK_PDMA0>;
356 clock-names = "apb_pclk";
359 #dma-requests = <32>;
362 pdma1: pdma@121B0000 {
363 compatible = "arm,pl330", "arm,primecell";
364 reg = <0x121B0000 0x1000>;
365 interrupts = <0 35 0>;
366 clocks = <&clock CLK_PDMA1>;
367 clock-names = "apb_pclk";
370 #dma-requests = <32>;
373 mdma0: mdma@10800000 {
374 compatible = "arm,pl330", "arm,primecell";
375 reg = <0x10800000 0x1000>;
376 interrupts = <0 33 0>;
377 clocks = <&clock CLK_MDMA0>;
378 clock-names = "apb_pclk";
384 mdma1: mdma@11C10000 {
385 compatible = "arm,pl330", "arm,primecell";
386 reg = <0x11C10000 0x1000>;
387 interrupts = <0 124 0>;
388 clocks = <&clock CLK_MDMA1>;
389 clock-names = "apb_pclk";
394 * MDMA1 can support both secure and non-secure
395 * AXI transactions. When this is enabled in the kernel
396 * for boards that run in secure mode, we are getting
397 * imprecise external aborts causing the kernel to oops.
404 compatible = "samsung,exynos5420-i2s";
405 reg = <0x03830000 0x100>;
409 dma-names = "tx", "rx", "tx-sec";
410 clocks = <&clock_audss EXYNOS_I2S_BUS>,
411 <&clock_audss EXYNOS_I2S_BUS>,
412 <&clock_audss EXYNOS_SCLK_I2S>;
413 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
414 samsung,idma-addr = <0x03000000>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&i2s0_bus>;
421 compatible = "samsung,exynos5420-i2s";
422 reg = <0x12D60000 0x100>;
425 dma-names = "tx", "rx";
426 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
427 clock-names = "iis", "i2s_opclk0";
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2s1_bus>;
434 compatible = "samsung,exynos5420-i2s";
435 reg = <0x12D70000 0x100>;
438 dma-names = "tx", "rx";
439 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
440 clock-names = "iis", "i2s_opclk0";
441 pinctrl-names = "default";
442 pinctrl-0 = <&i2s2_bus>;
446 spi_0: spi@12d20000 {
447 compatible = "samsung,exynos4210-spi";
448 reg = <0x12d20000 0x100>;
449 interrupts = <0 68 0>;
452 dma-names = "tx", "rx";
453 #address-cells = <1>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&spi0_bus>;
457 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
458 clock-names = "spi", "spi_busclk0";
462 spi_1: spi@12d30000 {
463 compatible = "samsung,exynos4210-spi";
464 reg = <0x12d30000 0x100>;
465 interrupts = <0 69 0>;
468 dma-names = "tx", "rx";
469 #address-cells = <1>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&spi1_bus>;
473 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
474 clock-names = "spi", "spi_busclk0";
478 spi_2: spi@12d40000 {
479 compatible = "samsung,exynos4210-spi";
480 reg = <0x12d40000 0x100>;
481 interrupts = <0 70 0>;
484 dma-names = "tx", "rx";
485 #address-cells = <1>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&spi2_bus>;
489 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
490 clock-names = "spi", "spi_busclk0";
494 uart_0: serial@12C00000 {
495 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
496 clock-names = "uart", "clk_uart_baud0";
499 uart_1: serial@12C10000 {
500 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
501 clock-names = "uart", "clk_uart_baud0";
504 uart_2: serial@12C20000 {
505 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
506 clock-names = "uart", "clk_uart_baud0";
509 uart_3: serial@12C30000 {
510 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
511 clock-names = "uart", "clk_uart_baud0";
515 compatible = "samsung,exynos4210-pwm";
516 reg = <0x12dd0000 0x100>;
517 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
519 clocks = <&clock CLK_PWM>;
520 clock-names = "timers";
523 dp_phy: video-phy@10040728 {
524 compatible = "samsung,exynos5420-dp-video-phy";
525 samsung,pmu-syscon = <&pmu_system_controller>;
529 dp: dp-controller@145B0000 {
530 clocks = <&clock CLK_DP1>;
536 mipi_phy: video-phy@10040714 {
537 compatible = "samsung,s5pv210-mipi-video-phy";
538 reg = <0x10040714 12>;
543 compatible = "samsung,exynos5410-mipi-dsi";
544 reg = <0x14500000 0x10000>;
545 interrupts = <0 82 0>;
546 phys = <&mipi_phy 1>;
548 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
549 clock-names = "bus_clk", "pll_clk";
550 #address-cells = <1>;
555 fimd: fimd@14400000 {
556 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
557 clock-names = "sclk_fimd", "fimd";
558 power-domains = <&disp_pd>;
562 compatible = "samsung,exynos-adc-v2";
563 reg = <0x12D10000 0x100>;
564 interrupts = <0 106 0>;
565 clocks = <&clock CLK_TSADC>;
567 #io-channel-cells = <1>;
569 samsung,syscon-phandle = <&pmu_system_controller>;
573 i2c_0: i2c@12C60000 {
574 compatible = "samsung,s3c2440-i2c";
575 reg = <0x12C60000 0x100>;
576 interrupts = <0 56 0>;
577 #address-cells = <1>;
579 clocks = <&clock CLK_I2C0>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c0_bus>;
583 samsung,sysreg-phandle = <&sysreg_system_controller>;
587 i2c_1: i2c@12C70000 {
588 compatible = "samsung,s3c2440-i2c";
589 reg = <0x12C70000 0x100>;
590 interrupts = <0 57 0>;
591 #address-cells = <1>;
593 clocks = <&clock CLK_I2C1>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c1_bus>;
597 samsung,sysreg-phandle = <&sysreg_system_controller>;
601 i2c_2: i2c@12C80000 {
602 compatible = "samsung,s3c2440-i2c";
603 reg = <0x12C80000 0x100>;
604 interrupts = <0 58 0>;
605 #address-cells = <1>;
607 clocks = <&clock CLK_I2C2>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&i2c2_bus>;
611 samsung,sysreg-phandle = <&sysreg_system_controller>;
615 i2c_3: i2c@12C90000 {
616 compatible = "samsung,s3c2440-i2c";
617 reg = <0x12C90000 0x100>;
618 interrupts = <0 59 0>;
619 #address-cells = <1>;
621 clocks = <&clock CLK_I2C3>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&i2c3_bus>;
625 samsung,sysreg-phandle = <&sysreg_system_controller>;
629 hsi2c_4: i2c@12CA0000 {
630 compatible = "samsung,exynos5-hsi2c";
631 reg = <0x12CA0000 0x1000>;
632 interrupts = <0 60 0>;
633 #address-cells = <1>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&i2c4_hs_bus>;
637 clocks = <&clock CLK_USI0>;
638 clock-names = "hsi2c";
642 hsi2c_5: i2c@12CB0000 {
643 compatible = "samsung,exynos5-hsi2c";
644 reg = <0x12CB0000 0x1000>;
645 interrupts = <0 61 0>;
646 #address-cells = <1>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&i2c5_hs_bus>;
650 clocks = <&clock CLK_USI1>;
651 clock-names = "hsi2c";
655 hsi2c_6: i2c@12CC0000 {
656 compatible = "samsung,exynos5-hsi2c";
657 reg = <0x12CC0000 0x1000>;
658 interrupts = <0 62 0>;
659 #address-cells = <1>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&i2c6_hs_bus>;
663 clocks = <&clock CLK_USI2>;
664 clock-names = "hsi2c";
668 hsi2c_7: i2c@12CD0000 {
669 compatible = "samsung,exynos5-hsi2c";
670 reg = <0x12CD0000 0x1000>;
671 interrupts = <0 63 0>;
672 #address-cells = <1>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&i2c7_hs_bus>;
676 clocks = <&clock CLK_USI3>;
677 clock-names = "hsi2c";
681 hsi2c_8: i2c@12E00000 {
682 compatible = "samsung,exynos5-hsi2c";
683 reg = <0x12E00000 0x1000>;
684 interrupts = <0 87 0>;
685 #address-cells = <1>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&i2c8_hs_bus>;
689 clocks = <&clock CLK_USI4>;
690 clock-names = "hsi2c";
694 hsi2c_9: i2c@12E10000 {
695 compatible = "samsung,exynos5-hsi2c";
696 reg = <0x12E10000 0x1000>;
697 interrupts = <0 88 0>;
698 #address-cells = <1>;
700 pinctrl-names = "default";
701 pinctrl-0 = <&i2c9_hs_bus>;
702 clocks = <&clock CLK_USI5>;
703 clock-names = "hsi2c";
707 hsi2c_10: i2c@12E20000 {
708 compatible = "samsung,exynos5-hsi2c";
709 reg = <0x12E20000 0x1000>;
710 interrupts = <0 203 0>;
711 #address-cells = <1>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&i2c10_hs_bus>;
715 clocks = <&clock CLK_USI6>;
716 clock-names = "hsi2c";
720 hdmi: hdmi@14530000 {
721 compatible = "samsung,exynos5420-hdmi";
722 reg = <0x14530000 0x70000>;
723 interrupts = <0 95 0>;
724 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
725 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
726 <&clock CLK_MOUT_HDMI>;
727 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
728 "sclk_hdmiphy", "mout_hdmi";
730 samsung,syscon-phandle = <&pmu_system_controller>;
732 power-domains = <&disp_pd>;
735 hdmiphy: hdmiphy@145D0000 {
736 reg = <0x145D0000 0x20>;
739 mixer: mixer@14450000 {
740 compatible = "samsung,exynos5420-mixer";
741 reg = <0x14450000 0x10000>;
742 interrupts = <0 94 0>;
743 clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
744 clock-names = "mixer", "sclk_hdmi";
745 power-domains = <&disp_pd>;
748 gsc_0: video-scaler@13e00000 {
749 compatible = "samsung,exynos5-gsc";
750 reg = <0x13e00000 0x1000>;
751 interrupts = <0 85 0>;
752 clocks = <&clock CLK_GSCL0>;
753 clock-names = "gscl";
754 power-domains = <&gsc_pd>;
757 gsc_1: video-scaler@13e10000 {
758 compatible = "samsung,exynos5-gsc";
759 reg = <0x13e10000 0x1000>;
760 interrupts = <0 86 0>;
761 clocks = <&clock CLK_GSCL1>;
762 clock-names = "gscl";
763 power-domains = <&gsc_pd>;
766 pmu_system_controller: system-controller@10040000 {
767 compatible = "samsung,exynos5420-pmu", "syscon";
768 reg = <0x10040000 0x5000>;
769 clock-names = "clkout16";
770 clocks = <&clock CLK_FIN_PLL>;
774 sysreg_system_controller: syscon@10050000 {
775 compatible = "samsung,exynos5-sysreg", "syscon";
776 reg = <0x10050000 0x5000>;
779 tmu_cpu0: tmu@10060000 {
780 compatible = "samsung,exynos5420-tmu";
781 reg = <0x10060000 0x100>;
782 interrupts = <0 65 0>;
783 clocks = <&clock CLK_TMU>;
784 clock-names = "tmu_apbif";
787 tmu_cpu1: tmu@10064000 {
788 compatible = "samsung,exynos5420-tmu";
789 reg = <0x10064000 0x100>;
790 interrupts = <0 183 0>;
791 clocks = <&clock CLK_TMU>;
792 clock-names = "tmu_apbif";
795 tmu_cpu2: tmu@10068000 {
796 compatible = "samsung,exynos5420-tmu-ext-triminfo";
797 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
798 interrupts = <0 184 0>;
799 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
800 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
803 tmu_cpu3: tmu@1006c000 {
804 compatible = "samsung,exynos5420-tmu-ext-triminfo";
805 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
806 interrupts = <0 185 0>;
807 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
808 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
811 tmu_gpu: tmu@100a0000 {
812 compatible = "samsung,exynos5420-tmu-ext-triminfo";
813 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
814 interrupts = <0 215 0>;
815 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
816 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
819 watchdog: watchdog@101D0000 {
820 compatible = "samsung,exynos5420-wdt";
821 reg = <0x101D0000 0x100>;
822 interrupts = <0 42 0>;
823 clocks = <&clock CLK_WDT>;
824 clock-names = "watchdog";
825 samsung,syscon-phandle = <&pmu_system_controller>;
829 compatible = "samsung,exynos4210-secss";
830 reg = <0x10830000 0x10000>;
831 interrupts = <0 112 0>;
832 clocks = <&clock CLK_SSS>;
833 clock-names = "secss";
836 usbdrd3_0: usb@12000000 {
837 compatible = "samsung,exynos5250-dwusb3";
838 clocks = <&clock CLK_USBD300>;
839 clock-names = "usbdrd30";
840 #address-cells = <1>;
844 usbdrd_dwc3_0: dwc3 {
845 compatible = "snps,dwc3";
846 reg = <0x12000000 0x10000>;
847 interrupts = <0 72 0>;
848 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
849 phy-names = "usb2-phy", "usb3-phy";
853 usbdrd_phy0: phy@12100000 {
854 compatible = "samsung,exynos5420-usbdrd-phy";
855 reg = <0x12100000 0x100>;
856 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
857 clock-names = "phy", "ref";
858 samsung,pmu-syscon = <&pmu_system_controller>;
862 usbdrd3_1: usb@12400000 {
863 compatible = "samsung,exynos5250-dwusb3";
864 clocks = <&clock CLK_USBD301>;
865 clock-names = "usbdrd30";
866 #address-cells = <1>;
870 usbdrd_dwc3_1: dwc3 {
871 compatible = "snps,dwc3";
872 reg = <0x12400000 0x10000>;
873 interrupts = <0 73 0>;
874 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
875 phy-names = "usb2-phy", "usb3-phy";
879 usbdrd_phy1: phy@12500000 {
880 compatible = "samsung,exynos5420-usbdrd-phy";
881 reg = <0x12500000 0x100>;
882 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
883 clock-names = "phy", "ref";
884 samsung,pmu-syscon = <&pmu_system_controller>;
888 usbhost2: usb@12110000 {
889 compatible = "samsung,exynos4210-ehci";
890 reg = <0x12110000 0x100>;
891 interrupts = <0 71 0>;
893 clocks = <&clock CLK_USBH20>;
894 clock-names = "usbhost";
895 #address-cells = <1>;
899 phys = <&usb2_phy 1>;
903 usbhost1: usb@12120000 {
904 compatible = "samsung,exynos4210-ohci";
905 reg = <0x12120000 0x100>;
906 interrupts = <0 71 0>;
908 clocks = <&clock CLK_USBH20>;
909 clock-names = "usbhost";
910 #address-cells = <1>;
914 phys = <&usb2_phy 1>;
918 usb2_phy: phy@12130000 {
919 compatible = "samsung,exynos5250-usb2-phy";
920 reg = <0x12130000 0x100>;
921 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
922 clock-names = "phy", "ref";
924 samsung,sysreg-phandle = <&sysreg_system_controller>;
925 samsung,pmureg-phandle = <&pmu_system_controller>;