2 * SAMSUNG EXYNOS5420 SoC cpu device tree source
4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This file provides desired ordering for Exynos5420 and Exynos5800
8 * boards: CPU[0123] being the A15.
10 * The Exynos5420, 5422 and 5800 actually share the same CPU configuration
11 * but particular boards choose different booting order.
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
14 * booting cluster (big or LITTLE) is chosen by IROM code by reading
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
30 compatible = "arm,cortex-a15";
32 clocks = <&clock CLK_ARM_CLK>;
33 clock-frequency = <1800000000>;
34 cci-control-port = <&cci_control1>;
35 operating-points-v2 = <&cluster_a15_opp_table>;
36 cooling-min-level = <0>;
37 cooling-max-level = <11>;
38 #cooling-cells = <2>; /* min followed by max */
39 capacity-dmips-mhz = <1024>;
44 compatible = "arm,cortex-a15";
46 clock-frequency = <1800000000>;
47 cci-control-port = <&cci_control1>;
48 operating-points-v2 = <&cluster_a15_opp_table>;
49 cooling-min-level = <0>;
50 cooling-max-level = <11>;
51 #cooling-cells = <2>; /* min followed by max */
52 capacity-dmips-mhz = <1024>;
57 compatible = "arm,cortex-a15";
59 clock-frequency = <1800000000>;
60 cci-control-port = <&cci_control1>;
61 operating-points-v2 = <&cluster_a15_opp_table>;
62 cooling-min-level = <0>;
63 cooling-max-level = <11>;
64 #cooling-cells = <2>; /* min followed by max */
65 capacity-dmips-mhz = <1024>;
70 compatible = "arm,cortex-a15";
72 clock-frequency = <1800000000>;
73 cci-control-port = <&cci_control1>;
74 operating-points-v2 = <&cluster_a15_opp_table>;
75 cooling-min-level = <0>;
76 cooling-max-level = <11>;
77 #cooling-cells = <2>; /* min followed by max */
78 capacity-dmips-mhz = <1024>;
83 compatible = "arm,cortex-a7";
85 clocks = <&clock CLK_KFC_CLK>;
86 clock-frequency = <1000000000>;
87 cci-control-port = <&cci_control0>;
88 operating-points-v2 = <&cluster_a7_opp_table>;
89 cooling-min-level = <0>;
90 cooling-max-level = <7>;
91 #cooling-cells = <2>; /* min followed by max */
92 capacity-dmips-mhz = <539>;
97 compatible = "arm,cortex-a7";
99 clock-frequency = <1000000000>;
100 cci-control-port = <&cci_control0>;
101 operating-points-v2 = <&cluster_a7_opp_table>;
102 cooling-min-level = <0>;
103 cooling-max-level = <7>;
104 #cooling-cells = <2>; /* min followed by max */
105 capacity-dmips-mhz = <539>;
110 compatible = "arm,cortex-a7";
112 clock-frequency = <1000000000>;
113 cci-control-port = <&cci_control0>;
114 operating-points-v2 = <&cluster_a7_opp_table>;
115 cooling-min-level = <0>;
116 cooling-max-level = <7>;
117 #cooling-cells = <2>; /* min followed by max */
118 capacity-dmips-mhz = <539>;
123 compatible = "arm,cortex-a7";
125 clock-frequency = <1000000000>;
126 cci-control-port = <&cci_control0>;
127 operating-points-v2 = <&cluster_a7_opp_table>;
128 cooling-min-level = <0>;
129 cooling-max-level = <7>;
130 #cooling-cells = <2>; /* min followed by max */
131 capacity-dmips-mhz = <539>;