1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5410 SoC device tree source
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung Exynos5410 SoC device nodes are listed in this file.
9 * Exynos5410 based board files can include this file and provide
10 * values for board specfic bindings.
13 #include "exynos54xx.dtsi"
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 compatible = "samsung,exynos5410", "samsung,exynos5";
20 interrupt-parent = <&gic>;
23 pinctrl0 = &pinctrl_0;
24 pinctrl1 = &pinctrl_1;
25 pinctrl2 = &pinctrl_2;
26 pinctrl3 = &pinctrl_3;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
42 compatible = "arm,cortex-a15";
44 clock-frequency = <1600000000>;
49 compatible = "arm,cortex-a15";
51 clock-frequency = <1600000000>;
56 compatible = "arm,cortex-a15";
58 clock-frequency = <1600000000>;
63 compatible = "simple-bus";
68 pmu_system_controller: system-controller@10040000 {
69 compatible = "samsung,exynos5410-pmu", "syscon";
70 reg = <0x10040000 0x5000>;
71 clock-names = "clkout16";
76 clock: clock-controller@10010000 {
77 compatible = "samsung,exynos5410-clock";
78 reg = <0x10010000 0x30000>;
82 clock_audss: audss-clock-controller@3810000 {
83 compatible = "samsung,exynos5410-audss-clock";
84 reg = <0x03810000 0x0C>;
86 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
87 clock-names = "pll_ref", "pll_in";
90 tmu_cpu0: tmu@10060000 {
91 compatible = "samsung,exynos5420-tmu";
92 reg = <0x10060000 0x100>;
93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&clock CLK_TMU>;
95 clock-names = "tmu_apbif";
96 #thermal-sensor-cells = <0>;
99 tmu_cpu1: tmu@10064000 {
100 compatible = "samsung,exynos5420-tmu";
101 reg = <0x10064000 0x100>;
102 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clock CLK_TMU>;
104 clock-names = "tmu_apbif";
105 #thermal-sensor-cells = <0>;
108 tmu_cpu2: tmu@10068000 {
109 compatible = "samsung,exynos5420-tmu";
110 reg = <0x10068000 0x100>;
111 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clock CLK_TMU>;
113 clock-names = "tmu_apbif";
114 #thermal-sensor-cells = <0>;
117 tmu_cpu3: tmu@1006c000 {
118 compatible = "samsung,exynos5420-tmu";
119 reg = <0x1006c000 0x100>;
120 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clock CLK_TMU>;
122 clock-names = "tmu_apbif";
123 #thermal-sensor-cells = <0>;
126 mmc_0: mmc@12200000 {
127 compatible = "samsung,exynos5250-dw-mshc";
128 reg = <0x12200000 0x1000>;
129 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
130 #address-cells = <1>;
132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
133 clock-names = "biu", "ciu";
138 mmc_1: mmc@12210000 {
139 compatible = "samsung,exynos5250-dw-mshc";
140 reg = <0x12210000 0x1000>;
141 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
144 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
145 clock-names = "biu", "ciu";
150 mmc_2: mmc@12220000 {
151 compatible = "samsung,exynos5250-dw-mshc";
152 reg = <0x12220000 0x1000>;
153 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
154 #address-cells = <1>;
156 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
157 clock-names = "biu", "ciu";
162 pinctrl_0: pinctrl@13400000 {
163 compatible = "samsung,exynos5410-pinctrl";
164 reg = <0x13400000 0x1000>;
165 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
167 wakeup-interrupt-controller {
168 compatible = "samsung,exynos4210-wakeup-eint";
169 interrupt-parent = <&gic>;
170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
174 pinctrl_1: pinctrl@14000000 {
175 compatible = "samsung,exynos5410-pinctrl";
176 reg = <0x14000000 0x1000>;
177 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
180 pinctrl_2: pinctrl@10d10000 {
181 compatible = "samsung,exynos5410-pinctrl";
182 reg = <0x10d10000 0x1000>;
183 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
186 pinctrl_3: pinctrl@3860000 {
187 compatible = "samsung,exynos5410-pinctrl";
188 reg = <0x03860000 0x1000>;
189 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
195 compatible = "simple-bus";
196 interrupt-parent = <&gic>;
199 pdma0: pdma@121a0000 {
200 compatible = "arm,pl330", "arm,primecell";
201 reg = <0x121a0000 0x1000>;
202 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&clock CLK_PDMA0>;
204 clock-names = "apb_pclk";
207 #dma-requests = <32>;
210 pdma1: pdma@121b0000 {
211 compatible = "arm,pl330", "arm,primecell";
212 reg = <0x121b0000 0x1000>;
213 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&clock CLK_PDMA1>;
215 clock-names = "apb_pclk";
218 #dma-requests = <32>;
222 audi2s0: i2s@3830000 {
223 compatible = "samsung,exynos5420-i2s";
224 reg = <0x03830000 0x100>;
228 dma-names = "tx", "rx", "tx-sec";
229 clocks = <&clock_audss EXYNOS_I2S_BUS>,
230 <&clock_audss EXYNOS_I2S_BUS>,
231 <&clock_audss EXYNOS_SCLK_I2S>;
232 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
234 clock-output-names = "i2s_cdclk0";
235 #sound-dai-cells = <1>;
236 samsung,idma-addr = <0x03000000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&audi2s0_bus>;
244 cpu0_thermal: cpu0-thermal {
245 thermal-sensors = <&tmu_cpu0>;
246 #include "exynos5420-trip-points.dtsi"
248 cpu1_thermal: cpu1-thermal {
249 thermal-sensors = <&tmu_cpu1>;
250 #include "exynos5420-trip-points.dtsi"
252 cpu2_thermal: cpu2-thermal {
253 thermal-sensors = <&tmu_cpu2>;
254 #include "exynos5420-trip-points.dtsi"
256 cpu3_thermal: cpu3-thermal {
257 thermal-sensors = <&tmu_cpu3>;
258 #include "exynos5420-trip-points.dtsi"
264 clocks = <&clock CLK_TSADC>;
266 samsung,syscon-phandle = <&pmu_system_controller>;
270 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
275 clocks = <&clock CLK_I2C0>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c0_bus>;
282 clocks = <&clock CLK_I2C1>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&i2c1_bus>;
289 clocks = <&clock CLK_I2C2>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&i2c2_bus>;
296 clocks = <&clock CLK_I2C3>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&i2c3_bus>;
303 clocks = <&clock CLK_USI0>;
304 clock-names = "hsi2c";
305 pinctrl-names = "default";
306 pinctrl-0 = <&i2c4_hs_bus>;
310 clocks = <&clock CLK_USI1>;
311 clock-names = "hsi2c";
312 pinctrl-names = "default";
313 pinctrl-0 = <&i2c5_hs_bus>;
317 clocks = <&clock CLK_USI2>;
318 clock-names = "hsi2c";
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c6_hs_bus>;
324 clocks = <&clock CLK_USI3>;
325 clock-names = "hsi2c";
326 pinctrl-names = "default";
327 pinctrl-0 = <&i2c7_hs_bus>;
331 clocks = <&fin_pll>, <&clock CLK_MCT>;
332 clock-names = "fin_pll", "mct";
336 clocks = <&clock CLK_SSS>;
337 clock-names = "secss";
341 clocks = <&clock CLK_PWM>;
342 clock-names = "timers";
346 clocks = <&clock CLK_RTC>;
352 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
353 clock-names = "uart", "clk_uart_baud0";
354 dmas = <&pdma0 13>, <&pdma0 14>;
355 dma-names = "rx", "tx";
359 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
360 clock-names = "uart", "clk_uart_baud0";
361 dmas = <&pdma1 15>, <&pdma1 16>;
362 dma-names = "rx", "tx";
366 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
367 clock-names = "uart", "clk_uart_baud0";
368 dmas = <&pdma0 15>, <&pdma0 16>;
369 dma-names = "rx", "tx";
373 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
374 clock-names = "uart", "clk_uart_baud0";
375 dmas = <&pdma1 17>, <&pdma1 18>;
376 dma-names = "rx", "tx";
380 clocks = <&clock CLK_SSS>;
381 clock-names = "secss";
385 #address-cells = <2>;
387 ranges = <0 0 0x04000000 0x20000
388 1 0 0x05000000 0x20000
389 2 0 0x06000000 0x20000
390 3 0 0x07000000 0x20000>;
394 clocks = <&clock CLK_SSS>;
395 clock-names = "secss";
399 clocks = <&clock CLK_USBD300>;
400 clock-names = "usbdrd30";
404 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
405 clock-names = "phy", "ref";
406 samsung,pmu-syscon = <&pmu_system_controller>;
410 clocks = <&clock CLK_USBD301>;
411 clock-names = "usbdrd30";
415 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
420 clock-names = "phy", "ref";
421 samsung,pmu-syscon = <&pmu_system_controller>;
425 clocks = <&clock CLK_USBH20>;
426 clock-names = "usbhost";
430 clocks = <&clock CLK_USBH20>;
431 clock-names = "usbhost";
435 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
436 clock-names = "phy", "ref";
437 samsung,sysreg-phandle = <&sysreg_system_controller>;
438 samsung,pmureg-phandle = <&pmu_system_controller>;
442 clocks = <&clock CLK_WDT>;
443 clock-names = "watchdog";
444 samsung,syscon-phandle = <&pmu_system_controller>;
447 #include "exynos5410-pinctrl.dtsi"
448 #include "exynos-syscon-restart.dtsi"