arch/arm/boot/dts/exynos5410.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5410 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
   8  * EXYNOS5410 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "skeleton.dtsi"
  17 #include "exynos5.dtsi"
  18 #include "exynos-syscon-restart.dtsi"
  19 #include <dt-bindings/clock/exynos5410.h>
  20
  21 / {
  22         compatible = "samsung,exynos5410", "samsung,exynos5";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 pinctrl0 = &pinctrl_0;
  27                 pinctrl1 = &pinctrl_1;
  28                 pinctrl2 = &pinctrl_2;
  29                 pinctrl3 = &pinctrl_3;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x0>;
  40                         clock-frequency = <1600000000>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <0x1>;
  47                         clock-frequency = <1600000000>;
  48                 };
  49
  50                 cpu2: cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x2>;
  54                         clock-frequency = <1600000000>;
  55                 };
  56
  57                 cpu3: cpu@3 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <0x3>;
  61                         clock-frequency = <1600000000>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 pmu_system_controller: system-controller@10040000 {
  72                         compatible = "samsung,exynos5410-pmu", "syscon";
  73                         reg = <0x10040000 0x5000>;
  74                         clock-names = "clkout16";
  75                         clocks = <&fin_pll>;
  76                         #clock-cells = <1>;
  77                 };
  78
  79                 mct: mct@101C0000 {
  80                         compatible = "samsung,exynos4210-mct";
  81                         reg = <0x101C0000 0xB00>;
  82                         interrupt-parent = <&interrupt_map>;
  83                         interrupts = <0>, <1>, <2>, <3>,
  84                                 <4>, <5>, <6>, <7>,
  85                                 <8>, <9>, <10>, <11>;
  86                         clocks = <&fin_pll>, <&clock CLK_MCT>;
  87                         clock-names = "fin_pll", "mct";
  88
  89                         interrupt_map: interrupt-map {
  90                                 #interrupt-cells = <1>;
  91                                 #address-cells = <0>;
  92                                 #size-cells = <0>;
  93                                 interrupt-map = <0 &combiner 23 3>,
  94                                                 <1 &combiner 23 4>,
  95                                                 <2 &combiner 25 2>,
  96                                                 <3 &combiner 25 3>,
  97                                                 <4 &gic 0 120 0>,
  98                                                 <5 &gic 0 121 0>,
  99                                                 <6 &gic 0 122 0>,
 100                                                 <7 &gic 0 123 0>,
 101                                                 <8 &gic 0 128 0>,
 102                                                 <9 &gic 0 129 0>,
 103                                                 <10 &gic 0 130 0>,
 104                                                 <11 &gic 0 131 0>;
 105                         };
 106                 };
 107
 108                 sysram@02020000 {
 109                         compatible = "mmio-sram";
 110                         reg = <0x02020000 0x54000>;
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         ranges = <0 0x02020000 0x54000>;
 114
 115                         smp-sysram@0 {
 116                                 compatible = "samsung,exynos4210-sysram";
 117                                 reg = <0x0 0x1000>;
 118                         };
 119
 120                         smp-sysram@53000 {
 121                                 compatible = "samsung,exynos4210-sysram-ns";
 122                                 reg = <0x53000 0x1000>;
 123                         };
 124                 };
 125
 126                 clock: clock-controller@10010000 {
 127                         compatible = "samsung,exynos5410-clock";
 128                         reg = <0x10010000 0x30000>;
 129                         #clock-cells = <1>;
 130                 };
 131
 132                 mmc_0: mmc@12200000 {
 133                         compatible = "samsung,exynos5250-dw-mshc";
 134                         reg = <0x12200000 0x1000>;
 135                         interrupts = <0 75 0>;
 136                         #address-cells = <1>;
 137                         #size-cells = <0>;
 138                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 139                         clock-names = "biu", "ciu";
 140                         fifo-depth = <0x80>;
 141                         status = "disabled";
 142                 };
 143
 144                 mmc_1: mmc@12210000 {
 145                         compatible = "samsung,exynos5250-dw-mshc";
 146                         reg = <0x12210000 0x1000>;
 147                         interrupts = <0 76 0>;
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 151                         clock-names = "biu", "ciu";
 152                         fifo-depth = <0x80>;
 153                         status = "disabled";
 154                 };
 155
 156                 mmc_2: mmc@12220000 {
 157                         compatible = "samsung,exynos5250-dw-mshc";
 158                         reg = <0x12220000 0x1000>;
 159                         interrupts = <0 77 0>;
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 163                         clock-names = "biu", "ciu";
 164                         fifo-depth = <0x80>;
 165                         status = "disabled";
 166                 };
 167
 168                 pinctrl_0: pinctrl@13400000 {
 169                         compatible = "samsung,exynos5410-pinctrl";
 170                         reg = <0x13400000 0x1000>;
 171                         interrupts = <0 45 0>;
 172
 173                         wakeup-interrupt-controller {
 174                                 compatible = "samsung,exynos4210-wakeup-eint";
 175                                 interrupt-parent = <&gic>;
 176                                 interrupts = <0 32 0>;
 177                         };
 178                 };
 179
 180                 pinctrl_1: pinctrl@14000000 {
 181                         compatible = "samsung,exynos5410-pinctrl";
 182                         reg = <0x14000000 0x1000>;
 183                         interrupts = <0 46 0>;
 184                 };
 185
 186                 pinctrl_2: pinctrl@10d10000 {
 187                         compatible = "samsung,exynos5410-pinctrl";
 188                         reg = <0x10d10000 0x1000>;
 189                         interrupts = <0 50 0>;
 190                 };
 191
 192                 pinctrl_3: pinctrl@03860000 {
 193                         compatible = "samsung,exynos5410-pinctrl";
 194                         reg = <0x03860000 0x1000>;
 195                         interrupts = <0 47 0>;
 196                 };
 197         };
 198 };
 199
 200 &pwm {
 201         clocks = <&clock CLK_PWM>;
 202         clock-names = "timers";
 203 };
 204
 205 &serial_0 {
 206         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 207         clock-names = "uart", "clk_uart_baud0";
 208 };
 209
 210 &serial_1 {
 211         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 212         clock-names = "uart", "clk_uart_baud0";
 213 };
 214
 215 &serial_2 {
 216         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 217         clock-names = "uart", "clk_uart_baud0";
 218 };
 219
 220 &serial_3 {
 221         status = "disabled";
 222 };
 223
 224 &sromc {
 225         #address-cells = <2>;
 226         #size-cells = <1>;
 227         ranges = <0 0 0x04000000 0x20000
 228                   1 0 0x05000000 0x20000
 229                   2 0 0x06000000 0x20000
 230                   3 0 0x07000000 0x20000>;
 231 };
 232
 233 #include "exynos5410-pinctrl.dtsi"