1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5250 SoC device tree source
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
10 * values for board specfic bindings.
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
14 * additional nodes can be added to this file.
17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5250", "samsung,exynos5";
43 pinctrl0 = &pinctrl_0;
44 pinctrl1 = &pinctrl_1;
45 pinctrl2 = &pinctrl_2;
46 pinctrl3 = &pinctrl_3;
55 compatible = "arm,cortex-a15";
57 clocks = <&clock CLK_ARM_CLK>;
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
64 compatible = "arm,cortex-a15";
66 clocks = <&clock CLK_ARM_CLK>;
68 operating-points-v2 = <&cpu0_opp_table>;
69 #cooling-cells = <2>; /* min followed by max */
73 cpu0_opp_table: opp_table0 {
74 compatible = "operating-points-v2";
78 opp-hz = /bits/ 64 <200000000>;
79 opp-microvolt = <925000>;
80 clock-latency-ns = <140000>;
83 opp-hz = /bits/ 64 <300000000>;
84 opp-microvolt = <937500>;
85 clock-latency-ns = <140000>;
88 opp-hz = /bits/ 64 <400000000>;
89 opp-microvolt = <950000>;
90 clock-latency-ns = <140000>;
93 opp-hz = /bits/ 64 <500000000>;
94 opp-microvolt = <975000>;
95 clock-latency-ns = <140000>;
98 opp-hz = /bits/ 64 <600000000>;
99 opp-microvolt = <1000000>;
100 clock-latency-ns = <140000>;
103 opp-hz = /bits/ 64 <700000000>;
104 opp-microvolt = <1012500>;
105 clock-latency-ns = <140000>;
108 opp-hz = /bits/ 64 <800000000>;
109 opp-microvolt = <1025000>;
110 clock-latency-ns = <140000>;
113 opp-hz = /bits/ 64 <900000000>;
114 opp-microvolt = <1050000>;
115 clock-latency-ns = <140000>;
118 opp-hz = /bits/ 64 <1000000000>;
119 opp-microvolt = <1075000>;
120 clock-latency-ns = <140000>;
124 opp-hz = /bits/ 64 <1100000000>;
125 opp-microvolt = <1100000>;
126 clock-latency-ns = <140000>;
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt = <1125000>;
131 clock-latency-ns = <140000>;
134 opp-hz = /bits/ 64 <1300000000>;
135 opp-microvolt = <1150000>;
136 clock-latency-ns = <140000>;
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt = <1200000>;
141 clock-latency-ns = <140000>;
144 opp-hz = /bits/ 64 <1500000000>;
145 opp-microvolt = <1225000>;
146 clock-latency-ns = <140000>;
149 opp-hz = /bits/ 64 <1600000000>;
150 opp-microvolt = <1250000>;
151 clock-latency-ns = <140000>;
154 opp-hz = /bits/ 64 <1700000000>;
155 opp-microvolt = <1300000>;
156 clock-latency-ns = <140000>;
161 compatible = "arm,cortex-a15-pmu";
162 interrupt-parent = <&combiner>;
163 interrupts = <1 2>, <22 4>;
168 compatible = "mmio-sram";
169 reg = <0x02020000 0x30000>;
170 #address-cells = <1>;
172 ranges = <0 0x02020000 0x30000>;
175 compatible = "samsung,exynos4210-sysram";
180 compatible = "samsung,exynos4210-sysram-ns";
181 reg = <0x2f000 0x1000>;
185 pd_gsc: power-domain@10044000 {
186 compatible = "samsung,exynos4210-pd";
187 reg = <0x10044000 0x20>;
188 #power-domain-cells = <0>;
192 pd_mfc: power-domain@10044040 {
193 compatible = "samsung,exynos4210-pd";
194 reg = <0x10044040 0x20>;
195 #power-domain-cells = <0>;
199 pd_g3d: power-domain@10044060 {
200 compatible = "samsung,exynos4210-pd";
201 reg = <0x10044060 0x20>;
202 #power-domain-cells = <0>;
206 pd_disp1: power-domain@100440a0 {
207 compatible = "samsung,exynos4210-pd";
208 reg = <0x100440A0 0x20>;
209 #power-domain-cells = <0>;
213 pd_mau: power-domain@100440c0 {
214 compatible = "samsung,exynos4210-pd";
215 reg = <0x100440C0 0x20>;
216 #power-domain-cells = <0>;
220 clock: clock-controller@10010000 {
221 compatible = "samsung,exynos5250-clock";
222 reg = <0x10010000 0x30000>;
226 clock_audss: audss-clock-controller@3810000 {
227 compatible = "samsung,exynos5250-audss-clock";
228 reg = <0x03810000 0x0C>;
230 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
231 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
232 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
233 power-domains = <&pd_mau>;
237 compatible = "samsung,exynos4210-mct";
238 reg = <0x101C0000 0x800>;
239 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
240 clock-names = "fin_pll", "mct";
241 interrupts-extended = <&combiner 23 3>,
245 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
246 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
249 pinctrl_0: pinctrl@11400000 {
250 compatible = "samsung,exynos5250-pinctrl";
251 reg = <0x11400000 0x1000>;
252 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
254 wakup_eint: wakeup-interrupt-controller {
255 compatible = "samsung,exynos4210-wakeup-eint";
256 interrupt-parent = <&gic>;
257 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
261 pinctrl_1: pinctrl@13400000 {
262 compatible = "samsung,exynos5250-pinctrl";
263 reg = <0x13400000 0x1000>;
264 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
267 pinctrl_2: pinctrl@10d10000 {
268 compatible = "samsung,exynos5250-pinctrl";
269 reg = <0x10d10000 0x1000>;
270 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
273 pinctrl_3: pinctrl@3860000 {
274 compatible = "samsung,exynos5250-pinctrl";
275 reg = <0x03860000 0x1000>;
276 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
277 power-domains = <&pd_mau>;
280 pmu_system_controller: system-controller@10040000 {
281 compatible = "samsung,exynos5250-pmu", "syscon";
282 reg = <0x10040000 0x5000>;
283 clock-names = "clkout16";
284 clocks = <&clock CLK_FIN_PLL>;
286 interrupt-controller;
287 #interrupt-cells = <3>;
288 interrupt-parent = <&gic>;
292 compatible = "samsung,exynos5250-wdt";
293 reg = <0x101D0000 0x100>;
294 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clock CLK_WDT>;
296 clock-names = "watchdog";
297 samsung,syscon-phandle = <&pmu_system_controller>;
300 mfc: codec@11000000 {
301 compatible = "samsung,mfc-v6";
302 reg = <0x11000000 0x10000>;
303 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
304 power-domains = <&pd_mfc>;
305 clocks = <&clock CLK_MFC>;
307 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
308 iommu-names = "left", "right";
311 rotator: rotator@11c00000 {
312 compatible = "samsung,exynos5250-rotator";
313 reg = <0x11C00000 0x64>;
314 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clock CLK_ROTATOR>;
316 clock-names = "rotator";
317 iommus = <&sysmmu_rotator>;
321 compatible = "samsung,exynos5250-mali", "arm,mali-t604";
322 reg = <0x11800000 0x5000>;
323 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
326 interrupt-names = "job", "mmu", "gpu";
327 clocks = <&clock CLK_G3D>;
328 clock-names = "core";
329 operating-points-v2 = <&gpu_opp_table>;
330 power-domains = <&pd_g3d>;
333 gpu_opp_table: gpu-opp-table {
334 compatible = "operating-points-v2";
337 opp-hz = /bits/ 64 <100000000>;
338 opp-microvolt = <925000>;
341 opp-hz = /bits/ 64 <160000000>;
342 opp-microvolt = <925000>;
345 opp-hz = /bits/ 64 <266000000>;
346 opp-microvolt = <1025000>;
349 opp-hz = /bits/ 64 <350000000>;
350 opp-microvolt = <1075000>;
353 opp-hz = /bits/ 64 <400000000>;
354 opp-microvolt = <1125000>;
357 opp-hz = /bits/ 64 <450000000>;
358 opp-microvolt = <1150000>;
361 opp-hz = /bits/ 64 <533000000>;
362 opp-microvolt = <1250000>;
368 compatible = "samsung,exynos5250-tmu";
369 reg = <0x10060000 0x100>;
370 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clock CLK_TMU>;
372 clock-names = "tmu_apbif";
373 #thermal-sensor-cells = <0>;
376 sata: sata@122f0000 {
377 compatible = "snps,dwc-ahci";
378 samsung,sata-freq = <66>;
379 reg = <0x122F0000 0x1ff>;
380 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
382 clock-names = "sata", "sclk_sata";
384 phy-names = "sata-phy";
385 ports-implemented = <0x1>;
389 sata_phy: sata-phy@12170000 {
390 compatible = "samsung,exynos5250-sata-phy";
391 reg = <0x12170000 0x1ff>;
392 clocks = <&clock CLK_SATA_PHYCTRL>;
393 clock-names = "sata_phyctrl";
395 samsung,syscon-phandle = <&pmu_system_controller>;
399 /* i2c_0-3 are defined in exynos5.dtsi */
400 i2c_4: i2c@12ca0000 {
401 compatible = "samsung,s3c2440-i2c";
402 reg = <0x12CA0000 0x100>;
403 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 clocks = <&clock CLK_I2C4>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c4_bus>;
413 i2c_5: i2c@12cb0000 {
414 compatible = "samsung,s3c2440-i2c";
415 reg = <0x12CB0000 0x100>;
416 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
419 clocks = <&clock CLK_I2C5>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c5_bus>;
426 i2c_6: i2c@12cc0000 {
427 compatible = "samsung,s3c2440-i2c";
428 reg = <0x12CC0000 0x100>;
429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
432 clocks = <&clock CLK_I2C6>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c6_bus>;
439 i2c_7: i2c@12cd0000 {
440 compatible = "samsung,s3c2440-i2c";
441 reg = <0x12CD0000 0x100>;
442 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
445 clocks = <&clock CLK_I2C7>;
447 pinctrl-names = "default";
448 pinctrl-0 = <&i2c7_bus>;
452 i2c_8: i2c@12ce0000 {
453 compatible = "samsung,s3c2440-hdmiphy-i2c";
454 reg = <0x12CE0000 0x1000>;
455 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
458 clocks = <&clock CLK_I2C_HDMI>;
462 hdmiphy: hdmiphy@38 {
463 compatible = "samsung,exynos4212-hdmiphy";
468 i2c_9: i2c@121d0000 {
469 compatible = "samsung,exynos5-sata-phy-i2c";
470 reg = <0x121D0000 0x100>;
471 #address-cells = <1>;
473 clocks = <&clock CLK_SATA_PHYI2C>;
478 spi_0: spi@12d20000 {
479 compatible = "samsung,exynos4210-spi";
481 reg = <0x12d20000 0x100>;
482 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
485 dma-names = "tx", "rx";
486 #address-cells = <1>;
488 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
489 clock-names = "spi", "spi_busclk0";
490 pinctrl-names = "default";
491 pinctrl-0 = <&spi0_bus>;
494 spi_1: spi@12d30000 {
495 compatible = "samsung,exynos4210-spi";
497 reg = <0x12d30000 0x100>;
498 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
501 dma-names = "tx", "rx";
502 #address-cells = <1>;
504 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
505 clock-names = "spi", "spi_busclk0";
506 pinctrl-names = "default";
507 pinctrl-0 = <&spi1_bus>;
510 spi_2: spi@12d40000 {
511 compatible = "samsung,exynos4210-spi";
513 reg = <0x12d40000 0x100>;
514 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
517 dma-names = "tx", "rx";
518 #address-cells = <1>;
520 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
521 clock-names = "spi", "spi_busclk0";
522 pinctrl-names = "default";
523 pinctrl-0 = <&spi2_bus>;
526 mmc_0: mmc@12200000 {
527 compatible = "samsung,exynos5250-dw-mshc";
528 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
531 reg = <0x12200000 0x1000>;
532 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
533 clock-names = "biu", "ciu";
538 mmc_1: mmc@12210000 {
539 compatible = "samsung,exynos5250-dw-mshc";
540 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
541 #address-cells = <1>;
543 reg = <0x12210000 0x1000>;
544 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
545 clock-names = "biu", "ciu";
550 mmc_2: mmc@12220000 {
551 compatible = "samsung,exynos5250-dw-mshc";
552 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
555 reg = <0x12220000 0x1000>;
556 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
557 clock-names = "biu", "ciu";
562 mmc_3: mmc@12230000 {
563 compatible = "samsung,exynos5250-dw-mshc";
564 reg = <0x12230000 0x1000>;
565 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
568 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
569 clock-names = "biu", "ciu";
575 compatible = "samsung,s5pv210-i2s";
577 reg = <0x03830000 0x100>;
581 dma-names = "tx", "rx", "tx-sec";
582 clocks = <&clock_audss EXYNOS_I2S_BUS>,
583 <&clock_audss EXYNOS_I2S_BUS>,
584 <&clock_audss EXYNOS_SCLK_I2S>;
585 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
586 samsung,idma-addr = <0x03000000>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&i2s0_bus>;
589 power-domains = <&pd_mau>;
591 #sound-dai-cells = <1>;
595 compatible = "samsung,s3c6410-i2s";
597 reg = <0x12D60000 0x100>;
600 dma-names = "tx", "rx";
601 clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
602 clock-names = "iis", "i2s_opclk0";
603 pinctrl-names = "default";
604 pinctrl-0 = <&i2s1_bus>;
605 power-domains = <&pd_mau>;
606 #sound-dai-cells = <1>;
610 compatible = "samsung,s3c6410-i2s";
612 reg = <0x12D70000 0x100>;
615 dma-names = "tx", "rx";
616 clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
617 clock-names = "iis", "i2s_opclk0";
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2s2_bus>;
620 power-domains = <&pd_mau>;
621 #sound-dai-cells = <1>;
625 compatible = "samsung,exynos5250-dwusb3";
626 clocks = <&clock CLK_USB3>;
627 clock-names = "usbdrd30";
628 #address-cells = <1>;
632 usbdrd_dwc3: dwc3@12000000 {
633 compatible = "synopsys,dwc3";
634 reg = <0x12000000 0x10000>;
635 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
636 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
637 phy-names = "usb2-phy", "usb3-phy";
641 usbdrd_phy: phy@12100000 {
642 compatible = "samsung,exynos5250-usbdrd-phy";
643 reg = <0x12100000 0x100>;
644 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
645 clock-names = "phy", "ref";
646 samsung,pmu-syscon = <&pmu_system_controller>;
651 compatible = "samsung,exynos4210-ehci";
652 reg = <0x12110000 0x100>;
653 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&clock CLK_USB2>;
656 clock-names = "usbhost";
657 phys = <&usb2_phy_gen 1>;
662 compatible = "samsung,exynos4210-ohci";
663 reg = <0x12120000 0x100>;
664 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clock CLK_USB2>;
667 clock-names = "usbhost";
668 phys = <&usb2_phy_gen 1>;
672 usb2_phy_gen: phy@12130000 {
673 compatible = "samsung,exynos5250-usb2-phy";
674 reg = <0x12130000 0x100>;
675 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
676 clock-names = "phy", "ref";
678 samsung,sysreg-phandle = <&sysreg_system_controller>;
679 samsung,pmureg-phandle = <&pmu_system_controller>;
683 #address-cells = <1>;
685 compatible = "simple-bus";
686 interrupt-parent = <&gic>;
689 pdma0: pdma@121a0000 {
690 compatible = "arm,pl330", "arm,primecell";
691 reg = <0x121A0000 0x1000>;
692 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clock CLK_PDMA0>;
694 clock-names = "apb_pclk";
697 #dma-requests = <32>;
700 pdma1: pdma@121b0000 {
701 compatible = "arm,pl330", "arm,primecell";
702 reg = <0x121B0000 0x1000>;
703 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clock CLK_PDMA1>;
705 clock-names = "apb_pclk";
708 #dma-requests = <32>;
711 mdma0: mdma@10800000 {
712 compatible = "arm,pl330", "arm,primecell";
713 reg = <0x10800000 0x1000>;
714 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clock CLK_MDMA0>;
716 clock-names = "apb_pclk";
722 mdma1: mdma@11c10000 {
723 compatible = "arm,pl330", "arm,primecell";
724 reg = <0x11C10000 0x1000>;
725 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clock CLK_MDMA1>;
727 clock-names = "apb_pclk";
734 gsc_0: gsc@13e00000 {
735 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
736 reg = <0x13e00000 0x1000>;
737 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
738 power-domains = <&pd_gsc>;
739 clocks = <&clock CLK_GSCL0>;
740 clock-names = "gscl";
741 iommus = <&sysmmu_gsc0>;
744 gsc_1: gsc@13e10000 {
745 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
746 reg = <0x13e10000 0x1000>;
747 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
748 power-domains = <&pd_gsc>;
749 clocks = <&clock CLK_GSCL1>;
750 clock-names = "gscl";
751 iommus = <&sysmmu_gsc1>;
754 gsc_2: gsc@13e20000 {
755 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
756 reg = <0x13e20000 0x1000>;
757 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
758 power-domains = <&pd_gsc>;
759 clocks = <&clock CLK_GSCL2>;
760 clock-names = "gscl";
761 iommus = <&sysmmu_gsc2>;
764 gsc_3: gsc@13e30000 {
765 compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
766 reg = <0x13e30000 0x1000>;
767 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
768 power-domains = <&pd_gsc>;
769 clocks = <&clock CLK_GSCL3>;
770 clock-names = "gscl";
771 iommus = <&sysmmu_gsc3>;
774 hdmi: hdmi@14530000 {
775 compatible = "samsung,exynos4212-hdmi";
776 reg = <0x14530000 0x70000>;
777 power-domains = <&pd_disp1>;
778 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
780 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
781 <&clock CLK_MOUT_HDMI>;
782 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
783 "sclk_hdmiphy", "mout_hdmi";
784 samsung,syscon-phandle = <&pmu_system_controller>;
786 #sound-dai-cells = <0>;
790 hdmicec: cec@101b0000 {
791 compatible = "samsung,s5p-cec";
792 reg = <0x101B0000 0x200>;
793 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
794 clocks = <&clock CLK_HDMI_CEC>;
795 clock-names = "hdmicec";
796 samsung,syscon-phandle = <&pmu_system_controller>;
797 hdmi-phandle = <&hdmi>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&hdmi_cec>;
803 mixer: mixer@14450000 {
804 compatible = "samsung,exynos5250-mixer";
805 reg = <0x14450000 0x10000>;
806 power-domains = <&pd_disp1>;
807 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
809 <&clock CLK_SCLK_HDMI>;
810 clock-names = "mixer", "hdmi", "sclk_hdmi";
811 iommus = <&sysmmu_tv>;
816 compatible = "samsung,exynos5250-dp-video-phy";
817 samsung,pmu-syscon = <&pmu_system_controller>;
821 mipi_phy: video-phy@10040710 {
822 compatible = "samsung,s5pv210-mipi-video-phy";
823 reg = <0x10040710 0x100>;
825 syscon = <&pmu_system_controller>;
828 dsi_0: dsi@14500000 {
829 compatible = "samsung,exynos4210-mipi-dsi";
830 reg = <0x14500000 0x10000>;
831 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
832 samsung,power-domain = <&pd_disp1>;
833 phys = <&mipi_phy 3>;
835 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
836 clock-names = "bus_clk", "sclk_mipi";
838 #address-cells = <1>;
843 compatible = "samsung,exynos-adc-v1";
844 reg = <0x12D10000 0x100>;
845 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clock CLK_ADC>;
848 #io-channel-cells = <1>;
850 samsung,syscon-phandle = <&pmu_system_controller>;
854 sysmmu_g2d: sysmmu@10a60000 {
855 compatible = "samsung,exynos-sysmmu";
856 reg = <0x10A60000 0x1000>;
857 interrupt-parent = <&combiner>;
859 clock-names = "sysmmu", "master";
860 clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
864 sysmmu_mfc_r: sysmmu@11200000 {
865 compatible = "samsung,exynos-sysmmu";
866 reg = <0x11200000 0x1000>;
867 interrupt-parent = <&combiner>;
869 power-domains = <&pd_mfc>;
870 clock-names = "sysmmu", "master";
871 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
875 sysmmu_mfc_l: sysmmu@11210000 {
876 compatible = "samsung,exynos-sysmmu";
877 reg = <0x11210000 0x1000>;
878 interrupt-parent = <&combiner>;
880 power-domains = <&pd_mfc>;
881 clock-names = "sysmmu", "master";
882 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
886 sysmmu_rotator: sysmmu@11d40000 {
887 compatible = "samsung,exynos-sysmmu";
888 reg = <0x11D40000 0x1000>;
889 interrupt-parent = <&combiner>;
891 clock-names = "sysmmu", "master";
892 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
896 sysmmu_jpeg: sysmmu@11f20000 {
897 compatible = "samsung,exynos-sysmmu";
898 reg = <0x11F20000 0x1000>;
899 interrupt-parent = <&combiner>;
901 power-domains = <&pd_gsc>;
902 clock-names = "sysmmu", "master";
903 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
907 sysmmu_fimc_isp: sysmmu@13260000 {
908 compatible = "samsung,exynos-sysmmu";
909 reg = <0x13260000 0x1000>;
910 interrupt-parent = <&combiner>;
912 clock-names = "sysmmu";
913 clocks = <&clock CLK_SMMU_FIMC_ISP>;
917 sysmmu_fimc_drc: sysmmu@13270000 {
918 compatible = "samsung,exynos-sysmmu";
919 reg = <0x13270000 0x1000>;
920 interrupt-parent = <&combiner>;
922 clock-names = "sysmmu";
923 clocks = <&clock CLK_SMMU_FIMC_DRC>;
927 sysmmu_fimc_fd: sysmmu@132a0000 {
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x132A0000 0x1000>;
930 interrupt-parent = <&combiner>;
932 clock-names = "sysmmu";
933 clocks = <&clock CLK_SMMU_FIMC_FD>;
937 sysmmu_fimc_scc: sysmmu@13280000 {
938 compatible = "samsung,exynos-sysmmu";
939 reg = <0x13280000 0x1000>;
940 interrupt-parent = <&combiner>;
942 clock-names = "sysmmu";
943 clocks = <&clock CLK_SMMU_FIMC_SCC>;
947 sysmmu_fimc_scp: sysmmu@13290000 {
948 compatible = "samsung,exynos-sysmmu";
949 reg = <0x13290000 0x1000>;
950 interrupt-parent = <&combiner>;
952 clock-names = "sysmmu";
953 clocks = <&clock CLK_SMMU_FIMC_SCP>;
957 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
958 compatible = "samsung,exynos-sysmmu";
959 reg = <0x132B0000 0x1000>;
960 interrupt-parent = <&combiner>;
962 clock-names = "sysmmu";
963 clocks = <&clock CLK_SMMU_FIMC_MCU>;
967 sysmmu_fimc_odc: sysmmu@132c0000 {
968 compatible = "samsung,exynos-sysmmu";
969 reg = <0x132C0000 0x1000>;
970 interrupt-parent = <&combiner>;
972 clock-names = "sysmmu";
973 clocks = <&clock CLK_SMMU_FIMC_ODC>;
977 sysmmu_fimc_dis0: sysmmu@132d0000 {
978 compatible = "samsung,exynos-sysmmu";
979 reg = <0x132D0000 0x1000>;
980 interrupt-parent = <&combiner>;
982 clock-names = "sysmmu";
983 clocks = <&clock CLK_SMMU_FIMC_DIS0>;
987 sysmmu_fimc_dis1: sysmmu@132e0000 {
988 compatible = "samsung,exynos-sysmmu";
989 reg = <0x132E0000 0x1000>;
990 interrupt-parent = <&combiner>;
992 clock-names = "sysmmu";
993 clocks = <&clock CLK_SMMU_FIMC_DIS1>;
997 sysmmu_fimc_3dnr: sysmmu@132f0000 {
998 compatible = "samsung,exynos-sysmmu";
999 reg = <0x132F0000 0x1000>;
1000 interrupt-parent = <&combiner>;
1002 clock-names = "sysmmu";
1003 clocks = <&clock CLK_SMMU_FIMC_3DNR>;
1007 sysmmu_fimc_lite0: sysmmu@13c40000 {
1008 compatible = "samsung,exynos-sysmmu";
1009 reg = <0x13C40000 0x1000>;
1010 interrupt-parent = <&combiner>;
1012 power-domains = <&pd_gsc>;
1013 clock-names = "sysmmu", "master";
1014 clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1018 sysmmu_fimc_lite1: sysmmu@13c50000 {
1019 compatible = "samsung,exynos-sysmmu";
1020 reg = <0x13C50000 0x1000>;
1021 interrupt-parent = <&combiner>;
1022 interrupts = <24 1>;
1023 power-domains = <&pd_gsc>;
1024 clock-names = "sysmmu", "master";
1025 clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1029 sysmmu_gsc0: sysmmu@13e80000 {
1030 compatible = "samsung,exynos-sysmmu";
1031 reg = <0x13E80000 0x1000>;
1032 interrupt-parent = <&combiner>;
1034 power-domains = <&pd_gsc>;
1035 clock-names = "sysmmu", "master";
1036 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1040 sysmmu_gsc1: sysmmu@13e90000 {
1041 compatible = "samsung,exynos-sysmmu";
1042 reg = <0x13E90000 0x1000>;
1043 interrupt-parent = <&combiner>;
1045 power-domains = <&pd_gsc>;
1046 clock-names = "sysmmu", "master";
1047 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1051 sysmmu_gsc2: sysmmu@13ea0000 {
1052 compatible = "samsung,exynos-sysmmu";
1053 reg = <0x13EA0000 0x1000>;
1054 interrupt-parent = <&combiner>;
1056 power-domains = <&pd_gsc>;
1057 clock-names = "sysmmu", "master";
1058 clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1062 sysmmu_gsc3: sysmmu@13eb0000 {
1063 compatible = "samsung,exynos-sysmmu";
1064 reg = <0x13EB0000 0x1000>;
1065 interrupt-parent = <&combiner>;
1067 power-domains = <&pd_gsc>;
1068 clock-names = "sysmmu", "master";
1069 clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1073 sysmmu_fimd1: sysmmu@14640000 {
1074 compatible = "samsung,exynos-sysmmu";
1075 reg = <0x14640000 0x1000>;
1076 interrupt-parent = <&combiner>;
1078 power-domains = <&pd_disp1>;
1079 clock-names = "sysmmu", "master";
1080 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1084 sysmmu_tv: sysmmu@14650000 {
1085 compatible = "samsung,exynos-sysmmu";
1086 reg = <0x14650000 0x1000>;
1087 interrupt-parent = <&combiner>;
1089 power-domains = <&pd_disp1>;
1090 clock-names = "sysmmu", "master";
1091 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1097 cpu_thermal: cpu-thermal {
1098 polling-delay-passive = <0>;
1099 polling-delay = <0>;
1100 thermal-sensors = <&tmu 0>;
1104 /* Corresponds to 800MHz at freq_table */
1105 cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1108 /* Corresponds to 200MHz at freq_table */
1109 cooling-device = <&cpu0 15 15>,
1117 compatible = "arm,armv7-timer";
1118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1123 * Unfortunately we need this since some versions
1124 * of U-Boot on Exynos don't set the CNTFRQ register,
1125 * so we need the value from DT.
1127 clock-frequency = <24000000>;
1132 power-domains = <&pd_disp1>;
1133 clocks = <&clock CLK_DP>;
1140 power-domains = <&pd_disp1>;
1141 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1142 clock-names = "sclk_fimd", "fimd";
1143 iommus = <&sysmmu_fimd1>;
1147 iommus = <&sysmmu_g2d>;
1148 clocks = <&clock CLK_G2D>;
1149 clock-names = "fimg2d";
1154 clocks = <&clock CLK_I2C0>;
1155 clock-names = "i2c";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&i2c0_bus>;
1161 clocks = <&clock CLK_I2C1>;
1162 clock-names = "i2c";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&i2c1_bus>;
1168 clocks = <&clock CLK_I2C2>;
1169 clock-names = "i2c";
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&i2c2_bus>;
1175 clocks = <&clock CLK_I2C3>;
1176 clock-names = "i2c";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&i2c3_bus>;
1182 clocks = <&clock CLK_SSS>;
1183 clock-names = "secss";
1187 clocks = <&clock CLK_PWM>;
1188 clock-names = "timers";
1192 clocks = <&clock CLK_RTC>;
1193 clock-names = "rtc";
1194 interrupt-parent = <&pmu_system_controller>;
1195 status = "disabled";
1199 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1200 clock-names = "uart", "clk_uart_baud0";
1201 dmas = <&pdma0 13>, <&pdma0 14>;
1202 dma-names = "rx", "tx";
1206 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1207 clock-names = "uart", "clk_uart_baud0";
1208 dmas = <&pdma1 15>, <&pdma1 16>;
1209 dma-names = "rx", "tx";
1213 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1214 clock-names = "uart", "clk_uart_baud0";
1215 dmas = <&pdma0 15>, <&pdma0 16>;
1216 dma-names = "rx", "tx";
1220 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1221 clock-names = "uart", "clk_uart_baud0";
1222 dmas = <&pdma1 17>, <&pdma1 18>;
1223 dma-names = "rx", "tx";
1227 clocks = <&clock CLK_SSS>;
1228 clock-names = "secss";
1232 clocks = <&clock CLK_SSS>;
1233 clock-names = "secss";
1236 #include "exynos5250-pinctrl.dtsi"
1237 #include "exynos-syscon-restart.dtsi"