Merge tag 'iio-fixes-for-5.6a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / exynos5250.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Samsung Exynos5250 SoC device tree source
4  *
5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6  *              http://www.samsung.com
7  *
8  * Samsung Exynos5250 SoC device nodes are listed in this file.
9  * Exynos5250 based board files can include this file and provide
10  * values for board specfic bindings.
11  *
12  * Note: This file does not include device nodes for all the controllers in
13  * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
14  * additional nodes can be added to this file.
15  */
16
17 #include <dt-bindings/clock/exynos5250.h>
18 #include "exynos5.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21
22 / {
23         compatible = "samsung,exynos5250", "samsung,exynos5";
24
25         aliases {
26                 spi0 = &spi_0;
27                 spi1 = &spi_1;
28                 spi2 = &spi_2;
29                 gsc0 = &gsc_0;
30                 gsc1 = &gsc_1;
31                 gsc2 = &gsc_2;
32                 gsc3 = &gsc_3;
33                 mshc0 = &mmc_0;
34                 mshc1 = &mmc_1;
35                 mshc2 = &mmc_2;
36                 mshc3 = &mmc_3;
37                 i2c4 = &i2c_4;
38                 i2c5 = &i2c_5;
39                 i2c6 = &i2c_6;
40                 i2c7 = &i2c_7;
41                 i2c8 = &i2c_8;
42                 i2c9 = &i2c_9;
43                 pinctrl0 = &pinctrl_0;
44                 pinctrl1 = &pinctrl_1;
45                 pinctrl2 = &pinctrl_2;
46                 pinctrl3 = &pinctrl_3;
47         };
48
49         cpus {
50                 #address-cells = <1>;
51                 #size-cells = <0>;
52
53                 cpu0: cpu@0 {
54                         device_type = "cpu";
55                         compatible = "arm,cortex-a15";
56                         reg = <0>;
57                         clocks = <&clock CLK_ARM_CLK>;
58                         clock-names = "cpu";
59                         operating-points-v2 = <&cpu0_opp_table>;
60                         #cooling-cells = <2>; /* min followed by max */
61                 };
62                 cpu1: cpu@1 {
63                         device_type = "cpu";
64                         compatible = "arm,cortex-a15";
65                         reg = <1>;
66                         clocks = <&clock CLK_ARM_CLK>;
67                         clock-names = "cpu";
68                         operating-points-v2 = <&cpu0_opp_table>;
69                         #cooling-cells = <2>; /* min followed by max */
70                 };
71         };
72
73         cpu0_opp_table: opp_table0 {
74                 compatible = "operating-points-v2";
75                 opp-shared;
76
77                 opp-200000000 {
78                         opp-hz = /bits/ 64 <200000000>;
79                         opp-microvolt = <925000>;
80                         clock-latency-ns = <140000>;
81                 };
82                 opp-300000000 {
83                         opp-hz = /bits/ 64 <300000000>;
84                         opp-microvolt = <937500>;
85                         clock-latency-ns = <140000>;
86                 };
87                 opp-400000000 {
88                         opp-hz = /bits/ 64 <400000000>;
89                         opp-microvolt = <950000>;
90                         clock-latency-ns = <140000>;
91                 };
92                 opp-500000000 {
93                         opp-hz = /bits/ 64 <500000000>;
94                         opp-microvolt = <975000>;
95                         clock-latency-ns = <140000>;
96                 };
97                 opp-600000000 {
98                         opp-hz = /bits/ 64 <600000000>;
99                         opp-microvolt = <1000000>;
100                         clock-latency-ns = <140000>;
101                 };
102                 opp-700000000 {
103                         opp-hz = /bits/ 64 <700000000>;
104                         opp-microvolt = <1012500>;
105                         clock-latency-ns = <140000>;
106                 };
107                 opp-800000000 {
108                         opp-hz = /bits/ 64 <800000000>;
109                         opp-microvolt = <1025000>;
110                         clock-latency-ns = <140000>;
111                 };
112                 opp-900000000 {
113                         opp-hz = /bits/ 64 <900000000>;
114                         opp-microvolt = <1050000>;
115                         clock-latency-ns = <140000>;
116                 };
117                 opp-1000000000 {
118                         opp-hz = /bits/ 64 <1000000000>;
119                         opp-microvolt = <1075000>;
120                         clock-latency-ns = <140000>;
121                         opp-suspend;
122                 };
123                 opp-1100000000 {
124                         opp-hz = /bits/ 64 <1100000000>;
125                         opp-microvolt = <1100000>;
126                         clock-latency-ns = <140000>;
127                 };
128                 opp-1200000000 {
129                         opp-hz = /bits/ 64 <1200000000>;
130                         opp-microvolt = <1125000>;
131                         clock-latency-ns = <140000>;
132                 };
133                 opp-1300000000 {
134                         opp-hz = /bits/ 64 <1300000000>;
135                         opp-microvolt = <1150000>;
136                         clock-latency-ns = <140000>;
137                 };
138                 opp-1400000000 {
139                         opp-hz = /bits/ 64 <1400000000>;
140                         opp-microvolt = <1200000>;
141                         clock-latency-ns = <140000>;
142                 };
143                 opp-1500000000 {
144                         opp-hz = /bits/ 64 <1500000000>;
145                         opp-microvolt = <1225000>;
146                         clock-latency-ns = <140000>;
147                 };
148                 opp-1600000000 {
149                         opp-hz = /bits/ 64 <1600000000>;
150                         opp-microvolt = <1250000>;
151                         clock-latency-ns = <140000>;
152                 };
153                 opp-1700000000 {
154                         opp-hz = /bits/ 64 <1700000000>;
155                         opp-microvolt = <1300000>;
156                         clock-latency-ns = <140000>;
157                 };
158         };
159
160         pmu {
161                 compatible = "arm,cortex-a15-pmu";
162                 interrupt-parent = <&combiner>;
163                 interrupts = <1 2>, <22 4>;
164         };
165
166         soc: soc {
167                 sram@2020000 {
168                         compatible = "mmio-sram";
169                         reg = <0x02020000 0x30000>;
170                         #address-cells = <1>;
171                         #size-cells = <1>;
172                         ranges = <0 0x02020000 0x30000>;
173
174                         smp-sram@0 {
175                                 compatible = "samsung,exynos4210-sysram";
176                                 reg = <0x0 0x1000>;
177                         };
178
179                         smp-sram@2f000 {
180                                 compatible = "samsung,exynos4210-sysram-ns";
181                                 reg = <0x2f000 0x1000>;
182                         };
183                 };
184
185                 pd_gsc: power-domain@10044000 {
186                         compatible = "samsung,exynos4210-pd";
187                         reg = <0x10044000 0x20>;
188                         #power-domain-cells = <0>;
189                         label = "GSC";
190                 };
191
192                 pd_mfc: power-domain@10044040 {
193                         compatible = "samsung,exynos4210-pd";
194                         reg = <0x10044040 0x20>;
195                         #power-domain-cells = <0>;
196                         label = "MFC";
197                 };
198
199                 pd_g3d: power-domain@10044060 {
200                         compatible = "samsung,exynos4210-pd";
201                         reg = <0x10044060 0x20>;
202                         #power-domain-cells = <0>;
203                         label = "G3D";
204                 };
205
206                 pd_disp1: power-domain@100440a0 {
207                         compatible = "samsung,exynos4210-pd";
208                         reg = <0x100440A0 0x20>;
209                         #power-domain-cells = <0>;
210                         label = "DISP1";
211                 };
212
213                 pd_mau: power-domain@100440c0 {
214                         compatible = "samsung,exynos4210-pd";
215                         reg = <0x100440C0 0x20>;
216                         #power-domain-cells = <0>;
217                         label = "MAU";
218                 };
219
220                 clock: clock-controller@10010000 {
221                         compatible = "samsung,exynos5250-clock";
222                         reg = <0x10010000 0x30000>;
223                         #clock-cells = <1>;
224                 };
225
226                 clock_audss: audss-clock-controller@3810000 {
227                         compatible = "samsung,exynos5250-audss-clock";
228                         reg = <0x03810000 0x0C>;
229                         #clock-cells = <1>;
230                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
231                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
232                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
233                         power-domains = <&pd_mau>;
234                 };
235
236                 timer@101c0000 {
237                         compatible = "samsung,exynos4210-mct";
238                         reg = <0x101C0000 0x800>;
239                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
240                         clock-names = "fin_pll", "mct";
241                         interrupts-extended = <&combiner 23 3>,
242                                               <&combiner 23 4>,
243                                               <&combiner 25 2>,
244                                               <&combiner 25 3>,
245                                               <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
246                                               <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
247                 };
248
249                 pinctrl_0: pinctrl@11400000 {
250                         compatible = "samsung,exynos5250-pinctrl";
251                         reg = <0x11400000 0x1000>;
252                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
253
254                         wakup_eint: wakeup-interrupt-controller {
255                                 compatible = "samsung,exynos4210-wakeup-eint";
256                                 interrupt-parent = <&gic>;
257                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
258                         };
259                 };
260
261                 pinctrl_1: pinctrl@13400000 {
262                         compatible = "samsung,exynos5250-pinctrl";
263                         reg = <0x13400000 0x1000>;
264                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
265                 };
266
267                 pinctrl_2: pinctrl@10d10000 {
268                         compatible = "samsung,exynos5250-pinctrl";
269                         reg = <0x10d10000 0x1000>;
270                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
271                 };
272
273                 pinctrl_3: pinctrl@3860000 {
274                         compatible = "samsung,exynos5250-pinctrl";
275                         reg = <0x03860000 0x1000>;
276                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
277                         power-domains = <&pd_mau>;
278                 };
279
280                 pmu_system_controller: system-controller@10040000 {
281                         compatible = "samsung,exynos5250-pmu", "syscon";
282                         reg = <0x10040000 0x5000>;
283                         clock-names = "clkout16";
284                         clocks = <&clock CLK_FIN_PLL>;
285                         #clock-cells = <1>;
286                         interrupt-controller;
287                         #interrupt-cells = <3>;
288                         interrupt-parent = <&gic>;
289                 };
290
291                 watchdog@101d0000 {
292                         compatible = "samsung,exynos5250-wdt";
293                         reg = <0x101D0000 0x100>;
294                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
295                         clocks = <&clock CLK_WDT>;
296                         clock-names = "watchdog";
297                         samsung,syscon-phandle = <&pmu_system_controller>;
298                 };
299
300                 mfc: codec@11000000 {
301                         compatible = "samsung,mfc-v6";
302                         reg = <0x11000000 0x10000>;
303                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
304                         power-domains = <&pd_mfc>;
305                         clocks = <&clock CLK_MFC>;
306                         clock-names = "mfc";
307                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
308                         iommu-names = "left", "right";
309                 };
310
311                 rotator: rotator@11c00000 {
312                         compatible = "samsung,exynos5250-rotator";
313                         reg = <0x11C00000 0x64>;
314                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
315                         clocks = <&clock CLK_ROTATOR>;
316                         clock-names = "rotator";
317                         iommus = <&sysmmu_rotator>;
318                 };
319
320                 mali: gpu@11800000 {
321                         compatible = "samsung,exynos5250-mali", "arm,mali-t604";
322                         reg = <0x11800000 0x5000>;
323                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
324                                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
325                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
326                         interrupt-names = "job", "mmu", "gpu";
327                         clocks = <&clock CLK_G3D>;
328                         clock-names = "core";
329                         operating-points-v2 = <&gpu_opp_table>;
330                         power-domains = <&pd_g3d>;
331                         status = "disabled";
332
333                         gpu_opp_table: gpu-opp-table {
334                                 compatible = "operating-points-v2";
335
336                                 opp-100000000 {
337                                         opp-hz = /bits/ 64 <100000000>;
338                                         opp-microvolt = <925000>;
339                                 };
340                                 opp-160000000 {
341                                         opp-hz = /bits/ 64 <160000000>;
342                                         opp-microvolt = <925000>;
343                                 };
344                                 opp-266000000 {
345                                         opp-hz = /bits/ 64 <266000000>;
346                                         opp-microvolt = <1025000>;
347                                 };
348                                 opp-350000000 {
349                                         opp-hz = /bits/ 64 <350000000>;
350                                         opp-microvolt = <1075000>;
351                                 };
352                                 opp-400000000 {
353                                         opp-hz = /bits/ 64 <400000000>;
354                                         opp-microvolt = <1125000>;
355                                 };
356                                 opp-450000000 {
357                                         opp-hz = /bits/ 64 <450000000>;
358                                         opp-microvolt = <1150000>;
359                                 };
360                                 opp-533000000 {
361                                         opp-hz = /bits/ 64 <533000000>;
362                                         opp-microvolt = <1250000>;
363                                 };
364                         };
365                 };
366
367                 tmu: tmu@10060000 {
368                         compatible = "samsung,exynos5250-tmu";
369                         reg = <0x10060000 0x100>;
370                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
371                         clocks = <&clock CLK_TMU>;
372                         clock-names = "tmu_apbif";
373                         #thermal-sensor-cells = <0>;
374                 };
375
376                 sata: sata@122f0000 {
377                         compatible = "snps,dwc-ahci";
378                         samsung,sata-freq = <66>;
379                         reg = <0x122F0000 0x1ff>;
380                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
381                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
382                         clock-names = "sata", "sclk_sata";
383                         phys = <&sata_phy>;
384                         phy-names = "sata-phy";
385                         ports-implemented = <0x1>;
386                         status = "disabled";
387                 };
388
389                 sata_phy: sata-phy@12170000 {
390                         compatible = "samsung,exynos5250-sata-phy";
391                         reg = <0x12170000 0x1ff>;
392                         clocks = <&clock CLK_SATA_PHYCTRL>;
393                         clock-names = "sata_phyctrl";
394                         #phy-cells = <0>;
395                         samsung,syscon-phandle = <&pmu_system_controller>;
396                         status = "disabled";
397                 };
398
399                 /* i2c_0-3 are defined in exynos5.dtsi */
400                 i2c_4: i2c@12ca0000 {
401                         compatible = "samsung,s3c2440-i2c";
402                         reg = <0x12CA0000 0x100>;
403                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
404                         #address-cells = <1>;
405                         #size-cells = <0>;
406                         clocks = <&clock CLK_I2C4>;
407                         clock-names = "i2c";
408                         pinctrl-names = "default";
409                         pinctrl-0 = <&i2c4_bus>;
410                         status = "disabled";
411                 };
412
413                 i2c_5: i2c@12cb0000 {
414                         compatible = "samsung,s3c2440-i2c";
415                         reg = <0x12CB0000 0x100>;
416                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
417                         #address-cells = <1>;
418                         #size-cells = <0>;
419                         clocks = <&clock CLK_I2C5>;
420                         clock-names = "i2c";
421                         pinctrl-names = "default";
422                         pinctrl-0 = <&i2c5_bus>;
423                         status = "disabled";
424                 };
425
426                 i2c_6: i2c@12cc0000 {
427                         compatible = "samsung,s3c2440-i2c";
428                         reg = <0x12CC0000 0x100>;
429                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
430                         #address-cells = <1>;
431                         #size-cells = <0>;
432                         clocks = <&clock CLK_I2C6>;
433                         clock-names = "i2c";
434                         pinctrl-names = "default";
435                         pinctrl-0 = <&i2c6_bus>;
436                         status = "disabled";
437                 };
438
439                 i2c_7: i2c@12cd0000 {
440                         compatible = "samsung,s3c2440-i2c";
441                         reg = <0x12CD0000 0x100>;
442                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
443                         #address-cells = <1>;
444                         #size-cells = <0>;
445                         clocks = <&clock CLK_I2C7>;
446                         clock-names = "i2c";
447                         pinctrl-names = "default";
448                         pinctrl-0 = <&i2c7_bus>;
449                         status = "disabled";
450                 };
451
452                 i2c_8: i2c@12ce0000 {
453                         compatible = "samsung,s3c2440-hdmiphy-i2c";
454                         reg = <0x12CE0000 0x1000>;
455                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
456                         #address-cells = <1>;
457                         #size-cells = <0>;
458                         clocks = <&clock CLK_I2C_HDMI>;
459                         clock-names = "i2c";
460                         status = "disabled";
461
462                         hdmiphy: hdmiphy@38 {
463                                 compatible = "samsung,exynos4212-hdmiphy";
464                                 reg = <0x38>;
465                         };
466                 };
467
468                 i2c_9: i2c@121d0000 {
469                         compatible = "samsung,exynos5-sata-phy-i2c";
470                         reg = <0x121D0000 0x100>;
471                         #address-cells = <1>;
472                         #size-cells = <0>;
473                         clocks = <&clock CLK_SATA_PHYI2C>;
474                         clock-names = "i2c";
475                         status = "disabled";
476                 };
477
478                 spi_0: spi@12d20000 {
479                         compatible = "samsung,exynos4210-spi";
480                         status = "disabled";
481                         reg = <0x12d20000 0x100>;
482                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
483                         dmas = <&pdma0 5
484                                 &pdma0 4>;
485                         dma-names = "tx", "rx";
486                         #address-cells = <1>;
487                         #size-cells = <0>;
488                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
489                         clock-names = "spi", "spi_busclk0";
490                         pinctrl-names = "default";
491                         pinctrl-0 = <&spi0_bus>;
492                 };
493
494                 spi_1: spi@12d30000 {
495                         compatible = "samsung,exynos4210-spi";
496                         status = "disabled";
497                         reg = <0x12d30000 0x100>;
498                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
499                         dmas = <&pdma1 5
500                                 &pdma1 4>;
501                         dma-names = "tx", "rx";
502                         #address-cells = <1>;
503                         #size-cells = <0>;
504                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
505                         clock-names = "spi", "spi_busclk0";
506                         pinctrl-names = "default";
507                         pinctrl-0 = <&spi1_bus>;
508                 };
509
510                 spi_2: spi@12d40000 {
511                         compatible = "samsung,exynos4210-spi";
512                         status = "disabled";
513                         reg = <0x12d40000 0x100>;
514                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
515                         dmas = <&pdma0 7
516                                 &pdma0 6>;
517                         dma-names = "tx", "rx";
518                         #address-cells = <1>;
519                         #size-cells = <0>;
520                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
521                         clock-names = "spi", "spi_busclk0";
522                         pinctrl-names = "default";
523                         pinctrl-0 = <&spi2_bus>;
524                 };
525
526                 mmc_0: mmc@12200000 {
527                         compatible = "samsung,exynos5250-dw-mshc";
528                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
529                         #address-cells = <1>;
530                         #size-cells = <0>;
531                         reg = <0x12200000 0x1000>;
532                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
533                         clock-names = "biu", "ciu";
534                         fifo-depth = <0x80>;
535                         status = "disabled";
536                 };
537
538                 mmc_1: mmc@12210000 {
539                         compatible = "samsung,exynos5250-dw-mshc";
540                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
541                         #address-cells = <1>;
542                         #size-cells = <0>;
543                         reg = <0x12210000 0x1000>;
544                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
545                         clock-names = "biu", "ciu";
546                         fifo-depth = <0x80>;
547                         status = "disabled";
548                 };
549
550                 mmc_2: mmc@12220000 {
551                         compatible = "samsung,exynos5250-dw-mshc";
552                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
553                         #address-cells = <1>;
554                         #size-cells = <0>;
555                         reg = <0x12220000 0x1000>;
556                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
557                         clock-names = "biu", "ciu";
558                         fifo-depth = <0x80>;
559                         status = "disabled";
560                 };
561
562                 mmc_3: mmc@12230000 {
563                         compatible = "samsung,exynos5250-dw-mshc";
564                         reg = <0x12230000 0x1000>;
565                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
566                         #address-cells = <1>;
567                         #size-cells = <0>;
568                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
569                         clock-names = "biu", "ciu";
570                         fifo-depth = <0x80>;
571                         status = "disabled";
572                 };
573
574                 i2s0: i2s@3830000 {
575                         compatible = "samsung,s5pv210-i2s";
576                         status = "disabled";
577                         reg = <0x03830000 0x100>;
578                         dmas = <&pdma0 10>,
579                                 <&pdma0 9>,
580                                 <&pdma0 8>;
581                         dma-names = "tx", "rx", "tx-sec";
582                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
583                                 <&clock_audss EXYNOS_I2S_BUS>,
584                                 <&clock_audss EXYNOS_SCLK_I2S>;
585                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
586                         samsung,idma-addr = <0x03000000>;
587                         pinctrl-names = "default";
588                         pinctrl-0 = <&i2s0_bus>;
589                         power-domains = <&pd_mau>;
590                         #clock-cells = <1>;
591                         #sound-dai-cells = <1>;
592                 };
593
594                 i2s1: i2s@12d60000 {
595                         compatible = "samsung,s3c6410-i2s";
596                         status = "disabled";
597                         reg = <0x12D60000 0x100>;
598                         dmas = <&pdma1 12>,
599                                 <&pdma1 11>;
600                         dma-names = "tx", "rx";
601                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
602                         clock-names = "iis", "i2s_opclk0";
603                         pinctrl-names = "default";
604                         pinctrl-0 = <&i2s1_bus>;
605                         power-domains = <&pd_mau>;
606                         #sound-dai-cells = <1>;
607                 };
608
609                 i2s2: i2s@12d70000 {
610                         compatible = "samsung,s3c6410-i2s";
611                         status = "disabled";
612                         reg = <0x12D70000 0x100>;
613                         dmas = <&pdma0 12>,
614                                 <&pdma0 11>;
615                         dma-names = "tx", "rx";
616                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
617                         clock-names = "iis", "i2s_opclk0";
618                         pinctrl-names = "default";
619                         pinctrl-0 = <&i2s2_bus>;
620                         power-domains = <&pd_mau>;
621                         #sound-dai-cells = <1>;
622                 };
623
624                 usb_dwc3 {
625                         compatible = "samsung,exynos5250-dwusb3";
626                         clocks = <&clock CLK_USB3>;
627                         clock-names = "usbdrd30";
628                         #address-cells = <1>;
629                         #size-cells = <1>;
630                         ranges;
631
632                         usbdrd_dwc3: dwc3@12000000 {
633                                 compatible = "synopsys,dwc3";
634                                 reg = <0x12000000 0x10000>;
635                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
636                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
637                                 phy-names = "usb2-phy", "usb3-phy";
638                         };
639                 };
640
641                 usbdrd_phy: phy@12100000 {
642                         compatible = "samsung,exynos5250-usbdrd-phy";
643                         reg = <0x12100000 0x100>;
644                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
645                         clock-names = "phy", "ref";
646                         samsung,pmu-syscon = <&pmu_system_controller>;
647                         #phy-cells = <1>;
648                 };
649
650                 ehci: usb@12110000 {
651                         compatible = "samsung,exynos4210-ehci";
652                         reg = <0x12110000 0x100>;
653                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
654
655                         clocks = <&clock CLK_USB2>;
656                         clock-names = "usbhost";
657                         phys = <&usb2_phy_gen 1>;
658                         phy-names = "host";
659                 };
660
661                 ohci: usb@12120000 {
662                         compatible = "samsung,exynos4210-ohci";
663                         reg = <0x12120000 0x100>;
664                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
665
666                         clocks = <&clock CLK_USB2>;
667                         clock-names = "usbhost";
668                         phys = <&usb2_phy_gen 1>;
669                         phy-names = "host";
670                 };
671
672                 usb2_phy_gen: phy@12130000 {
673                         compatible = "samsung,exynos5250-usb2-phy";
674                         reg = <0x12130000 0x100>;
675                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
676                         clock-names = "phy", "ref";
677                         #phy-cells = <1>;
678                         samsung,sysreg-phandle = <&sysreg_system_controller>;
679                         samsung,pmureg-phandle = <&pmu_system_controller>;
680                 };
681
682                 amba {
683                         #address-cells = <1>;
684                         #size-cells = <1>;
685                         compatible = "simple-bus";
686                         interrupt-parent = <&gic>;
687                         ranges;
688
689                         pdma0: pdma@121a0000 {
690                                 compatible = "arm,pl330", "arm,primecell";
691                                 reg = <0x121A0000 0x1000>;
692                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
693                                 clocks = <&clock CLK_PDMA0>;
694                                 clock-names = "apb_pclk";
695                                 #dma-cells = <1>;
696                                 #dma-channels = <8>;
697                                 #dma-requests = <32>;
698                         };
699
700                         pdma1: pdma@121b0000 {
701                                 compatible = "arm,pl330", "arm,primecell";
702                                 reg = <0x121B0000 0x1000>;
703                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
704                                 clocks = <&clock CLK_PDMA1>;
705                                 clock-names = "apb_pclk";
706                                 #dma-cells = <1>;
707                                 #dma-channels = <8>;
708                                 #dma-requests = <32>;
709                         };
710
711                         mdma0: mdma@10800000 {
712                                 compatible = "arm,pl330", "arm,primecell";
713                                 reg = <0x10800000 0x1000>;
714                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
715                                 clocks = <&clock CLK_MDMA0>;
716                                 clock-names = "apb_pclk";
717                                 #dma-cells = <1>;
718                                 #dma-channels = <8>;
719                                 #dma-requests = <1>;
720                         };
721
722                         mdma1: mdma@11c10000 {
723                                 compatible = "arm,pl330", "arm,primecell";
724                                 reg = <0x11C10000 0x1000>;
725                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
726                                 clocks = <&clock CLK_MDMA1>;
727                                 clock-names = "apb_pclk";
728                                 #dma-cells = <1>;
729                                 #dma-channels = <8>;
730                                 #dma-requests = <1>;
731                         };
732                 };
733
734                 gsc_0:  gsc@13e00000 {
735                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
736                         reg = <0x13e00000 0x1000>;
737                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
738                         power-domains = <&pd_gsc>;
739                         clocks = <&clock CLK_GSCL0>;
740                         clock-names = "gscl";
741                         iommus = <&sysmmu_gsc0>;
742                 };
743
744                 gsc_1:  gsc@13e10000 {
745                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
746                         reg = <0x13e10000 0x1000>;
747                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
748                         power-domains = <&pd_gsc>;
749                         clocks = <&clock CLK_GSCL1>;
750                         clock-names = "gscl";
751                         iommus = <&sysmmu_gsc1>;
752                 };
753
754                 gsc_2:  gsc@13e20000 {
755                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
756                         reg = <0x13e20000 0x1000>;
757                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
758                         power-domains = <&pd_gsc>;
759                         clocks = <&clock CLK_GSCL2>;
760                         clock-names = "gscl";
761                         iommus = <&sysmmu_gsc2>;
762                 };
763
764                 gsc_3:  gsc@13e30000 {
765                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
766                         reg = <0x13e30000 0x1000>;
767                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
768                         power-domains = <&pd_gsc>;
769                         clocks = <&clock CLK_GSCL3>;
770                         clock-names = "gscl";
771                         iommus = <&sysmmu_gsc3>;
772                 };
773
774                 hdmi: hdmi@14530000 {
775                         compatible = "samsung,exynos4212-hdmi";
776                         reg = <0x14530000 0x70000>;
777                         power-domains = <&pd_disp1>;
778                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
779                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
780                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
781                                  <&clock CLK_MOUT_HDMI>;
782                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
783                                         "sclk_hdmiphy", "mout_hdmi";
784                         samsung,syscon-phandle = <&pmu_system_controller>;
785                         phy = <&hdmiphy>;
786                         #sound-dai-cells = <0>;
787                         status = "disabled";
788                 };
789
790                 hdmicec: cec@101b0000 {
791                         compatible = "samsung,s5p-cec";
792                         reg = <0x101B0000 0x200>;
793                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
794                         clocks = <&clock CLK_HDMI_CEC>;
795                         clock-names = "hdmicec";
796                         samsung,syscon-phandle = <&pmu_system_controller>;
797                         hdmi-phandle = <&hdmi>;
798                         pinctrl-names = "default";
799                         pinctrl-0 = <&hdmi_cec>;
800                         status = "disabled";
801                 };
802
803                 mixer: mixer@14450000 {
804                         compatible = "samsung,exynos5250-mixer";
805                         reg = <0x14450000 0x10000>;
806                         power-domains = <&pd_disp1>;
807                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
808                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
809                                  <&clock CLK_SCLK_HDMI>;
810                         clock-names = "mixer", "hdmi", "sclk_hdmi";
811                         iommus = <&sysmmu_tv>;
812                         status = "disabled";
813                 };
814
815                 dp_phy: video-phy {
816                         compatible = "samsung,exynos5250-dp-video-phy";
817                         samsung,pmu-syscon = <&pmu_system_controller>;
818                         #phy-cells = <0>;
819                 };
820
821                 mipi_phy: video-phy@10040710 {
822                         compatible = "samsung,s5pv210-mipi-video-phy";
823                         reg = <0x10040710 0x100>;
824                         #phy-cells = <1>;
825                         syscon = <&pmu_system_controller>;
826                 };
827
828                 dsi_0: dsi@14500000 {
829                         compatible = "samsung,exynos4210-mipi-dsi";
830                         reg = <0x14500000 0x10000>;
831                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
832                         samsung,power-domain = <&pd_disp1>;
833                         phys = <&mipi_phy 3>;
834                         phy-names = "dsim";
835                         clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
836                         clock-names = "bus_clk", "sclk_mipi";
837                         status = "disabled";
838                         #address-cells = <1>;
839                         #size-cells = <0>;
840                 };
841
842                 adc: adc@12d10000 {
843                         compatible = "samsung,exynos-adc-v1";
844                         reg = <0x12D10000 0x100>;
845                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
846                         clocks = <&clock CLK_ADC>;
847                         clock-names = "adc";
848                         #io-channel-cells = <1>;
849                         io-channel-ranges;
850                         samsung,syscon-phandle = <&pmu_system_controller>;
851                         status = "disabled";
852                 };
853
854                 sysmmu_g2d: sysmmu@10a60000 {
855                         compatible = "samsung,exynos-sysmmu";
856                         reg = <0x10A60000 0x1000>;
857                         interrupt-parent = <&combiner>;
858                         interrupts = <24 5>;
859                         clock-names = "sysmmu", "master";
860                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
861                         #iommu-cells = <0>;
862                 };
863
864                 sysmmu_mfc_r: sysmmu@11200000 {
865                         compatible = "samsung,exynos-sysmmu";
866                         reg = <0x11200000 0x1000>;
867                         interrupt-parent = <&combiner>;
868                         interrupts = <6 2>;
869                         power-domains = <&pd_mfc>;
870                         clock-names = "sysmmu", "master";
871                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
872                         #iommu-cells = <0>;
873                 };
874
875                 sysmmu_mfc_l: sysmmu@11210000 {
876                         compatible = "samsung,exynos-sysmmu";
877                         reg = <0x11210000 0x1000>;
878                         interrupt-parent = <&combiner>;
879                         interrupts = <8 5>;
880                         power-domains = <&pd_mfc>;
881                         clock-names = "sysmmu", "master";
882                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
883                         #iommu-cells = <0>;
884                 };
885
886                 sysmmu_rotator: sysmmu@11d40000 {
887                         compatible = "samsung,exynos-sysmmu";
888                         reg = <0x11D40000 0x1000>;
889                         interrupt-parent = <&combiner>;
890                         interrupts = <4 0>;
891                         clock-names = "sysmmu", "master";
892                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
893                         #iommu-cells = <0>;
894                 };
895
896                 sysmmu_jpeg: sysmmu@11f20000 {
897                         compatible = "samsung,exynos-sysmmu";
898                         reg = <0x11F20000 0x1000>;
899                         interrupt-parent = <&combiner>;
900                         interrupts = <4 2>;
901                         power-domains = <&pd_gsc>;
902                         clock-names = "sysmmu", "master";
903                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
904                         #iommu-cells = <0>;
905                 };
906
907                 sysmmu_fimc_isp: sysmmu@13260000 {
908                         compatible = "samsung,exynos-sysmmu";
909                         reg = <0x13260000 0x1000>;
910                         interrupt-parent = <&combiner>;
911                         interrupts = <10 6>;
912                         clock-names = "sysmmu";
913                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
914                         #iommu-cells = <0>;
915                 };
916
917                 sysmmu_fimc_drc: sysmmu@13270000 {
918                         compatible = "samsung,exynos-sysmmu";
919                         reg = <0x13270000 0x1000>;
920                         interrupt-parent = <&combiner>;
921                         interrupts = <11 6>;
922                         clock-names = "sysmmu";
923                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
924                         #iommu-cells = <0>;
925                 };
926
927                 sysmmu_fimc_fd: sysmmu@132a0000 {
928                         compatible = "samsung,exynos-sysmmu";
929                         reg = <0x132A0000 0x1000>;
930                         interrupt-parent = <&combiner>;
931                         interrupts = <5 0>;
932                         clock-names = "sysmmu";
933                         clocks = <&clock CLK_SMMU_FIMC_FD>;
934                         #iommu-cells = <0>;
935                 };
936
937                 sysmmu_fimc_scc: sysmmu@13280000 {
938                         compatible = "samsung,exynos-sysmmu";
939                         reg = <0x13280000 0x1000>;
940                         interrupt-parent = <&combiner>;
941                         interrupts = <5 2>;
942                         clock-names = "sysmmu";
943                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
944                         #iommu-cells = <0>;
945                 };
946
947                 sysmmu_fimc_scp: sysmmu@13290000 {
948                         compatible = "samsung,exynos-sysmmu";
949                         reg = <0x13290000 0x1000>;
950                         interrupt-parent = <&combiner>;
951                         interrupts = <3 6>;
952                         clock-names = "sysmmu";
953                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
954                         #iommu-cells = <0>;
955                 };
956
957                 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
958                         compatible = "samsung,exynos-sysmmu";
959                         reg = <0x132B0000 0x1000>;
960                         interrupt-parent = <&combiner>;
961                         interrupts = <5 4>;
962                         clock-names = "sysmmu";
963                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
964                         #iommu-cells = <0>;
965                 };
966
967                 sysmmu_fimc_odc: sysmmu@132c0000 {
968                         compatible = "samsung,exynos-sysmmu";
969                         reg = <0x132C0000 0x1000>;
970                         interrupt-parent = <&combiner>;
971                         interrupts = <11 0>;
972                         clock-names = "sysmmu";
973                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
974                         #iommu-cells = <0>;
975                 };
976
977                 sysmmu_fimc_dis0: sysmmu@132d0000 {
978                         compatible = "samsung,exynos-sysmmu";
979                         reg = <0x132D0000 0x1000>;
980                         interrupt-parent = <&combiner>;
981                         interrupts = <10 4>;
982                         clock-names = "sysmmu";
983                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
984                         #iommu-cells = <0>;
985                 };
986
987                 sysmmu_fimc_dis1: sysmmu@132e0000 {
988                         compatible = "samsung,exynos-sysmmu";
989                         reg = <0x132E0000 0x1000>;
990                         interrupt-parent = <&combiner>;
991                         interrupts = <9 4>;
992                         clock-names = "sysmmu";
993                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
994                         #iommu-cells = <0>;
995                 };
996
997                 sysmmu_fimc_3dnr: sysmmu@132f0000 {
998                         compatible = "samsung,exynos-sysmmu";
999                         reg = <0x132F0000 0x1000>;
1000                         interrupt-parent = <&combiner>;
1001                         interrupts = <5 6>;
1002                         clock-names = "sysmmu";
1003                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
1004                         #iommu-cells = <0>;
1005                 };
1006
1007                 sysmmu_fimc_lite0: sysmmu@13c40000 {
1008                         compatible = "samsung,exynos-sysmmu";
1009                         reg = <0x13C40000 0x1000>;
1010                         interrupt-parent = <&combiner>;
1011                         interrupts = <3 4>;
1012                         power-domains = <&pd_gsc>;
1013                         clock-names = "sysmmu", "master";
1014                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1015                         #iommu-cells = <0>;
1016                 };
1017
1018                 sysmmu_fimc_lite1: sysmmu@13c50000 {
1019                         compatible = "samsung,exynos-sysmmu";
1020                         reg = <0x13C50000 0x1000>;
1021                         interrupt-parent = <&combiner>;
1022                         interrupts = <24 1>;
1023                         power-domains = <&pd_gsc>;
1024                         clock-names = "sysmmu", "master";
1025                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1026                         #iommu-cells = <0>;
1027                 };
1028
1029                 sysmmu_gsc0: sysmmu@13e80000 {
1030                         compatible = "samsung,exynos-sysmmu";
1031                         reg = <0x13E80000 0x1000>;
1032                         interrupt-parent = <&combiner>;
1033                         interrupts = <2 0>;
1034                         power-domains = <&pd_gsc>;
1035                         clock-names = "sysmmu", "master";
1036                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1037                         #iommu-cells = <0>;
1038                 };
1039
1040                 sysmmu_gsc1: sysmmu@13e90000 {
1041                         compatible = "samsung,exynos-sysmmu";
1042                         reg = <0x13E90000 0x1000>;
1043                         interrupt-parent = <&combiner>;
1044                         interrupts = <2 2>;
1045                         power-domains = <&pd_gsc>;
1046                         clock-names = "sysmmu", "master";
1047                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1048                         #iommu-cells = <0>;
1049                 };
1050
1051                 sysmmu_gsc2: sysmmu@13ea0000 {
1052                         compatible = "samsung,exynos-sysmmu";
1053                         reg = <0x13EA0000 0x1000>;
1054                         interrupt-parent = <&combiner>;
1055                         interrupts = <2 4>;
1056                         power-domains = <&pd_gsc>;
1057                         clock-names = "sysmmu", "master";
1058                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1059                         #iommu-cells = <0>;
1060                 };
1061
1062                 sysmmu_gsc3: sysmmu@13eb0000 {
1063                         compatible = "samsung,exynos-sysmmu";
1064                         reg = <0x13EB0000 0x1000>;
1065                         interrupt-parent = <&combiner>;
1066                         interrupts = <2 6>;
1067                         power-domains = <&pd_gsc>;
1068                         clock-names = "sysmmu", "master";
1069                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1070                         #iommu-cells = <0>;
1071                 };
1072
1073                 sysmmu_fimd1: sysmmu@14640000 {
1074                         compatible = "samsung,exynos-sysmmu";
1075                         reg = <0x14640000 0x1000>;
1076                         interrupt-parent = <&combiner>;
1077                         interrupts = <3 2>;
1078                         power-domains = <&pd_disp1>;
1079                         clock-names = "sysmmu", "master";
1080                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1081                         #iommu-cells = <0>;
1082                 };
1083
1084                 sysmmu_tv: sysmmu@14650000 {
1085                         compatible = "samsung,exynos-sysmmu";
1086                         reg = <0x14650000 0x1000>;
1087                         interrupt-parent = <&combiner>;
1088                         interrupts = <7 4>;
1089                         power-domains = <&pd_disp1>;
1090                         clock-names = "sysmmu", "master";
1091                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1092                         #iommu-cells = <0>;
1093                 };
1094         };
1095
1096         thermal-zones {
1097                 cpu_thermal: cpu-thermal {
1098                         polling-delay-passive = <0>;
1099                         polling-delay = <0>;
1100                         thermal-sensors = <&tmu 0>;
1101
1102                         cooling-maps {
1103                                 map0 {
1104                                      /* Corresponds to 800MHz at freq_table */
1105                                      cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1106                                 };
1107                                 map1 {
1108                                      /* Corresponds to 200MHz at freq_table */
1109                                      cooling-device = <&cpu0 15 15>,
1110                                                       <&cpu1 15 15>;
1111                                };
1112                        };
1113                 };
1114         };
1115
1116         timer {
1117                 compatible = "arm,armv7-timer";
1118                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1119                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1120                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1121                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1122                 /*
1123                  * Unfortunately we need this since some versions
1124                  * of U-Boot on Exynos don't set the CNTFRQ register,
1125                  * so we need the value from DT.
1126                  */
1127                 clock-frequency = <24000000>;
1128         };
1129 };
1130
1131 &dp {
1132         power-domains = <&pd_disp1>;
1133         clocks = <&clock CLK_DP>;
1134         clock-names = "dp";
1135         phys = <&dp_phy>;
1136         phy-names = "dp";
1137 };
1138
1139 &fimd {
1140         power-domains = <&pd_disp1>;
1141         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1142         clock-names = "sclk_fimd", "fimd";
1143         iommus = <&sysmmu_fimd1>;
1144 };
1145
1146 &g2d {
1147         iommus = <&sysmmu_g2d>;
1148         clocks = <&clock CLK_G2D>;
1149         clock-names = "fimg2d";
1150         status = "okay";
1151 };
1152
1153 &i2c_0 {
1154         clocks = <&clock CLK_I2C0>;
1155         clock-names = "i2c";
1156         pinctrl-names = "default";
1157         pinctrl-0 = <&i2c0_bus>;
1158 };
1159
1160 &i2c_1 {
1161         clocks = <&clock CLK_I2C1>;
1162         clock-names = "i2c";
1163         pinctrl-names = "default";
1164         pinctrl-0 = <&i2c1_bus>;
1165 };
1166
1167 &i2c_2 {
1168         clocks = <&clock CLK_I2C2>;
1169         clock-names = "i2c";
1170         pinctrl-names = "default";
1171         pinctrl-0 = <&i2c2_bus>;
1172 };
1173
1174 &i2c_3 {
1175         clocks = <&clock CLK_I2C3>;
1176         clock-names = "i2c";
1177         pinctrl-names = "default";
1178         pinctrl-0 = <&i2c3_bus>;
1179 };
1180
1181 &prng {
1182         clocks = <&clock CLK_SSS>;
1183         clock-names = "secss";
1184 };
1185
1186 &pwm {
1187         clocks = <&clock CLK_PWM>;
1188         clock-names = "timers";
1189 };
1190
1191 &rtc {
1192         clocks = <&clock CLK_RTC>;
1193         clock-names = "rtc";
1194         interrupt-parent = <&pmu_system_controller>;
1195         status = "disabled";
1196 };
1197
1198 &serial_0 {
1199         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1200         clock-names = "uart", "clk_uart_baud0";
1201         dmas = <&pdma0 13>, <&pdma0 14>;
1202         dma-names = "rx", "tx";
1203 };
1204
1205 &serial_1 {
1206         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1207         clock-names = "uart", "clk_uart_baud0";
1208         dmas = <&pdma1 15>, <&pdma1 16>;
1209         dma-names = "rx", "tx";
1210 };
1211
1212 &serial_2 {
1213         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1214         clock-names = "uart", "clk_uart_baud0";
1215         dmas = <&pdma0 15>, <&pdma0 16>;
1216         dma-names = "rx", "tx";
1217 };
1218
1219 &serial_3 {
1220         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1221         clock-names = "uart", "clk_uart_baud0";
1222         dmas = <&pdma1 17>, <&pdma1 18>;
1223         dma-names = "rx", "tx";
1224 };
1225
1226 &sss {
1227         clocks = <&clock CLK_SSS>;
1228         clock-names = "secss";
1229 };
1230
1231 &trng {
1232         clocks = <&clock CLK_SSS>;
1233         clock-names = "secss";
1234 };
1235
1236 #include "exynos5250-pinctrl.dtsi"
1237 #include "exynos-syscon-restart.dtsi"