arch/arm/boot/dts/exynos5250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos5250 SoC device tree source
   4  *
   5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung Exynos5250 SoC device nodes are listed in this file.
   9  * Exynos5250 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
  14  * additional nodes can be added to this file.
  15  */
  16
  17 #include <dt-bindings/clock/exynos5250.h>
  18 #include "exynos5.dtsi"
  19 #include "exynos4-cpu-thermal.dtsi"
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5250", "samsung,exynos5";
  24
  25         aliases {
  26                 spi0 = &spi_0;
  27                 spi1 = &spi_1;
  28                 spi2 = &spi_2;
  29                 gsc0 = &gsc_0;
  30                 gsc1 = &gsc_1;
  31                 gsc2 = &gsc_2;
  32                 gsc3 = &gsc_3;
  33                 i2c4 = &i2c_4;
  34                 i2c5 = &i2c_5;
  35                 i2c6 = &i2c_6;
  36                 i2c7 = &i2c_7;
  37                 i2c8 = &i2c_8;
  38                 i2c9 = &i2c_9;
  39                 pinctrl0 = &pinctrl_0;
  40                 pinctrl1 = &pinctrl_1;
  41                 pinctrl2 = &pinctrl_2;
  42                 pinctrl3 = &pinctrl_3;
  43         };
  44
  45         cpus {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48
  49                 cpu-map {
  50                         cluster0 {
  51                                 core0 {
  52                                         cpu = <&cpu0>;
  53                                 };
  54                                 core1 {
  55                                         cpu = <&cpu1>;
  56                                 };
  57                         };
  58                 };
  59
  60                 cpu0: cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a15";
  63                         reg = <0>;
  64                         clocks = <&clock CLK_ARM_CLK>;
  65                         clock-names = "cpu";
  66                         operating-points-v2 = <&cpu0_opp_table>;
  67                         #cooling-cells = <2>; /* min followed by max */
  68                 };
  69                 cpu1: cpu@1 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a15";
  72                         reg = <1>;
  73                         clocks = <&clock CLK_ARM_CLK>;
  74                         clock-names = "cpu";
  75                         operating-points-v2 = <&cpu0_opp_table>;
  76                         #cooling-cells = <2>; /* min followed by max */
  77                 };
  78         };
  79
  80         cpu0_opp_table: opp-table-0 {
  81                 compatible = "operating-points-v2";
  82                 opp-shared;
  83
  84                 opp-200000000 {
  85                         opp-hz = /bits/ 64 <200000000>;
  86                         opp-microvolt = <925000>;
  87                         clock-latency-ns = <140000>;
  88                 };
  89                 opp-300000000 {
  90                         opp-hz = /bits/ 64 <300000000>;
  91                         opp-microvolt = <937500>;
  92                         clock-latency-ns = <140000>;
  93                 };
  94                 opp-400000000 {
  95                         opp-hz = /bits/ 64 <400000000>;
  96                         opp-microvolt = <950000>;
  97                         clock-latency-ns = <140000>;
  98                 };
  99                 opp-500000000 {
 100                         opp-hz = /bits/ 64 <500000000>;
 101                         opp-microvolt = <975000>;
 102                         clock-latency-ns = <140000>;
 103                 };
 104                 opp-600000000 {
 105                         opp-hz = /bits/ 64 <600000000>;
 106                         opp-microvolt = <1000000>;
 107                         clock-latency-ns = <140000>;
 108                 };
 109                 opp-700000000 {
 110                         opp-hz = /bits/ 64 <700000000>;
 111                         opp-microvolt = <1012500>;
 112                         clock-latency-ns = <140000>;
 113                 };
 114                 opp-800000000 {
 115                         opp-hz = /bits/ 64 <800000000>;
 116                         opp-microvolt = <1025000>;
 117                         clock-latency-ns = <140000>;
 118                 };
 119                 opp-900000000 {
 120                         opp-hz = /bits/ 64 <900000000>;
 121                         opp-microvolt = <1050000>;
 122                         clock-latency-ns = <140000>;
 123                 };
 124                 opp-1000000000 {
 125                         opp-hz = /bits/ 64 <1000000000>;
 126                         opp-microvolt = <1075000>;
 127                         clock-latency-ns = <140000>;
 128                         opp-suspend;
 129                 };
 130                 opp-1100000000 {
 131                         opp-hz = /bits/ 64 <1100000000>;
 132                         opp-microvolt = <1100000>;
 133                         clock-latency-ns = <140000>;
 134                 };
 135                 opp-1200000000 {
 136                         opp-hz = /bits/ 64 <1200000000>;
 137                         opp-microvolt = <1125000>;
 138                         clock-latency-ns = <140000>;
 139                 };
 140                 opp-1300000000 {
 141                         opp-hz = /bits/ 64 <1300000000>;
 142                         opp-microvolt = <1150000>;
 143                         clock-latency-ns = <140000>;
 144                 };
 145                 opp-1400000000 {
 146                         opp-hz = /bits/ 64 <1400000000>;
 147                         opp-microvolt = <1200000>;
 148                         clock-latency-ns = <140000>;
 149                 };
 150                 opp-1500000000 {
 151                         opp-hz = /bits/ 64 <1500000000>;
 152                         opp-microvolt = <1225000>;
 153                         clock-latency-ns = <140000>;
 154                 };
 155                 opp-1600000000 {
 156                         opp-hz = /bits/ 64 <1600000000>;
 157                         opp-microvolt = <1250000>;
 158                         clock-latency-ns = <140000>;
 159                 };
 160                 opp-1700000000 {
 161                         opp-hz = /bits/ 64 <1700000000>;
 162                         opp-microvolt = <1300000>;
 163                         clock-latency-ns = <140000>;
 164                 };
 165         };
 166
 167         pmu {
 168                 compatible = "arm,cortex-a15-pmu";
 169                 interrupt-parent = <&combiner>;
 170                 interrupts = <1 2>, <22 4>;
 171         };
 172
 173         soc: soc {
 174                 sram@2020000 {
 175                         compatible = "mmio-sram";
 176                         reg = <0x02020000 0x30000>;
 177                         #address-cells = <1>;
 178                         #size-cells = <1>;
 179                         ranges = <0 0x02020000 0x30000>;
 180
 181                         smp-sram@0 {
 182                                 compatible = "samsung,exynos4210-sysram";
 183                                 reg = <0x0 0x1000>;
 184                         };
 185
 186                         smp-sram@2f000 {
 187                                 compatible = "samsung,exynos4210-sysram-ns";
 188                                 reg = <0x2f000 0x1000>;
 189                         };
 190                 };
 191
 192                 pd_gsc: power-domain@10044000 {
 193                         compatible = "samsung,exynos4210-pd";
 194                         reg = <0x10044000 0x20>;
 195                         #power-domain-cells = <0>;
 196                         label = "GSC";
 197                 };
 198
 199                 pd_mfc: power-domain@10044040 {
 200                         compatible = "samsung,exynos4210-pd";
 201                         reg = <0x10044040 0x20>;
 202                         #power-domain-cells = <0>;
 203                         label = "MFC";
 204                 };
 205
 206                 pd_g3d: power-domain@10044060 {
 207                         compatible = "samsung,exynos4210-pd";
 208                         reg = <0x10044060 0x20>;
 209                         #power-domain-cells = <0>;
 210                         label = "G3D";
 211                 };
 212
 213                 pd_disp1: power-domain@100440a0 {
 214                         compatible = "samsung,exynos4210-pd";
 215                         reg = <0x100440a0 0x20>;
 216                         #power-domain-cells = <0>;
 217                         label = "DISP1";
 218                 };
 219
 220                 pd_mau: power-domain@100440c0 {
 221                         compatible = "samsung,exynos4210-pd";
 222                         reg = <0x100440c0 0x20>;
 223                         #power-domain-cells = <0>;
 224                         label = "MAU";
 225                 };
 226
 227                 clock: clock-controller@10010000 {
 228                         compatible = "samsung,exynos5250-clock";
 229                         reg = <0x10010000 0x30000>;
 230                         #clock-cells = <1>;
 231                 };
 232
 233                 clock_audss: audss-clock-controller@3810000 {
 234                         compatible = "samsung,exynos5250-audss-clock";
 235                         reg = <0x03810000 0x0c>;
 236                         #clock-cells = <1>;
 237                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 238                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 239                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 240                         power-domains = <&pd_mau>;
 241                 };
 242
 243                 timer@101c0000 {
 244                         compatible = "samsung,exynos5250-mct",
 245                                      "samsung,exynos4210-mct";
 246                         reg = <0x101c0000 0x800>;
 247                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 248                         clock-names = "fin_pll", "mct";
 249                         interrupts-extended = <&combiner 23 3>,
 250                                               <&combiner 23 4>,
 251                                               <&combiner 25 2>,
 252                                               <&combiner 25 3>,
 253                                               <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 254                                               <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 255                 };
 256
 257                 pinctrl_0: pinctrl@11400000 {
 258                         compatible = "samsung,exynos5250-pinctrl";
 259                         reg = <0x11400000 0x1000>;
 260                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 261
 262                         wakup_eint: wakeup-interrupt-controller {
 263                                 compatible = "samsung,exynos4210-wakeup-eint";
 264                                 interrupt-parent = <&gic>;
 265                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 266                         };
 267                 };
 268
 269                 pinctrl_1: pinctrl@13400000 {
 270                         compatible = "samsung,exynos5250-pinctrl";
 271                         reg = <0x13400000 0x1000>;
 272                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 273                 };
 274
 275                 pinctrl_2: pinctrl@10d10000 {
 276                         compatible = "samsung,exynos5250-pinctrl";
 277                         reg = <0x10d10000 0x1000>;
 278                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 279                 };
 280
 281                 pinctrl_3: pinctrl@3860000 {
 282                         compatible = "samsung,exynos5250-pinctrl";
 283                         reg = <0x03860000 0x1000>;
 284                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 285                         power-domains = <&pd_mau>;
 286                 };
 287
 288                 pmu_system_controller: system-controller@10040000 {
 289                         compatible = "samsung,exynos5250-pmu", "simple-mfd", "syscon";
 290                         reg = <0x10040000 0x5000>;
 291                         clock-names = "clkout16";
 292                         clocks = <&clock CLK_FIN_PLL>;
 293                         #clock-cells = <1>;
 294                         interrupt-controller;
 295                         #interrupt-cells = <3>;
 296                         interrupt-parent = <&gic>;
 297
 298                         dp_phy: dp-phy {
 299                                 compatible = "samsung,exynos5250-dp-video-phy";
 300                                 #phy-cells = <0>;
 301                         };
 302
 303                         mipi_phy: mipi-phy {
 304                                 compatible = "samsung,s5pv210-mipi-video-phy";
 305                                 #phy-cells = <1>;
 306                         };
 307                 };
 308
 309                 watchdog@101d0000 {
 310                         compatible = "samsung,exynos5250-wdt";
 311                         reg = <0x101d0000 0x100>;
 312                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&clock CLK_WDT>;
 314                         clock-names = "watchdog";
 315                         samsung,syscon-phandle = <&pmu_system_controller>;
 316                 };
 317
 318                 mfc: codec@11000000 {
 319                         compatible = "samsung,mfc-v6";
 320                         reg = <0x11000000 0x10000>;
 321                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 322                         power-domains = <&pd_mfc>;
 323                         clocks = <&clock CLK_MFC>;
 324                         clock-names = "mfc";
 325                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 326                         iommu-names = "left", "right";
 327                 };
 328
 329                 rotator: rotator@11c00000 {
 330                         compatible = "samsung,exynos5250-rotator";
 331                         reg = <0x11c00000 0x64>;
 332                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&clock CLK_ROTATOR>;
 334                         clock-names = "rotator";
 335                         iommus = <&sysmmu_rotator>;
 336                 };
 337
 338                 mali: gpu@11800000 {
 339                         compatible = "samsung,exynos5250-mali", "arm,mali-t604";
 340                         reg = <0x11800000 0x5000>;
 341                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 342                                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 344                         interrupt-names = "job", "mmu", "gpu";
 345                         clocks = <&clock CLK_G3D>;
 346                         clock-names = "core";
 347                         operating-points-v2 = <&gpu_opp_table>;
 348                         power-domains = <&pd_g3d>;
 349                         status = "disabled";
 350
 351                         gpu_opp_table: opp-table {
 352                                 compatible = "operating-points-v2";
 353
 354                                 opp-100000000 {
 355                                         opp-hz = /bits/ 64 <100000000>;
 356                                         opp-microvolt = <925000>;
 357                                 };
 358                                 opp-160000000 {
 359                                         opp-hz = /bits/ 64 <160000000>;
 360                                         opp-microvolt = <925000>;
 361                                 };
 362                                 opp-266000000 {
 363                                         opp-hz = /bits/ 64 <266000000>;
 364                                         opp-microvolt = <1025000>;
 365                                 };
 366                                 opp-350000000 {
 367                                         opp-hz = /bits/ 64 <350000000>;
 368                                         opp-microvolt = <1075000>;
 369                                 };
 370                                 opp-400000000 {
 371                                         opp-hz = /bits/ 64 <400000000>;
 372                                         opp-microvolt = <1125000>;
 373                                 };
 374                                 opp-450000000 {
 375                                         opp-hz = /bits/ 64 <450000000>;
 376                                         opp-microvolt = <1150000>;
 377                                 };
 378                                 opp-533000000 {
 379                                         opp-hz = /bits/ 64 <533000000>;
 380                                         opp-microvolt = <1250000>;
 381                                 };
 382                         };
 383                 };
 384
 385                 tmu: tmu@10060000 {
 386                         compatible = "samsung,exynos5250-tmu";
 387                         reg = <0x10060000 0x100>;
 388                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&clock CLK_TMU>;
 390                         clock-names = "tmu_apbif";
 391                         #thermal-sensor-cells = <0>;
 392                 };
 393
 394                 sata: sata@122f0000 {
 395                         compatible = "snps,dwc-ahci";
 396                         reg = <0x122f0000 0x1ff>;
 397                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 399                         clock-names = "sata", "pclk";
 400                         phys = <&sata_phy>;
 401                         phy-names = "sata-phy";
 402                         ports-implemented = <0x1>;
 403                         status = "disabled";
 404                 };
 405
 406                 sata_phy: sata-phy@12170000 {
 407                         compatible = "samsung,exynos5250-sata-phy";
 408                         reg = <0x12170000 0x1ff>;
 409                         clocks = <&clock CLK_SATA_PHYCTRL>;
 410                         clock-names = "sata_phyctrl";
 411                         #phy-cells = <0>;
 412                         samsung,syscon-phandle = <&pmu_system_controller>;
 413                         status = "disabled";
 414                 };
 415
 416                 /* i2c_0-3 are defined in exynos5.dtsi */
 417                 i2c_4: i2c@12ca0000 {
 418                         compatible = "samsung,s3c2440-i2c";
 419                         reg = <0x12ca0000 0x100>;
 420                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         clocks = <&clock CLK_I2C4>;
 424                         clock-names = "i2c";
 425                         pinctrl-names = "default";
 426                         pinctrl-0 = <&i2c4_bus>;
 427                         status = "disabled";
 428                 };
 429
 430                 i2c_5: i2c@12cb0000 {
 431                         compatible = "samsung,s3c2440-i2c";
 432                         reg = <0x12cb0000 0x100>;
 433                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         clocks = <&clock CLK_I2C5>;
 437                         clock-names = "i2c";
 438                         pinctrl-names = "default";
 439                         pinctrl-0 = <&i2c5_bus>;
 440                         status = "disabled";
 441                 };
 442
 443                 i2c_6: i2c@12cc0000 {
 444                         compatible = "samsung,s3c2440-i2c";
 445                         reg = <0x12cc0000 0x100>;
 446                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         clocks = <&clock CLK_I2C6>;
 450                         clock-names = "i2c";
 451                         pinctrl-names = "default";
 452                         pinctrl-0 = <&i2c6_bus>;
 453                         status = "disabled";
 454                 };
 455
 456                 i2c_7: i2c@12cd0000 {
 457                         compatible = "samsung,s3c2440-i2c";
 458                         reg = <0x12cd0000 0x100>;
 459                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         clocks = <&clock CLK_I2C7>;
 463                         clock-names = "i2c";
 464                         pinctrl-names = "default";
 465                         pinctrl-0 = <&i2c7_bus>;
 466                         status = "disabled";
 467                 };
 468
 469                 i2c_8: i2c@12ce0000 {
 470                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 471                         reg = <0x12ce0000 0x1000>;
 472                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         clocks = <&clock CLK_I2C_HDMI>;
 476                         clock-names = "i2c";
 477                         status = "disabled";
 478
 479                         hdmiphy: hdmi-phy@38 {
 480                                 compatible = "samsung,exynos4212-hdmiphy";
 481                                 reg = <0x38>;
 482                         };
 483                 };
 484
 485                 i2c_9: i2c@121d0000 {
 486                         compatible = "samsung,exynos5-sata-phy-i2c";
 487                         reg = <0x121d0000 0x100>;
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         clocks = <&clock CLK_SATA_PHYI2C>;
 491                         clock-names = "i2c";
 492                         status = "disabled";
 493
 494                         sata_phy_i2c: sata-phy-i2c@38 {
 495                                 compatible = "samsung,exynos-sataphy-i2c";
 496                                 reg = <0x38>;
 497                                 status = "disabled";
 498                         };
 499                 };
 500
 501                 spi_0: spi@12d20000 {
 502                         compatible = "samsung,exynos4210-spi";
 503                         status = "disabled";
 504                         reg = <0x12d20000 0x100>;
 505                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 506                         dmas = <&pdma0 5>, <&pdma0 4>;
 507                         dma-names = "tx", "rx";
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 511                         clock-names = "spi", "spi_busclk0";
 512                         pinctrl-names = "default";
 513                         pinctrl-0 = <&spi0_bus>;
 514                 };
 515
 516                 spi_1: spi@12d30000 {
 517                         compatible = "samsung,exynos4210-spi";
 518                         status = "disabled";
 519                         reg = <0x12d30000 0x100>;
 520                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 521                         dmas = <&pdma1 5>, <&pdma1 4>;
 522                         dma-names = "tx", "rx";
 523                         #address-cells = <1>;
 524                         #size-cells = <0>;
 525                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 526                         clock-names = "spi", "spi_busclk0";
 527                         pinctrl-names = "default";
 528                         pinctrl-0 = <&spi1_bus>;
 529                 };
 530
 531                 spi_2: spi@12d40000 {
 532                         compatible = "samsung,exynos4210-spi";
 533                         status = "disabled";
 534                         reg = <0x12d40000 0x100>;
 535                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 536                         dmas = <&pdma0 7>, <&pdma0 6>;
 537                         dma-names = "tx", "rx";
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 541                         clock-names = "spi", "spi_busclk0";
 542                         pinctrl-names = "default";
 543                         pinctrl-0 = <&spi2_bus>;
 544                 };
 545
 546                 mmc_0: mmc@12200000 {
 547                         compatible = "samsung,exynos5250-dw-mshc";
 548                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                         reg = <0x12200000 0x1000>;
 552                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 553                         clock-names = "biu", "ciu";
 554                         fifo-depth = <0x80>;
 555                         status = "disabled";
 556                 };
 557
 558                 mmc_1: mmc@12210000 {
 559                         compatible = "samsung,exynos5250-dw-mshc";
 560                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                         reg = <0x12210000 0x1000>;
 564                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 565                         clock-names = "biu", "ciu";
 566                         fifo-depth = <0x80>;
 567                         status = "disabled";
 568                 };
 569
 570                 mmc_2: mmc@12220000 {
 571                         compatible = "samsung,exynos5250-dw-mshc";
 572                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                         reg = <0x12220000 0x1000>;
 576                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 577                         clock-names = "biu", "ciu";
 578                         fifo-depth = <0x80>;
 579                         status = "disabled";
 580                 };
 581
 582                 mmc_3: mmc@12230000 {
 583                         compatible = "samsung,exynos5250-dw-mshc";
 584                         reg = <0x12230000 0x1000>;
 585                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 586                         #address-cells = <1>;
 587                         #size-cells = <0>;
 588                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 589                         clock-names = "biu", "ciu";
 590                         fifo-depth = <0x80>;
 591                         status = "disabled";
 592                 };
 593
 594                 i2s0: i2s@3830000 {
 595                         compatible = "samsung,s5pv210-i2s";
 596                         status = "disabled";
 597                         reg = <0x03830000 0x100>;
 598                         dmas = <&pdma0 10>,
 599                                 <&pdma0 9>,
 600                                 <&pdma0 8>;
 601                         dma-names = "tx", "rx", "tx-sec";
 602                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 603                                 <&clock_audss EXYNOS_I2S_BUS>,
 604                                 <&clock_audss EXYNOS_SCLK_I2S>;
 605                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 606                         samsung,idma-addr = <0x03000000>;
 607                         pinctrl-names = "default";
 608                         pinctrl-0 = <&i2s0_bus>;
 609                         power-domains = <&pd_mau>;
 610                         #clock-cells = <1>;
 611                         #sound-dai-cells = <1>;
 612                 };
 613
 614                 i2s1: i2s@12d60000 {
 615                         compatible = "samsung,s3c6410-i2s";
 616                         status = "disabled";
 617                         reg = <0x12d60000 0x100>;
 618                         dmas = <&pdma1 12>,
 619                                 <&pdma1 11>;
 620                         dma-names = "tx", "rx";
 621                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 622                         clock-names = "iis", "i2s_opclk0";
 623                         pinctrl-names = "default";
 624                         pinctrl-0 = <&i2s1_bus>;
 625                         power-domains = <&pd_mau>;
 626                         #sound-dai-cells = <1>;
 627                 };
 628
 629                 i2s2: i2s@12d70000 {
 630                         compatible = "samsung,s3c6410-i2s";
 631                         status = "disabled";
 632                         reg = <0x12d70000 0x100>;
 633                         dmas = <&pdma0 12>,
 634                                 <&pdma0 11>;
 635                         dma-names = "tx", "rx";
 636                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 637                         clock-names = "iis", "i2s_opclk0";
 638                         pinctrl-names = "default";
 639                         pinctrl-0 = <&i2s2_bus>;
 640                         power-domains = <&pd_mau>;
 641                         #sound-dai-cells = <1>;
 642                 };
 643
 644                 usbdrd: usb@12000000 {
 645                         compatible = "samsung,exynos5250-dwusb3";
 646                         clocks = <&clock CLK_USB3>;
 647                         clock-names = "usbdrd30";
 648                         #address-cells = <1>;
 649                         #size-cells = <1>;
 650                         ranges = <0x0 0x12000000 0x10000>;
 651
 652                         usbdrd_dwc3: usb@0 {
 653                                 compatible = "snps,dwc3";
 654                                 reg = <0x0 0x10000>;
 655                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 656                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 657                                 phy-names = "usb2-phy", "usb3-phy";
 658                         };
 659                 };
 660
 661                 usbdrd_phy: phy@12100000 {
 662                         compatible = "samsung,exynos5250-usbdrd-phy";
 663                         reg = <0x12100000 0x100>;
 664                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 665                         clock-names = "phy", "ref";
 666                         samsung,pmu-syscon = <&pmu_system_controller>;
 667                         #phy-cells = <1>;
 668                 };
 669
 670                 ehci: usb@12110000 {
 671                         compatible = "samsung,exynos4210-ehci";
 672                         reg = <0x12110000 0x100>;
 673                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 674
 675                         clocks = <&clock CLK_USB2>;
 676                         clock-names = "usbhost";
 677                         phys = <&usb2_phy_gen 1>;
 678                         phy-names = "host";
 679                 };
 680
 681                 ohci: usb@12120000 {
 682                         compatible = "samsung,exynos4210-ohci";
 683                         reg = <0x12120000 0x100>;
 684                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 685
 686                         clocks = <&clock CLK_USB2>;
 687                         clock-names = "usbhost";
 688                         phys = <&usb2_phy_gen 1>;
 689                         phy-names = "host";
 690                 };
 691
 692                 usb2_phy_gen: phy@12130000 {
 693                         compatible = "samsung,exynos5250-usb2-phy";
 694                         reg = <0x12130000 0x100>;
 695                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 696                         clock-names = "phy", "ref";
 697                         #phy-cells = <1>;
 698                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 699                         samsung,pmureg-phandle = <&pmu_system_controller>;
 700                 };
 701
 702                 pdma0: dma-controller@121a0000 {
 703                         compatible = "arm,pl330", "arm,primecell";
 704                         reg = <0x121a0000 0x1000>;
 705                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 706                         clocks = <&clock CLK_PDMA0>;
 707                         clock-names = "apb_pclk";
 708                         #dma-cells = <1>;
 709                 };
 710
 711                 pdma1: dma-controller@121b0000 {
 712                         compatible = "arm,pl330", "arm,primecell";
 713                         reg = <0x121b0000 0x1000>;
 714                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 715                         clocks = <&clock CLK_PDMA1>;
 716                         clock-names = "apb_pclk";
 717                         #dma-cells = <1>;
 718                 };
 719
 720                 mdma0: dma-controller@10800000 {
 721                         compatible = "arm,pl330", "arm,primecell";
 722                         reg = <0x10800000 0x1000>;
 723                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&clock CLK_MDMA0>;
 725                         clock-names = "apb_pclk";
 726                         #dma-cells = <1>;
 727                 };
 728
 729                 mdma1: dma-controller@11c10000 {
 730                         compatible = "arm,pl330", "arm,primecell";
 731                         reg = <0x11c10000 0x1000>;
 732                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 733                         clocks = <&clock CLK_MDMA1>;
 734                         clock-names = "apb_pclk";
 735                         #dma-cells = <1>;
 736                 };
 737
 738                 gsc_0: gsc@13e00000 {
 739                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 740                         reg = <0x13e00000 0x1000>;
 741                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 742                         power-domains = <&pd_gsc>;
 743                         clocks = <&clock CLK_GSCL0>;
 744                         clock-names = "gscl";
 745                         iommus = <&sysmmu_gsc0>;
 746                 };
 747
 748                 gsc_1: gsc@13e10000 {
 749                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 750                         reg = <0x13e10000 0x1000>;
 751                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 752                         power-domains = <&pd_gsc>;
 753                         clocks = <&clock CLK_GSCL1>;
 754                         clock-names = "gscl";
 755                         iommus = <&sysmmu_gsc1>;
 756                 };
 757
 758                 gsc_2: gsc@13e20000 {
 759                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 760                         reg = <0x13e20000 0x1000>;
 761                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 762                         power-domains = <&pd_gsc>;
 763                         clocks = <&clock CLK_GSCL2>;
 764                         clock-names = "gscl";
 765                         iommus = <&sysmmu_gsc2>;
 766                 };
 767
 768                 gsc_3: gsc@13e30000 {
 769                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 770                         reg = <0x13e30000 0x1000>;
 771                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 772                         power-domains = <&pd_gsc>;
 773                         clocks = <&clock CLK_GSCL3>;
 774                         clock-names = "gscl";
 775                         iommus = <&sysmmu_gsc3>;
 776                 };
 777
 778                 hdmi: hdmi@14530000 {
 779                         compatible = "samsung,exynos4212-hdmi";
 780                         reg = <0x14530000 0x70000>;
 781                         power-domains = <&pd_disp1>;
 782                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 784                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 785                                  <&clock CLK_MOUT_HDMI>;
 786                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 787                                         "sclk_hdmiphy", "mout_hdmi";
 788                         samsung,syscon-phandle = <&pmu_system_controller>;
 789                         phy = <&hdmiphy>;
 790                         #sound-dai-cells = <0>;
 791                         status = "disabled";
 792                 };
 793
 794                 hdmicec: cec@101b0000 {
 795                         compatible = "samsung,s5p-cec";
 796                         reg = <0x101b0000 0x200>;
 797                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 798                         clocks = <&clock CLK_HDMI_CEC>;
 799                         clock-names = "hdmicec";
 800                         samsung,syscon-phandle = <&pmu_system_controller>;
 801                         hdmi-phandle = <&hdmi>;
 802                         pinctrl-names = "default";
 803                         pinctrl-0 = <&hdmi_cec>;
 804                         status = "disabled";
 805                 };
 806
 807                 mixer: mixer@14450000 {
 808                         compatible = "samsung,exynos5250-mixer";
 809                         reg = <0x14450000 0x10000>;
 810                         power-domains = <&pd_disp1>;
 811                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 813                                  <&clock CLK_SCLK_HDMI>;
 814                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 815                         iommus = <&sysmmu_tv>;
 816                         status = "disabled";
 817                 };
 818
 819                 dsi_0: dsi@14500000 {
 820                         compatible = "samsung,exynos4210-mipi-dsi";
 821                         reg = <0x14500000 0x10000>;
 822                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 823                         samsung,power-domain = <&pd_disp1>;
 824                         phys = <&mipi_phy 3>;
 825                         phy-names = "dsim";
 826                         clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
 827                         clock-names = "bus_clk", "sclk_mipi";
 828                         status = "disabled";
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831                 };
 832
 833                 adc: adc@12d10000 {
 834                         compatible = "samsung,exynos-adc-v1";
 835                         reg = <0x12d10000 0x100>;
 836                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 837                         clocks = <&clock CLK_ADC>;
 838                         clock-names = "adc";
 839                         #io-channel-cells = <1>;
 840                         samsung,syscon-phandle = <&pmu_system_controller>;
 841                         status = "disabled";
 842                 };
 843
 844                 sysmmu_g2d: sysmmu@10a60000 {
 845                         compatible = "samsung,exynos-sysmmu";
 846                         reg = <0x10a60000 0x1000>;
 847                         interrupt-parent = <&combiner>;
 848                         interrupts = <24 5>;
 849                         clock-names = "sysmmu", "master";
 850                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 851                         #iommu-cells = <0>;
 852                 };
 853
 854                 sysmmu_mfc_r: sysmmu@11200000 {
 855                         compatible = "samsung,exynos-sysmmu";
 856                         reg = <0x11200000 0x1000>;
 857                         interrupt-parent = <&combiner>;
 858                         interrupts = <6 2>;
 859                         power-domains = <&pd_mfc>;
 860                         clock-names = "sysmmu", "master";
 861                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 862                         #iommu-cells = <0>;
 863                 };
 864
 865                 sysmmu_mfc_l: sysmmu@11210000 {
 866                         compatible = "samsung,exynos-sysmmu";
 867                         reg = <0x11210000 0x1000>;
 868                         interrupt-parent = <&combiner>;
 869                         interrupts = <8 5>;
 870                         power-domains = <&pd_mfc>;
 871                         clock-names = "sysmmu", "master";
 872                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 873                         #iommu-cells = <0>;
 874                 };
 875
 876                 sysmmu_rotator: sysmmu@11d40000 {
 877                         compatible = "samsung,exynos-sysmmu";
 878                         reg = <0x11d40000 0x1000>;
 879                         interrupt-parent = <&combiner>;
 880                         interrupts = <4 0>;
 881                         clock-names = "sysmmu", "master";
 882                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 883                         #iommu-cells = <0>;
 884                 };
 885
 886                 sysmmu_jpeg: sysmmu@11f20000 {
 887                         compatible = "samsung,exynos-sysmmu";
 888                         reg = <0x11f20000 0x1000>;
 889                         interrupt-parent = <&combiner>;
 890                         interrupts = <4 2>;
 891                         power-domains = <&pd_gsc>;
 892                         clock-names = "sysmmu", "master";
 893                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 894                         #iommu-cells = <0>;
 895                 };
 896
 897                 sysmmu_fimc_isp: sysmmu@13260000 {
 898                         compatible = "samsung,exynos-sysmmu";
 899                         reg = <0x13260000 0x1000>;
 900                         interrupt-parent = <&combiner>;
 901                         interrupts = <10 6>;
 902                         clock-names = "sysmmu";
 903                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
 904                         #iommu-cells = <0>;
 905                 };
 906
 907                 sysmmu_fimc_drc: sysmmu@13270000 {
 908                         compatible = "samsung,exynos-sysmmu";
 909                         reg = <0x13270000 0x1000>;
 910                         interrupt-parent = <&combiner>;
 911                         interrupts = <11 6>;
 912                         clock-names = "sysmmu";
 913                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
 914                         #iommu-cells = <0>;
 915                 };
 916
 917                 sysmmu_fimc_fd: sysmmu@132a0000 {
 918                         compatible = "samsung,exynos-sysmmu";
 919                         reg = <0x132a0000 0x1000>;
 920                         interrupt-parent = <&combiner>;
 921                         interrupts = <5 0>;
 922                         clock-names = "sysmmu";
 923                         clocks = <&clock CLK_SMMU_FIMC_FD>;
 924                         #iommu-cells = <0>;
 925                 };
 926
 927                 sysmmu_fimc_scc: sysmmu@13280000 {
 928                         compatible = "samsung,exynos-sysmmu";
 929                         reg = <0x13280000 0x1000>;
 930                         interrupt-parent = <&combiner>;
 931                         interrupts = <5 2>;
 932                         clock-names = "sysmmu";
 933                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
 934                         #iommu-cells = <0>;
 935                 };
 936
 937                 sysmmu_fimc_scp: sysmmu@13290000 {
 938                         compatible = "samsung,exynos-sysmmu";
 939                         reg = <0x13290000 0x1000>;
 940                         interrupt-parent = <&combiner>;
 941                         interrupts = <3 6>;
 942                         clock-names = "sysmmu";
 943                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
 944                         #iommu-cells = <0>;
 945                 };
 946
 947                 sysmmu_fimc_mcuctl: sysmmu@132b0000 {
 948                         compatible = "samsung,exynos-sysmmu";
 949                         reg = <0x132b0000 0x1000>;
 950                         interrupt-parent = <&combiner>;
 951                         interrupts = <5 4>;
 952                         clock-names = "sysmmu";
 953                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
 954                         #iommu-cells = <0>;
 955                 };
 956
 957                 sysmmu_fimc_odc: sysmmu@132c0000 {
 958                         compatible = "samsung,exynos-sysmmu";
 959                         reg = <0x132c0000 0x1000>;
 960                         interrupt-parent = <&combiner>;
 961                         interrupts = <11 0>;
 962                         clock-names = "sysmmu";
 963                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
 964                         #iommu-cells = <0>;
 965                 };
 966
 967                 sysmmu_fimc_dis0: sysmmu@132d0000 {
 968                         compatible = "samsung,exynos-sysmmu";
 969                         reg = <0x132d0000 0x1000>;
 970                         interrupt-parent = <&combiner>;
 971                         interrupts = <10 4>;
 972                         clock-names = "sysmmu";
 973                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 974                         #iommu-cells = <0>;
 975                 };
 976
 977                 sysmmu_fimc_dis1: sysmmu@132e0000 {
 978                         compatible = "samsung,exynos-sysmmu";
 979                         reg = <0x132e0000 0x1000>;
 980                         interrupt-parent = <&combiner>;
 981                         interrupts = <9 4>;
 982                         clock-names = "sysmmu";
 983                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 984                         #iommu-cells = <0>;
 985                 };
 986
 987                 sysmmu_fimc_3dnr: sysmmu@132f0000 {
 988                         compatible = "samsung,exynos-sysmmu";
 989                         reg = <0x132f0000 0x1000>;
 990                         interrupt-parent = <&combiner>;
 991                         interrupts = <5 6>;
 992                         clock-names = "sysmmu";
 993                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
 994                         #iommu-cells = <0>;
 995                 };
 996
 997                 sysmmu_fimc_lite0: sysmmu@13c40000 {
 998                         compatible = "samsung,exynos-sysmmu";
 999                         reg = <0x13c40000 0x1000>;
1000                         interrupt-parent = <&combiner>;
1001                         interrupts = <3 4>;
1002                         power-domains = <&pd_gsc>;
1003                         clock-names = "sysmmu", "master";
1004                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
1005                         #iommu-cells = <0>;
1006                 };
1007
1008                 sysmmu_fimc_lite1: sysmmu@13c50000 {
1009                         compatible = "samsung,exynos-sysmmu";
1010                         reg = <0x13c50000 0x1000>;
1011                         interrupt-parent = <&combiner>;
1012                         interrupts = <24 1>;
1013                         power-domains = <&pd_gsc>;
1014                         clock-names = "sysmmu", "master";
1015                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
1016                         #iommu-cells = <0>;
1017                 };
1018
1019                 sysmmu_gsc0: sysmmu@13e80000 {
1020                         compatible = "samsung,exynos-sysmmu";
1021                         reg = <0x13e80000 0x1000>;
1022                         interrupt-parent = <&combiner>;
1023                         interrupts = <2 0>;
1024                         power-domains = <&pd_gsc>;
1025                         clock-names = "sysmmu", "master";
1026                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1027                         #iommu-cells = <0>;
1028                 };
1029
1030                 sysmmu_gsc1: sysmmu@13e90000 {
1031                         compatible = "samsung,exynos-sysmmu";
1032                         reg = <0x13e90000 0x1000>;
1033                         interrupt-parent = <&combiner>;
1034                         interrupts = <2 2>;
1035                         power-domains = <&pd_gsc>;
1036                         clock-names = "sysmmu", "master";
1037                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1038                         #iommu-cells = <0>;
1039                 };
1040
1041                 sysmmu_gsc2: sysmmu@13ea0000 {
1042                         compatible = "samsung,exynos-sysmmu";
1043                         reg = <0x13ea0000 0x1000>;
1044                         interrupt-parent = <&combiner>;
1045                         interrupts = <2 4>;
1046                         power-domains = <&pd_gsc>;
1047                         clock-names = "sysmmu", "master";
1048                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
1049                         #iommu-cells = <0>;
1050                 };
1051
1052                 sysmmu_gsc3: sysmmu@13eb0000 {
1053                         compatible = "samsung,exynos-sysmmu";
1054                         reg = <0x13eb0000 0x1000>;
1055                         interrupt-parent = <&combiner>;
1056                         interrupts = <2 6>;
1057                         power-domains = <&pd_gsc>;
1058                         clock-names = "sysmmu", "master";
1059                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
1060                         #iommu-cells = <0>;
1061                 };
1062
1063                 sysmmu_fimd1: sysmmu@14640000 {
1064                         compatible = "samsung,exynos-sysmmu";
1065                         reg = <0x14640000 0x1000>;
1066                         interrupt-parent = <&combiner>;
1067                         interrupts = <3 2>;
1068                         power-domains = <&pd_disp1>;
1069                         clock-names = "sysmmu", "master";
1070                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
1071                         #iommu-cells = <0>;
1072                 };
1073
1074                 sysmmu_tv: sysmmu@14650000 {
1075                         compatible = "samsung,exynos-sysmmu";
1076                         reg = <0x14650000 0x1000>;
1077                         interrupt-parent = <&combiner>;
1078                         interrupts = <7 4>;
1079                         power-domains = <&pd_disp1>;
1080                         clock-names = "sysmmu", "master";
1081                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
1082                         #iommu-cells = <0>;
1083                 };
1084         };
1085
1086         timer {
1087                 compatible = "arm,armv7-timer";
1088                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1089                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1090                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1091                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1092                 /*
1093                  * Unfortunately we need this since some versions
1094                  * of U-Boot on Exynos don't set the CNTFRQ register,
1095                  * so we need the value from DT.
1096                  */
1097                 clock-frequency = <24000000>;
1098         };
1099 };
1100
1101 &cpu_thermal {
1102         polling-delay-passive = <0>;
1103         polling-delay = <0>;
1104         thermal-sensors = <&tmu>;
1105
1106         cooling-maps {
1107                 map0 {
1108                         /* Corresponds to 800MHz at freq_table */
1109                         cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1110                 };
1111                 map1 {
1112                         /* Corresponds to 200MHz at freq_table */
1113                         cooling-device = <&cpu0 15 15>,
1114                                          <&cpu1 15 15>;
1115                 };
1116         };
1117 };
1118
1119 &dp {
1120         power-domains = <&pd_disp1>;
1121         clocks = <&clock CLK_DP>;
1122         clock-names = "dp";
1123         phys = <&dp_phy>;
1124         phy-names = "dp";
1125 };
1126
1127 &fimd {
1128         power-domains = <&pd_disp1>;
1129         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1130         clock-names = "sclk_fimd", "fimd";
1131         iommus = <&sysmmu_fimd1>;
1132 };
1133
1134 &g2d {
1135         iommus = <&sysmmu_g2d>;
1136         clocks = <&clock CLK_G2D>;
1137         clock-names = "fimg2d";
1138         status = "okay";
1139 };
1140
1141 &i2c_0 {
1142         clocks = <&clock CLK_I2C0>;
1143         clock-names = "i2c";
1144         pinctrl-names = "default";
1145         pinctrl-0 = <&i2c0_bus>;
1146 };
1147
1148 &i2c_1 {
1149         clocks = <&clock CLK_I2C1>;
1150         clock-names = "i2c";
1151         pinctrl-names = "default";
1152         pinctrl-0 = <&i2c1_bus>;
1153 };
1154
1155 &i2c_2 {
1156         clocks = <&clock CLK_I2C2>;
1157         clock-names = "i2c";
1158         pinctrl-names = "default";
1159         pinctrl-0 = <&i2c2_bus>;
1160 };
1161
1162 &i2c_3 {
1163         clocks = <&clock CLK_I2C3>;
1164         clock-names = "i2c";
1165         pinctrl-names = "default";
1166         pinctrl-0 = <&i2c3_bus>;
1167 };
1168
1169 &prng {
1170         clocks = <&clock CLK_SSS>;
1171         clock-names = "secss";
1172 };
1173
1174 &pwm {
1175         clocks = <&clock CLK_PWM>;
1176         clock-names = "timers";
1177 };
1178
1179 &rtc {
1180         clocks = <&clock CLK_RTC>;
1181         clock-names = "rtc";
1182         interrupt-parent = <&pmu_system_controller>;
1183         status = "disabled";
1184 };
1185
1186 &serial_0 {
1187         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1188         clock-names = "uart", "clk_uart_baud0";
1189         dmas = <&pdma0 13>, <&pdma0 14>;
1190         dma-names = "rx", "tx";
1191 };
1192
1193 &serial_1 {
1194         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1195         clock-names = "uart", "clk_uart_baud0";
1196         dmas = <&pdma1 15>, <&pdma1 16>;
1197         dma-names = "rx", "tx";
1198 };
1199
1200 &serial_2 {
1201         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1202         clock-names = "uart", "clk_uart_baud0";
1203         dmas = <&pdma0 15>, <&pdma0 16>;
1204         dma-names = "rx", "tx";
1205 };
1206
1207 &serial_3 {
1208         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1209         clock-names = "uart", "clk_uart_baud0";
1210         dmas = <&pdma1 17>, <&pdma1 18>;
1211         dma-names = "rx", "tx";
1212 };
1213
1214 &sss {
1215         clocks = <&clock CLK_SSS>;
1216         clock-names = "secss";
1217 };
1218
1219 &trng {
1220         clocks = <&clock CLK_SSS>;
1221         clock-names = "secss";
1222 };
1223
1224 #include "exynos5250-pinctrl.dtsi"
1225 #include "exynos-syscon-restart.dtsi"