2 * Samsung's Exynos4x12 SoCs device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "exynos4.dtsi"
21 #include "exynos4x12-pinctrl.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 pinctrl3 = &pinctrl_3;
30 fimc-lite0 = &fimc_lite_0;
31 fimc-lite1 = &fimc_lite_1;
36 compatible = "mmio-sram";
37 reg = <0x02020000 0x40000>;
40 ranges = <0 0x02020000 0x40000>;
43 compatible = "samsung,exynos4210-sysram";
48 compatible = "samsung,exynos4210-sysram-ns";
49 reg = <0x2f000 0x1000>;
53 pd_isp: isp-power-domain@10023CA0 {
54 compatible = "samsung,exynos4210-pd";
55 reg = <0x10023CA0 0x20>;
56 #power-domain-cells = <0>;
59 l2c: l2-cache-controller@10502000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10502000 0x1000>;
64 arm,tag-latency = <2 2 1>;
65 arm,data-latency = <3 2 1>;
66 arm,double-linefill = <1>;
67 arm,double-linefill-incr = <0>;
68 arm,double-linefill-wrap = <1>;
69 arm,prefetch-drop = <1>;
70 arm,prefetch-offset = <7>;
73 clock: clock-controller@10030000 {
74 compatible = "samsung,exynos4412-clock";
75 reg = <0x10030000 0x20000>;
80 compatible = "samsung,exynos4412-mct";
81 reg = <0x10050000 0x800>;
82 interrupt-parent = <&mct_map>;
83 interrupts = <0>, <1>, <2>, <3>, <4>;
84 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
85 clock-names = "fin_pll", "mct";
88 #interrupt-cells = <1>;
91 interrupt-map = <0 &gic 0 57 0>,
100 compatible = "samsung,exynos-adc-v1";
101 reg = <0x126C0000 0x100>;
102 interrupt-parent = <&combiner>;
104 clocks = <&clock CLK_TSADC>;
106 #io-channel-cells = <1>;
108 samsung,syscon-phandle = <&pmu_system_controller>;
113 compatible = "samsung,exynos4212-g2d";
114 reg = <0x10800000 0x1000>;
115 interrupts = <0 89 0>;
116 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
117 clock-names = "sclk_fimg2d", "fimg2d";
118 iommus = <&sysmmu_g2d>;
122 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
123 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
124 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
126 /* fimc_[0-3] are configured outside, under phandles */
127 fimc_lite_0: fimc-lite@12390000 {
128 compatible = "samsung,exynos4212-fimc-lite";
129 reg = <0x12390000 0x1000>;
130 interrupts = <0 105 0>;
131 power-domains = <&pd_isp>;
132 clocks = <&clock CLK_FIMC_LITE0>;
133 clock-names = "flite";
134 iommus = <&sysmmu_fimc_lite0>;
138 fimc_lite_1: fimc-lite@123A0000 {
139 compatible = "samsung,exynos4212-fimc-lite";
140 reg = <0x123A0000 0x1000>;
141 interrupts = <0 106 0>;
142 power-domains = <&pd_isp>;
143 clocks = <&clock CLK_FIMC_LITE1>;
144 clock-names = "flite";
145 iommus = <&sysmmu_fimc_lite1>;
149 fimc_is: fimc-is@12000000 {
150 compatible = "samsung,exynos4212-fimc-is", "simple-bus";
151 reg = <0x12000000 0x260000>;
152 interrupts = <0 90 0>, <0 95 0>;
153 power-domains = <&pd_isp>;
154 clocks = <&clock CLK_FIMC_LITE0>,
155 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
156 <&clock CLK_PPMUISPMX>,
157 <&clock CLK_MOUT_MPLL_USER_T>,
158 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
159 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
160 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
161 <&clock CLK_DIV_MCUISP0>,
162 <&clock CLK_DIV_MCUISP1>,
163 <&clock CLK_UART_ISP_SCLK>,
164 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
165 <&clock CLK_ACLK400_MCUISP>,
166 <&clock CLK_DIV_ACLK400_MCUISP>;
167 clock-names = "lite0", "lite1", "ppmuispx",
168 "ppmuispmx", "mpll", "isp",
169 "drc", "fd", "mcuisp",
170 "ispdiv0", "ispdiv1", "mcuispdiv0",
171 "mcuispdiv1", "uart", "aclk200",
172 "div_aclk200", "aclk400mcuisp",
174 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
175 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
176 iommu-names = "isp", "drc", "fd", "mcuctl";
177 #address-cells = <1>;
183 reg = <0x10020000 0x3000>;
186 i2c1_isp: i2c-isp@12140000 {
187 compatible = "samsung,exynos4212-i2c-isp";
188 reg = <0x12140000 0x100>;
189 clocks = <&clock CLK_I2C1_ISP>;
190 clock-names = "i2c_isp";
191 #address-cells = <1>;
197 mshc_0: mmc@12550000 {
198 compatible = "samsung,exynos4412-dw-mshc";
199 reg = <0x12550000 0x1000>;
200 interrupts = <0 77 0>;
201 #address-cells = <1>;
204 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
205 clock-names = "biu", "ciu";
209 sysmmu_g2d: sysmmu@10A40000{
210 compatible = "samsung,exynos-sysmmu";
211 reg = <0x10A40000 0x1000>;
212 interrupt-parent = <&combiner>;
214 clock-names = "sysmmu", "master";
215 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
219 sysmmu_fimc_isp: sysmmu@12260000 {
220 compatible = "samsung,exynos-sysmmu";
221 reg = <0x12260000 0x1000>;
222 interrupt-parent = <&combiner>;
224 power-domains = <&pd_isp>;
225 clock-names = "sysmmu";
226 clocks = <&clock CLK_SMMU_ISP>;
230 sysmmu_fimc_drc: sysmmu@12270000 {
231 compatible = "samsung,exynos-sysmmu";
232 reg = <0x12270000 0x1000>;
233 interrupt-parent = <&combiner>;
235 power-domains = <&pd_isp>;
236 clock-names = "sysmmu";
237 clocks = <&clock CLK_SMMU_DRC>;
241 sysmmu_fimc_fd: sysmmu@122A0000 {
242 compatible = "samsung,exynos-sysmmu";
243 reg = <0x122A0000 0x1000>;
244 interrupt-parent = <&combiner>;
246 power-domains = <&pd_isp>;
247 clock-names = "sysmmu";
248 clocks = <&clock CLK_SMMU_FD>;
252 sysmmu_fimc_mcuctl: sysmmu@122B0000 {
253 compatible = "samsung,exynos-sysmmu";
254 reg = <0x122B0000 0x1000>;
255 interrupt-parent = <&combiner>;
257 power-domains = <&pd_isp>;
258 clock-names = "sysmmu";
259 clocks = <&clock CLK_SMMU_ISPCX>;
263 sysmmu_fimc_lite0: sysmmu@123B0000 {
264 compatible = "samsung,exynos-sysmmu";
265 reg = <0x123B0000 0x1000>;
266 interrupt-parent = <&combiner>;
268 power-domains = <&pd_isp>;
269 clock-names = "sysmmu", "master";
270 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
274 sysmmu_fimc_lite1: sysmmu@123C0000 {
275 compatible = "samsung,exynos-sysmmu";
276 reg = <0x123C0000 0x1000>;
277 interrupt-parent = <&combiner>;
279 power-domains = <&pd_isp>;
280 clock-names = "sysmmu", "master";
281 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
286 compatible = "samsung,exynos-bus";
287 clocks = <&clock CLK_DIV_DMC>;
289 operating-points-v2 = <&bus_dmc_opp_table>;
294 compatible = "samsung,exynos-bus";
295 clocks = <&clock CLK_DIV_ACP>;
297 operating-points-v2 = <&bus_acp_opp_table>;
302 compatible = "samsung,exynos-bus";
303 clocks = <&clock CLK_DIV_C2C>;
305 operating-points-v2 = <&bus_dmc_opp_table>;
309 bus_dmc_opp_table: opp_table1 {
310 compatible = "operating-points-v2";
314 opp-hz = /bits/ 64 <100000000>;
315 opp-microvolt = <900000>;
318 opp-hz = /bits/ 64 <134000000>;
319 opp-microvolt = <900000>;
322 opp-hz = /bits/ 64 <160000000>;
323 opp-microvolt = <900000>;
326 opp-hz = /bits/ 64 <267000000>;
327 opp-microvolt = <950000>;
330 opp-hz = /bits/ 64 <400000000>;
331 opp-microvolt = <1050000>;
335 bus_acp_opp_table: opp_table2 {
336 compatible = "operating-points-v2";
340 opp-hz = /bits/ 64 <100000000>;
343 opp-hz = /bits/ 64 <134000000>;
346 opp-hz = /bits/ 64 <160000000>;
349 opp-hz = /bits/ 64 <267000000>;
353 bus_leftbus: bus_leftbus {
354 compatible = "samsung,exynos-bus";
355 clocks = <&clock CLK_DIV_GDL>;
357 operating-points-v2 = <&bus_leftbus_opp_table>;
361 bus_rightbus: bus_rightbus {
362 compatible = "samsung,exynos-bus";
363 clocks = <&clock CLK_DIV_GDR>;
365 operating-points-v2 = <&bus_leftbus_opp_table>;
369 bus_display: bus_display {
370 compatible = "samsung,exynos-bus";
371 clocks = <&clock CLK_ACLK160>;
373 operating-points-v2 = <&bus_display_opp_table>;
378 compatible = "samsung,exynos-bus";
379 clocks = <&clock CLK_ACLK133>;
381 operating-points-v2 = <&bus_fsys_opp_table>;
386 compatible = "samsung,exynos-bus";
387 clocks = <&clock CLK_ACLK100>;
389 operating-points-v2 = <&bus_peri_opp_table>;
394 compatible = "samsung,exynos-bus";
395 clocks = <&clock CLK_SCLK_MFC>;
397 operating-points-v2 = <&bus_leftbus_opp_table>;
401 bus_leftbus_opp_table: opp_table3 {
402 compatible = "operating-points-v2";
406 opp-hz = /bits/ 64 <100000000>;
407 opp-microvolt = <900000>;
410 opp-hz = /bits/ 64 <134000000>;
411 opp-microvolt = <925000>;
414 opp-hz = /bits/ 64 <160000000>;
415 opp-microvolt = <950000>;
418 opp-hz = /bits/ 64 <200000000>;
419 opp-microvolt = <1000000>;
423 bus_display_opp_table: opp_table4 {
424 compatible = "operating-points-v2";
428 opp-hz = /bits/ 64 <160000000>;
431 opp-hz = /bits/ 64 <200000000>;
435 bus_fsys_opp_table: opp_table5 {
436 compatible = "operating-points-v2";
440 opp-hz = /bits/ 64 <100000000>;
443 opp-hz = /bits/ 64 <134000000>;
447 bus_peri_opp_table: opp_table6 {
448 compatible = "operating-points-v2";
452 opp-hz = /bits/ 64 <50000000>;
455 opp-hz = /bits/ 64 <100000000>;
461 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
462 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
463 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
464 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
465 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
469 compatible = "samsung,exynos4x12-usb2-phy";
470 samsung,sysreg-phandle = <&sys_reg>;
474 compatible = "samsung,exynos4212-fimc";
475 samsung,pix-limits = <4224 8192 1920 4224>;
476 samsung,mainscaler-ext;
482 compatible = "samsung,exynos4212-fimc";
483 samsung,pix-limits = <4224 8192 1920 4224>;
484 samsung,mainscaler-ext;
490 compatible = "samsung,exynos4212-fimc";
491 samsung,pix-limits = <4224 8192 1920 4224>;
492 samsung,mainscaler-ext;
499 compatible = "samsung,exynos4212-fimc";
500 samsung,pix-limits = <1920 8192 1366 1920>;
501 samsung,rotators = <0>;
502 samsung,mainscaler-ext;
508 compatible = "samsung,exynos4212-hdmi";
512 compatible = "samsung,exynos4212-jpeg";
516 compatible = "samsung,exynos4212-rotator";
520 compatible = "samsung,exynos4212-mixer";
521 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
522 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
523 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
527 compatible = "samsung,exynos4x12-pinctrl";
528 reg = <0x11400000 0x1000>;
529 interrupts = <0 47 0>;
533 compatible = "samsung,exynos4x12-pinctrl";
534 reg = <0x11000000 0x1000>;
535 interrupts = <0 46 0>;
537 wakup_eint: wakeup-interrupt-controller {
538 compatible = "samsung,exynos4210-wakeup-eint";
539 interrupt-parent = <&gic>;
540 interrupts = <0 32 0>;
545 compatible = "samsung,exynos4x12-pinctrl";
546 reg = <0x03860000 0x1000>;
547 interrupt-parent = <&combiner>;
552 compatible = "samsung,exynos4x12-pinctrl";
553 reg = <0x106E0000 0x1000>;
554 interrupts = <0 72 0>;
557 &pmu_system_controller {
558 compatible = "samsung,exynos4212-pmu", "syscon";
559 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
560 "clkout4", "clkout8", "clkout9";
561 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
562 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
563 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
568 compatible = "samsung,exynos4412-tmu";
569 interrupt-parent = <&combiner>;
571 reg = <0x100C0000 0x100>;
572 clocks = <&clock 383>;
573 clock-names = "tmu_apbif";