arch/arm/boot/dts/exynos4412.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos4412 SoC device tree source
   4  *
   5  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
   9  * based board files can include this file and provide values for board specfic
  10  * bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
  14  * nodes can be added to this file.
  15  */
  16
  17 #include "exynos4.dtsi"
  18
  19 #include "exynos4-cpu-thermal.dtsi"
  20
  21 / {
  22         compatible = "samsung,exynos4412", "samsung,exynos4";
  23
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 fimc-lite0 = &fimc_lite_0;
  30                 fimc-lite1 = &fimc_lite_1;
  31                 mshc0 = &mshc_0;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@a00 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a9";
  41                         reg = <0xA00>;
  42                         clocks = <&clock CLK_ARM_CLK>;
  43                         clock-names = "cpu";
  44                         operating-points-v2 = <&cpu0_opp_table>;
  45                         #cooling-cells = <2>; /* min followed by max */
  46                 };
  47
  48                 cpu1: cpu@a01 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a9";
  51                         reg = <0xA01>;
  52                         clocks = <&clock CLK_ARM_CLK>;
  53                         clock-names = "cpu";
  54                         operating-points-v2 = <&cpu0_opp_table>;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                 };
  57
  58                 cpu2: cpu@a02 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a9";
  61                         reg = <0xA02>;
  62                         clocks = <&clock CLK_ARM_CLK>;
  63                         clock-names = "cpu";
  64                         operating-points-v2 = <&cpu0_opp_table>;
  65                         #cooling-cells = <2>; /* min followed by max */
  66                 };
  67
  68                 cpu3: cpu@a03 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a9";
  71                         reg = <0xA03>;
  72                         clocks = <&clock CLK_ARM_CLK>;
  73                         clock-names = "cpu";
  74                         operating-points-v2 = <&cpu0_opp_table>;
  75                         #cooling-cells = <2>; /* min followed by max */
  76                 };
  77         };
  78
  79         cpu0_opp_table: opp-table0 {
  80                 compatible = "operating-points-v2";
  81                 opp-shared;
  82
  83                 opp-200000000 {
  84                         opp-hz = /bits/ 64 <200000000>;
  85                         opp-microvolt = <900000>;
  86                         clock-latency-ns = <200000>;
  87                 };
  88                 opp-300000000 {
  89                         opp-hz = /bits/ 64 <300000000>;
  90                         opp-microvolt = <900000>;
  91                         clock-latency-ns = <200000>;
  92                 };
  93                 opp-400000000 {
  94                         opp-hz = /bits/ 64 <400000000>;
  95                         opp-microvolt = <925000>;
  96                         clock-latency-ns = <200000>;
  97                 };
  98                 opp-500000000 {
  99                         opp-hz = /bits/ 64 <500000000>;
 100                         opp-microvolt = <950000>;
 101                         clock-latency-ns = <200000>;
 102                 };
 103                 opp-600000000 {
 104                         opp-hz = /bits/ 64 <600000000>;
 105                         opp-microvolt = <975000>;
 106                         clock-latency-ns = <200000>;
 107                 };
 108                 opp-700000000 {
 109                         opp-hz = /bits/ 64 <700000000>;
 110                         opp-microvolt = <987500>;
 111                         clock-latency-ns = <200000>;
 112                 };
 113                 opp-800000000 {
 114                         opp-hz = /bits/ 64 <800000000>;
 115                         opp-microvolt = <1000000>;
 116                         clock-latency-ns = <200000>;
 117                         opp-suspend;
 118                 };
 119                 opp-900000000 {
 120                         opp-hz = /bits/ 64 <900000000>;
 121                         opp-microvolt = <1037500>;
 122                         clock-latency-ns = <200000>;
 123                 };
 124                 opp-1000000000 {
 125                         opp-hz = /bits/ 64 <1000000000>;
 126                         opp-microvolt = <1087500>;
 127                         clock-latency-ns = <200000>;
 128                 };
 129                 opp-1100000000 {
 130                         opp-hz = /bits/ 64 <1100000000>;
 131                         opp-microvolt = <1137500>;
 132                         clock-latency-ns = <200000>;
 133                 };
 134                 opp-1200000000 {
 135                         opp-hz = /bits/ 64 <1200000000>;
 136                         opp-microvolt = <1187500>;
 137                         clock-latency-ns = <200000>;
 138                 };
 139                 opp-1300000000 {
 140                         opp-hz = /bits/ 64 <1300000000>;
 141                         opp-microvolt = <1250000>;
 142                         clock-latency-ns = <200000>;
 143                 };
 144                 opp-1400000000 {
 145                         opp-hz = /bits/ 64 <1400000000>;
 146                         opp-microvolt = <1287500>;
 147                         clock-latency-ns = <200000>;
 148                 };
 149                 cpu0_opp_1500: opp-1500000000 {
 150                         opp-hz = /bits/ 64 <1500000000>;
 151                         opp-microvolt = <1350000>;
 152                         clock-latency-ns = <200000>;
 153                         turbo-mode;
 154                 };
 155         };
 156
 157
 158         soc: soc {
 159
 160                 pinctrl_0: pinctrl@11400000 {
 161                         compatible = "samsung,exynos4x12-pinctrl";
 162                         reg = <0x11400000 0x1000>;
 163                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 164                 };
 165
 166                 pinctrl_1: pinctrl@11000000 {
 167                         compatible = "samsung,exynos4x12-pinctrl";
 168                         reg = <0x11000000 0x1000>;
 169                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 170
 171                         wakup_eint: wakeup-interrupt-controller {
 172                                 compatible = "samsung,exynos4210-wakeup-eint";
 173                                 interrupt-parent = <&gic>;
 174                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 175                         };
 176                 };
 177
 178                 pinctrl_2: pinctrl@3860000 {
 179                         compatible = "samsung,exynos4x12-pinctrl";
 180                         reg = <0x03860000 0x1000>;
 181                         interrupt-parent = <&combiner>;
 182                         interrupts = <10 0>;
 183                 };
 184
 185                 pinctrl_3: pinctrl@106e0000 {
 186                         compatible = "samsung,exynos4x12-pinctrl";
 187                         reg = <0x106E0000 0x1000>;
 188                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 189                 };
 190
 191                 sram@2020000 {
 192                         compatible = "mmio-sram";
 193                         reg = <0x02020000 0x40000>;
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         ranges = <0 0x02020000 0x40000>;
 197
 198                         smp-sram@0 {
 199                                 compatible = "samsung,exynos4210-sysram";
 200                                 reg = <0x0 0x1000>;
 201                         };
 202
 203                         smp-sram@2f000 {
 204                                 compatible = "samsung,exynos4210-sysram-ns";
 205                                 reg = <0x2f000 0x1000>;
 206                         };
 207                 };
 208
 209                 pd_isp: power-domain@10023ca0 {
 210                         compatible = "samsung,exynos4210-pd";
 211                         reg = <0x10023CA0 0x20>;
 212                         #power-domain-cells = <0>;
 213                         label = "ISP";
 214                 };
 215
 216                 l2c: cache-controller@10502000 {
 217                         compatible = "arm,pl310-cache";
 218                         reg = <0x10502000 0x1000>;
 219                         cache-unified;
 220                         cache-level = <2>;
 221                         prefetch-data = <1>;
 222                         prefetch-instr = <1>;
 223                         arm,tag-latency = <2 2 1>;
 224                         arm,data-latency = <3 2 1>;
 225                         arm,double-linefill = <1>;
 226                         arm,double-linefill-incr = <0>;
 227                         arm,double-linefill-wrap = <1>;
 228                         arm,prefetch-drop = <1>;
 229                         arm,prefetch-offset = <7>;
 230                 };
 231
 232                 clock: clock-controller@10030000 {
 233                         compatible = "samsung,exynos4412-clock";
 234                         reg = <0x10030000 0x18000>;
 235                         #clock-cells = <1>;
 236                 };
 237
 238                 isp_clock: clock-controller@10048000 {
 239                         compatible = "samsung,exynos4412-isp-clock";
 240                         reg = <0x10048000 0x1000>;
 241                         #clock-cells = <1>;
 242                         power-domains = <&pd_isp>;
 243                         clocks = <&clock CLK_ACLK200>,
 244                                  <&clock CLK_ACLK400_MCUISP>;
 245                         clock-names = "aclk200", "aclk400_mcuisp";
 246                 };
 247
 248                 timer@10050000 {
 249                         compatible = "samsung,exynos4412-mct";
 250                         reg = <0x10050000 0x800>;
 251                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 252                         clock-names = "fin_pll", "mct";
 253                         interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 254                                               <&combiner 12 5>,
 255                                               <&combiner 12 6>,
 256                                               <&combiner 12 7>,
 257                                               <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
 258                 };
 259
 260                 watchdog: watchdog@10060000 {
 261                         compatible = "samsung,exynos5250-wdt";
 262                         reg = <0x10060000 0x100>;
 263                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&clock CLK_WDT>;
 265                         clock-names = "watchdog";
 266                         samsung,syscon-phandle = <&pmu_system_controller>;
 267                 };
 268
 269                 adc: adc@126c0000 {
 270                         compatible = "samsung,exynos4212-adc";
 271                         reg = <0x126C0000 0x100>;
 272                         interrupt-parent = <&combiner>;
 273                         interrupts = <10 3>;
 274                         clocks = <&clock CLK_TSADC>;
 275                         clock-names = "adc";
 276                         #io-channel-cells = <1>;
 277                         io-channel-ranges;
 278                         samsung,syscon-phandle = <&pmu_system_controller>;
 279                         status = "disabled";
 280                 };
 281
 282                 g2d: g2d@10800000 {
 283                         compatible = "samsung,exynos4212-g2d";
 284                         reg = <0x10800000 0x1000>;
 285                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 286                         clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 287                         clock-names = "sclk_fimg2d", "fimg2d";
 288                         iommus = <&sysmmu_g2d>;
 289                 };
 290
 291                 mshc_0: mmc@12550000 {
 292                         compatible = "samsung,exynos4412-dw-mshc";
 293                         reg = <0x12550000 0x1000>;
 294                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         fifo-depth = <0x80>;
 298                         clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 299                         clock-names = "biu", "ciu";
 300                         status = "disabled";
 301                 };
 302
 303                 sysmmu_g2d: sysmmu@10a40000 {
 304                         compatible = "samsung,exynos-sysmmu";
 305                         reg = <0x10A40000 0x1000>;
 306                         interrupt-parent = <&combiner>;
 307                         interrupts = <4 7>;
 308                         clock-names = "sysmmu", "master";
 309                         clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 310                         #iommu-cells = <0>;
 311                 };
 312
 313                 sysmmu_fimc_isp: sysmmu@12260000 {
 314                         compatible = "samsung,exynos-sysmmu";
 315                         reg = <0x12260000 0x1000>;
 316                         interrupt-parent = <&combiner>;
 317                         interrupts = <16 2>;
 318                         power-domains = <&pd_isp>;
 319                         clock-names = "sysmmu";
 320                         clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
 321                         #iommu-cells = <0>;
 322                 };
 323
 324                 sysmmu_fimc_drc: sysmmu@12270000 {
 325                         compatible = "samsung,exynos-sysmmu";
 326                         reg = <0x12270000 0x1000>;
 327                         interrupt-parent = <&combiner>;
 328                         interrupts = <16 3>;
 329                         power-domains = <&pd_isp>;
 330                         clock-names = "sysmmu";
 331                         clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
 332                         #iommu-cells = <0>;
 333                 };
 334
 335                 sysmmu_fimc_fd: sysmmu@122a0000 {
 336                         compatible = "samsung,exynos-sysmmu";
 337                         reg = <0x122A0000 0x1000>;
 338                         interrupt-parent = <&combiner>;
 339                         interrupts = <16 4>;
 340                         power-domains = <&pd_isp>;
 341                         clock-names = "sysmmu";
 342                         clocks = <&isp_clock CLK_ISP_SMMU_FD>;
 343                         #iommu-cells = <0>;
 344                 };
 345
 346                 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
 347                         compatible = "samsung,exynos-sysmmu";
 348                         reg = <0x122B0000 0x1000>;
 349                         interrupt-parent = <&combiner>;
 350                         interrupts = <16 5>;
 351                         power-domains = <&pd_isp>;
 352                         clock-names = "sysmmu";
 353                         clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
 354                         #iommu-cells = <0>;
 355                 };
 356
 357                 sysmmu_fimc_lite0: sysmmu@123b0000 {
 358                         compatible = "samsung,exynos-sysmmu";
 359                         reg = <0x123B0000 0x1000>;
 360                         interrupt-parent = <&combiner>;
 361                         interrupts = <16 0>;
 362                         power-domains = <&pd_isp>;
 363                         clock-names = "sysmmu", "master";
 364                         clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
 365                                  <&isp_clock CLK_ISP_FIMC_LITE0>;
 366                         #iommu-cells = <0>;
 367                 };
 368
 369                 sysmmu_fimc_lite1: sysmmu@123c0000 {
 370                         compatible = "samsung,exynos-sysmmu";
 371                         reg = <0x123C0000 0x1000>;
 372                         interrupt-parent = <&combiner>;
 373                         interrupts = <16 1>;
 374                         power-domains = <&pd_isp>;
 375                         clock-names = "sysmmu", "master";
 376                         clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
 377                                  <&isp_clock CLK_ISP_FIMC_LITE1>;
 378                         #iommu-cells = <0>;
 379                 };
 380
 381                 bus_dmc: bus_dmc {
 382                         compatible = "samsung,exynos-bus";
 383                         clocks = <&clock CLK_DIV_DMC>;
 384                         clock-names = "bus";
 385                         operating-points-v2 = <&bus_dmc_opp_table>;
 386                         status = "disabled";
 387                 };
 388
 389                 bus_acp: bus_acp {
 390                         compatible = "samsung,exynos-bus";
 391                         clocks = <&clock CLK_DIV_ACP>;
 392                         clock-names = "bus";
 393                         operating-points-v2 = <&bus_acp_opp_table>;
 394                         status = "disabled";
 395                 };
 396
 397                 bus_c2c: bus_c2c {
 398                         compatible = "samsung,exynos-bus";
 399                         clocks = <&clock CLK_DIV_C2C>;
 400                         clock-names = "bus";
 401                         operating-points-v2 = <&bus_dmc_opp_table>;
 402                         status = "disabled";
 403                 };
 404
 405                 bus_dmc_opp_table: opp-table1 {
 406                         compatible = "operating-points-v2";
 407                         opp-shared;
 408
 409                         opp-100000000 {
 410                                 opp-hz = /bits/ 64 <100000000>;
 411                                 opp-microvolt = <900000>;
 412                         };
 413                         opp-134000000 {
 414                                 opp-hz = /bits/ 64 <134000000>;
 415                                 opp-microvolt = <900000>;
 416                         };
 417                         opp-160000000 {
 418                                 opp-hz = /bits/ 64 <160000000>;
 419                                 opp-microvolt = <900000>;
 420                         };
 421                         opp-267000000 {
 422                                 opp-hz = /bits/ 64 <267000000>;
 423                                 opp-microvolt = <950000>;
 424                         };
 425                         opp-400000000 {
 426                                 opp-hz = /bits/ 64 <400000000>;
 427                                 opp-microvolt = <1050000>;
 428                                 opp-suspend;
 429                         };
 430                 };
 431
 432                 bus_acp_opp_table: opp-table2 {
 433                         compatible = "operating-points-v2";
 434                         opp-shared;
 435
 436                         opp-100000000 {
 437                                 opp-hz = /bits/ 64 <100000000>;
 438                         };
 439                         opp-134000000 {
 440                                 opp-hz = /bits/ 64 <134000000>;
 441                         };
 442                         opp-160000000 {
 443                                 opp-hz = /bits/ 64 <160000000>;
 444                         };
 445                         opp-267000000 {
 446                                 opp-hz = /bits/ 64 <267000000>;
 447                         };
 448                 };
 449
 450                 bus_leftbus: bus_leftbus {
 451                         compatible = "samsung,exynos-bus";
 452                         clocks = <&clock CLK_DIV_GDL>;
 453                         clock-names = "bus";
 454                         operating-points-v2 = <&bus_leftbus_opp_table>;
 455                         status = "disabled";
 456                 };
 457
 458                 bus_rightbus: bus_rightbus {
 459                         compatible = "samsung,exynos-bus";
 460                         clocks = <&clock CLK_DIV_GDR>;
 461                         clock-names = "bus";
 462                         operating-points-v2 = <&bus_leftbus_opp_table>;
 463                         status = "disabled";
 464                 };
 465
 466                 bus_display: bus_display {
 467                         compatible = "samsung,exynos-bus";
 468                         clocks = <&clock CLK_ACLK160>;
 469                         clock-names = "bus";
 470                         operating-points-v2 = <&bus_display_opp_table>;
 471                         status = "disabled";
 472                 };
 473
 474                 bus_fsys: bus_fsys {
 475                         compatible = "samsung,exynos-bus";
 476                         clocks = <&clock CLK_ACLK133>;
 477                         clock-names = "bus";
 478                         operating-points-v2 = <&bus_fsys_opp_table>;
 479                         status = "disabled";
 480                 };
 481
 482                 bus_peri: bus_peri {
 483                         compatible = "samsung,exynos-bus";
 484                         clocks = <&clock CLK_ACLK100>;
 485                         clock-names = "bus";
 486                         operating-points-v2 = <&bus_peri_opp_table>;
 487                         status = "disabled";
 488                 };
 489
 490                 bus_mfc: bus_mfc {
 491                         compatible = "samsung,exynos-bus";
 492                         clocks = <&clock CLK_SCLK_MFC>;
 493                         clock-names = "bus";
 494                         operating-points-v2 = <&bus_leftbus_opp_table>;
 495                         status = "disabled";
 496                 };
 497
 498                 bus_leftbus_opp_table: opp-table3 {
 499                         compatible = "operating-points-v2";
 500                         opp-shared;
 501
 502                         opp-100000000 {
 503                                 opp-hz = /bits/ 64 <100000000>;
 504                                 opp-microvolt = <900000>;
 505                         };
 506                         opp-134000000 {
 507                                 opp-hz = /bits/ 64 <134000000>;
 508                                 opp-microvolt = <925000>;
 509                         };
 510                         opp-160000000 {
 511                                 opp-hz = /bits/ 64 <160000000>;
 512                                 opp-microvolt = <950000>;
 513                         };
 514                         opp-200000000 {
 515                                 opp-hz = /bits/ 64 <200000000>;
 516                                 opp-microvolt = <1000000>;
 517                                 opp-suspend;
 518                         };
 519                 };
 520
 521                 bus_display_opp_table: opp-table4 {
 522                         compatible = "operating-points-v2";
 523                         opp-shared;
 524
 525                         opp-160000000 {
 526                                 opp-hz = /bits/ 64 <160000000>;
 527                         };
 528                         opp-200000000 {
 529                                 opp-hz = /bits/ 64 <200000000>;
 530                         };
 531                 };
 532
 533                 bus_fsys_opp_table: opp-table5 {
 534                         compatible = "operating-points-v2";
 535                         opp-shared;
 536
 537                         opp-100000000 {
 538                                 opp-hz = /bits/ 64 <100000000>;
 539                         };
 540                         opp-134000000 {
 541                                 opp-hz = /bits/ 64 <134000000>;
 542                         };
 543                 };
 544
 545                 bus_peri_opp_table: opp-table6 {
 546                         compatible = "operating-points-v2";
 547                         opp-shared;
 548
 549                         opp-50000000 {
 550                                 opp-hz = /bits/ 64 <50000000>;
 551                         };
 552                         opp-100000000 {
 553                                 opp-hz = /bits/ 64 <100000000>;
 554                         };
 555                 };
 556         };
 557 };
 558
 559 &combiner {
 560         samsung,combiner-nr = <20>;
 561         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 562                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 563                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 564                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 565                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 566                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 567                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 568                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 569                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 570                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 571                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 572                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 573                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 574                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 575                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 576                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 577                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 578                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 579                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 580                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 581 };
 582
 583 &camera {
 584         clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 585                  <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 586         clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 587
 588         /* fimc_[0-3] are configured outside, under phandles */
 589         fimc_lite_0: fimc-lite@12390000 {
 590                 compatible = "samsung,exynos4212-fimc-lite";
 591                 reg = <0x12390000 0x1000>;
 592                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 593                 power-domains = <&pd_isp>;
 594                 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
 595                 clock-names = "flite";
 596                 iommus = <&sysmmu_fimc_lite0>;
 597                 status = "disabled";
 598         };
 599
 600         fimc_lite_1: fimc-lite@123a0000 {
 601                 compatible = "samsung,exynos4212-fimc-lite";
 602                 reg = <0x123A0000 0x1000>;
 603                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 604                 power-domains = <&pd_isp>;
 605                 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
 606                 clock-names = "flite";
 607                 iommus = <&sysmmu_fimc_lite1>;
 608                 status = "disabled";
 609         };
 610
 611         fimc_is: fimc-is@12000000 {
 612                 compatible = "samsung,exynos4212-fimc-is";
 613                 reg = <0x12000000 0x260000>;
 614                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 615                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 616                 power-domains = <&pd_isp>;
 617                 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
 618                          <&isp_clock CLK_ISP_FIMC_LITE1>,
 619                          <&isp_clock CLK_ISP_PPMUISPX>,
 620                          <&isp_clock CLK_ISP_PPMUISPMX>,
 621                          <&isp_clock CLK_ISP_FIMC_ISP>,
 622                          <&isp_clock CLK_ISP_FIMC_DRC>,
 623                          <&isp_clock CLK_ISP_FIMC_FD>,
 624                          <&isp_clock CLK_ISP_MCUISP>,
 625                          <&isp_clock CLK_ISP_GICISP>,
 626                          <&isp_clock CLK_ISP_MCUCTL_ISP>,
 627                          <&isp_clock CLK_ISP_PWM_ISP>,
 628                          <&isp_clock CLK_ISP_DIV_ISP0>,
 629                          <&isp_clock CLK_ISP_DIV_ISP1>,
 630                          <&isp_clock CLK_ISP_DIV_MCUISP0>,
 631                          <&isp_clock CLK_ISP_DIV_MCUISP1>,
 632                          <&clock CLK_MOUT_MPLL_USER_T>,
 633                          <&clock CLK_ACLK200>,
 634                          <&clock CLK_ACLK400_MCUISP>,
 635                          <&clock CLK_DIV_ACLK200>,
 636                          <&clock CLK_DIV_ACLK400_MCUISP>,
 637                          <&clock CLK_UART_ISP_SCLK>;
 638                 clock-names = "lite0", "lite1", "ppmuispx",
 639                               "ppmuispmx", "isp",
 640                               "drc", "fd", "mcuisp",
 641                               "gicisp", "mcuctl_isp", "pwm_isp",
 642                               "ispdiv0", "ispdiv1", "mcuispdiv0",
 643                               "mcuispdiv1", "mpll", "aclk200",
 644                               "aclk400mcuisp", "div_aclk200",
 645                               "div_aclk400mcuisp", "uart";
 646                 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
 647                          <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
 648                 iommu-names = "isp", "drc", "fd", "mcuctl";
 649                 #address-cells = <1>;
 650                 #size-cells = <1>;
 651                 ranges;
 652                 status = "disabled";
 653
 654                 pmu@10020000 {
 655                         reg = <0x10020000 0x3000>;
 656                 };
 657
 658                 i2c1_isp: i2c-isp@12140000 {
 659                         compatible = "samsung,exynos4212-i2c-isp";
 660                         reg = <0x12140000 0x100>;
 661                         clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
 662                         clock-names = "i2c_isp";
 663                         #address-cells = <1>;
 664                         #size-cells = <0>;
 665                 };
 666         };
 667 };
 668
 669 &exynos_usbphy {
 670         compatible = "samsung,exynos4x12-usb2-phy";
 671         samsung,sysreg-phandle = <&sys_reg>;
 672 };
 673
 674 &fimc_0 {
 675         compatible = "samsung,exynos4212-fimc";
 676         samsung,pix-limits = <4224 8192 1920 4224>;
 677         samsung,mainscaler-ext;
 678         samsung,isp-wb;
 679         samsung,cam-if;
 680 };
 681
 682 &fimc_1 {
 683         compatible = "samsung,exynos4212-fimc";
 684         samsung,pix-limits = <4224 8192 1920 4224>;
 685         samsung,mainscaler-ext;
 686         samsung,isp-wb;
 687         samsung,cam-if;
 688 };
 689
 690 &fimc_2 {
 691         compatible = "samsung,exynos4212-fimc";
 692         samsung,pix-limits = <4224 8192 1920 4224>;
 693         samsung,mainscaler-ext;
 694         samsung,isp-wb;
 695         samsung,lcd-wb;
 696         samsung,cam-if;
 697 };
 698
 699 &fimc_3 {
 700         compatible = "samsung,exynos4212-fimc";
 701         samsung,pix-limits = <1920 8192 1366 1920>;
 702         samsung,rotators = <0>;
 703         samsung,mainscaler-ext;
 704         samsung,isp-wb;
 705         samsung,lcd-wb;
 706 };
 707
 708 &gic {
 709         cpu-offset = <0x4000>;
 710 };
 711
 712 &gpu {
 713         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 714                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 715                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 716                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 717                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 718                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 719                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 720                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 721                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 722                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 723                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 724         interrupt-names = "gp",
 725                           "gpmmu",
 726                           "pp0",
 727                           "ppmmu0",
 728                           "pp1",
 729                           "ppmmu1",
 730                           "pp2",
 731                           "ppmmu2",
 732                           "pp3",
 733                           "ppmmu3",
 734                           "pmu";
 735         operating-points-v2 = <&gpu_opp_table>;
 736
 737         gpu_opp_table: opp-table {
 738                 compatible = "operating-points-v2";
 739
 740                 opp-160000000 {
 741                         opp-hz = /bits/ 64 <160000000>;
 742                         opp-microvolt = <875000>;
 743                 };
 744                 opp-267000000 {
 745                         opp-hz = /bits/ 64 <267000000>;
 746                         opp-microvolt = <900000>;
 747                 };
 748                 opp-350000000 {
 749                         opp-hz = /bits/ 64 <350000000>;
 750                         opp-microvolt = <950000>;
 751                 };
 752                 opp-440000000 {
 753                         opp-hz = /bits/ 64 <440000000>;
 754                         opp-microvolt = <1025000>;
 755                 };
 756         };
 757 };
 758
 759 &hdmi {
 760         compatible = "samsung,exynos4212-hdmi";
 761 };
 762
 763 &jpeg_codec {
 764         compatible = "samsung,exynos4212-jpeg";
 765 };
 766
 767 &rotator {
 768         compatible = "samsung,exynos4212-rotator";
 769 };
 770
 771 &mixer {
 772         compatible = "samsung,exynos4212-mixer";
 773         clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
 774         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 775                  <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
 776 };
 777
 778 &pmu {
 779         interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
 780         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 781         status = "okay";
 782 };
 783
 784 &pmu_system_controller {
 785         compatible = "samsung,exynos4412-pmu", "syscon";
 786         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 787                         "clkout4", "clkout8", "clkout9";
 788         clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 789                 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 790                 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
 791         #clock-cells = <1>;
 792 };
 793
 794 &tmu {
 795         compatible = "samsung,exynos4412-tmu";
 796         interrupt-parent = <&combiner>;
 797         interrupts = <2 4>;
 798         reg = <0x100C0000 0x100>;
 799         clocks = <&clock 383>;
 800         clock-names = "tmu_apbif";
 801         status = "disabled";
 802 };
 803
 804 #include "exynos4412-pinctrl.dtsi"