1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoC device tree source
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
17 #include "exynos4.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
22 compatible = "samsung,exynos4412", "samsung,exynos4";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
40 compatible = "arm,cortex-a9";
42 clocks = <&clock CLK_ARM_CLK>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
50 compatible = "arm,cortex-a9";
52 clocks = <&clock CLK_ARM_CLK>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
60 compatible = "arm,cortex-a9";
62 clocks = <&clock CLK_ARM_CLK>;
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
70 compatible = "arm,cortex-a9";
72 clocks = <&clock CLK_ARM_CLK>;
74 operating-points-v2 = <&cpu0_opp_table>;
75 #cooling-cells = <2>; /* min followed by max */
79 cpu0_opp_table: opp-table0 {
80 compatible = "operating-points-v2";
84 opp-hz = /bits/ 64 <200000000>;
85 opp-microvolt = <900000>;
86 clock-latency-ns = <200000>;
89 opp-hz = /bits/ 64 <300000000>;
90 opp-microvolt = <900000>;
91 clock-latency-ns = <200000>;
94 opp-hz = /bits/ 64 <400000000>;
95 opp-microvolt = <925000>;
96 clock-latency-ns = <200000>;
99 opp-hz = /bits/ 64 <500000000>;
100 opp-microvolt = <950000>;
101 clock-latency-ns = <200000>;
104 opp-hz = /bits/ 64 <600000000>;
105 opp-microvolt = <975000>;
106 clock-latency-ns = <200000>;
109 opp-hz = /bits/ 64 <700000000>;
110 opp-microvolt = <987500>;
111 clock-latency-ns = <200000>;
114 opp-hz = /bits/ 64 <800000000>;
115 opp-microvolt = <1000000>;
116 clock-latency-ns = <200000>;
120 opp-hz = /bits/ 64 <900000000>;
121 opp-microvolt = <1037500>;
122 clock-latency-ns = <200000>;
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1087500>;
127 clock-latency-ns = <200000>;
130 opp-hz = /bits/ 64 <1100000000>;
131 opp-microvolt = <1137500>;
132 clock-latency-ns = <200000>;
135 opp-hz = /bits/ 64 <1200000000>;
136 opp-microvolt = <1187500>;
137 clock-latency-ns = <200000>;
140 opp-hz = /bits/ 64 <1300000000>;
141 opp-microvolt = <1250000>;
142 clock-latency-ns = <200000>;
145 opp-hz = /bits/ 64 <1400000000>;
146 opp-microvolt = <1287500>;
147 clock-latency-ns = <200000>;
149 cpu0_opp_1500: opp-1500000000 {
150 opp-hz = /bits/ 64 <1500000000>;
151 opp-microvolt = <1350000>;
152 clock-latency-ns = <200000>;
160 pinctrl_0: pinctrl@11400000 {
161 compatible = "samsung,exynos4x12-pinctrl";
162 reg = <0x11400000 0x1000>;
163 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
166 pinctrl_1: pinctrl@11000000 {
167 compatible = "samsung,exynos4x12-pinctrl";
168 reg = <0x11000000 0x1000>;
169 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
171 wakup_eint: wakeup-interrupt-controller {
172 compatible = "samsung,exynos4210-wakeup-eint";
173 interrupt-parent = <&gic>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
178 pinctrl_2: pinctrl@3860000 {
179 compatible = "samsung,exynos4x12-pinctrl";
180 reg = <0x03860000 0x1000>;
181 interrupt-parent = <&combiner>;
185 pinctrl_3: pinctrl@106e0000 {
186 compatible = "samsung,exynos4x12-pinctrl";
187 reg = <0x106E0000 0x1000>;
188 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
192 compatible = "mmio-sram";
193 reg = <0x02020000 0x40000>;
194 #address-cells = <1>;
196 ranges = <0 0x02020000 0x40000>;
199 compatible = "samsung,exynos4210-sysram";
204 compatible = "samsung,exynos4210-sysram-ns";
205 reg = <0x2f000 0x1000>;
209 pd_isp: power-domain@10023ca0 {
210 compatible = "samsung,exynos4210-pd";
211 reg = <0x10023CA0 0x20>;
212 #power-domain-cells = <0>;
216 l2c: cache-controller@10502000 {
217 compatible = "arm,pl310-cache";
218 reg = <0x10502000 0x1000>;
222 prefetch-instr = <1>;
223 arm,tag-latency = <2 2 1>;
224 arm,data-latency = <3 2 1>;
225 arm,double-linefill = <1>;
226 arm,double-linefill-incr = <0>;
227 arm,double-linefill-wrap = <1>;
228 arm,prefetch-drop = <1>;
229 arm,prefetch-offset = <7>;
232 clock: clock-controller@10030000 {
233 compatible = "samsung,exynos4412-clock";
234 reg = <0x10030000 0x18000>;
238 isp_clock: clock-controller@10048000 {
239 compatible = "samsung,exynos4412-isp-clock";
240 reg = <0x10048000 0x1000>;
242 power-domains = <&pd_isp>;
243 clocks = <&clock CLK_ACLK200>,
244 <&clock CLK_ACLK400_MCUISP>;
245 clock-names = "aclk200", "aclk400_mcuisp";
249 compatible = "samsung,exynos4412-mct";
250 reg = <0x10050000 0x800>;
251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
252 clock-names = "fin_pll", "mct";
253 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
257 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
260 watchdog: watchdog@10060000 {
261 compatible = "samsung,exynos5250-wdt";
262 reg = <0x10060000 0x100>;
263 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clock CLK_WDT>;
265 clock-names = "watchdog";
266 samsung,syscon-phandle = <&pmu_system_controller>;
270 compatible = "samsung,exynos4212-adc";
271 reg = <0x126C0000 0x100>;
272 interrupt-parent = <&combiner>;
274 clocks = <&clock CLK_TSADC>;
276 #io-channel-cells = <1>;
278 samsung,syscon-phandle = <&pmu_system_controller>;
283 compatible = "samsung,exynos4212-g2d";
284 reg = <0x10800000 0x1000>;
285 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
287 clock-names = "sclk_fimg2d", "fimg2d";
288 iommus = <&sysmmu_g2d>;
291 mshc_0: mmc@12550000 {
292 compatible = "samsung,exynos4412-dw-mshc";
293 reg = <0x12550000 0x1000>;
294 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
295 #address-cells = <1>;
298 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
299 clock-names = "biu", "ciu";
303 sysmmu_g2d: sysmmu@10a40000 {
304 compatible = "samsung,exynos-sysmmu";
305 reg = <0x10A40000 0x1000>;
306 interrupt-parent = <&combiner>;
308 clock-names = "sysmmu", "master";
309 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
313 sysmmu_fimc_isp: sysmmu@12260000 {
314 compatible = "samsung,exynos-sysmmu";
315 reg = <0x12260000 0x1000>;
316 interrupt-parent = <&combiner>;
318 power-domains = <&pd_isp>;
319 clock-names = "sysmmu";
320 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
324 sysmmu_fimc_drc: sysmmu@12270000 {
325 compatible = "samsung,exynos-sysmmu";
326 reg = <0x12270000 0x1000>;
327 interrupt-parent = <&combiner>;
329 power-domains = <&pd_isp>;
330 clock-names = "sysmmu";
331 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
335 sysmmu_fimc_fd: sysmmu@122a0000 {
336 compatible = "samsung,exynos-sysmmu";
337 reg = <0x122A0000 0x1000>;
338 interrupt-parent = <&combiner>;
340 power-domains = <&pd_isp>;
341 clock-names = "sysmmu";
342 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
346 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
347 compatible = "samsung,exynos-sysmmu";
348 reg = <0x122B0000 0x1000>;
349 interrupt-parent = <&combiner>;
351 power-domains = <&pd_isp>;
352 clock-names = "sysmmu";
353 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
357 sysmmu_fimc_lite0: sysmmu@123b0000 {
358 compatible = "samsung,exynos-sysmmu";
359 reg = <0x123B0000 0x1000>;
360 interrupt-parent = <&combiner>;
362 power-domains = <&pd_isp>;
363 clock-names = "sysmmu", "master";
364 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
365 <&isp_clock CLK_ISP_FIMC_LITE0>;
369 sysmmu_fimc_lite1: sysmmu@123c0000 {
370 compatible = "samsung,exynos-sysmmu";
371 reg = <0x123C0000 0x1000>;
372 interrupt-parent = <&combiner>;
374 power-domains = <&pd_isp>;
375 clock-names = "sysmmu", "master";
376 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
377 <&isp_clock CLK_ISP_FIMC_LITE1>;
382 compatible = "samsung,exynos-bus";
383 clocks = <&clock CLK_DIV_DMC>;
385 operating-points-v2 = <&bus_dmc_opp_table>;
390 compatible = "samsung,exynos-bus";
391 clocks = <&clock CLK_DIV_ACP>;
393 operating-points-v2 = <&bus_acp_opp_table>;
398 compatible = "samsung,exynos-bus";
399 clocks = <&clock CLK_DIV_C2C>;
401 operating-points-v2 = <&bus_dmc_opp_table>;
405 bus_dmc_opp_table: opp-table1 {
406 compatible = "operating-points-v2";
410 opp-hz = /bits/ 64 <100000000>;
411 opp-microvolt = <900000>;
414 opp-hz = /bits/ 64 <134000000>;
415 opp-microvolt = <900000>;
418 opp-hz = /bits/ 64 <160000000>;
419 opp-microvolt = <900000>;
422 opp-hz = /bits/ 64 <267000000>;
423 opp-microvolt = <950000>;
426 opp-hz = /bits/ 64 <400000000>;
427 opp-microvolt = <1050000>;
432 bus_acp_opp_table: opp-table2 {
433 compatible = "operating-points-v2";
437 opp-hz = /bits/ 64 <100000000>;
440 opp-hz = /bits/ 64 <134000000>;
443 opp-hz = /bits/ 64 <160000000>;
446 opp-hz = /bits/ 64 <267000000>;
450 bus_leftbus: bus_leftbus {
451 compatible = "samsung,exynos-bus";
452 clocks = <&clock CLK_DIV_GDL>;
454 operating-points-v2 = <&bus_leftbus_opp_table>;
458 bus_rightbus: bus_rightbus {
459 compatible = "samsung,exynos-bus";
460 clocks = <&clock CLK_DIV_GDR>;
462 operating-points-v2 = <&bus_leftbus_opp_table>;
466 bus_display: bus_display {
467 compatible = "samsung,exynos-bus";
468 clocks = <&clock CLK_ACLK160>;
470 operating-points-v2 = <&bus_display_opp_table>;
475 compatible = "samsung,exynos-bus";
476 clocks = <&clock CLK_ACLK133>;
478 operating-points-v2 = <&bus_fsys_opp_table>;
483 compatible = "samsung,exynos-bus";
484 clocks = <&clock CLK_ACLK100>;
486 operating-points-v2 = <&bus_peri_opp_table>;
491 compatible = "samsung,exynos-bus";
492 clocks = <&clock CLK_SCLK_MFC>;
494 operating-points-v2 = <&bus_leftbus_opp_table>;
498 bus_leftbus_opp_table: opp-table3 {
499 compatible = "operating-points-v2";
503 opp-hz = /bits/ 64 <100000000>;
504 opp-microvolt = <900000>;
507 opp-hz = /bits/ 64 <134000000>;
508 opp-microvolt = <925000>;
511 opp-hz = /bits/ 64 <160000000>;
512 opp-microvolt = <950000>;
515 opp-hz = /bits/ 64 <200000000>;
516 opp-microvolt = <1000000>;
521 bus_display_opp_table: opp-table4 {
522 compatible = "operating-points-v2";
526 opp-hz = /bits/ 64 <160000000>;
529 opp-hz = /bits/ 64 <200000000>;
533 bus_fsys_opp_table: opp-table5 {
534 compatible = "operating-points-v2";
538 opp-hz = /bits/ 64 <100000000>;
541 opp-hz = /bits/ 64 <134000000>;
545 bus_peri_opp_table: opp-table6 {
546 compatible = "operating-points-v2";
550 opp-hz = /bits/ 64 <50000000>;
553 opp-hz = /bits/ 64 <100000000>;
560 samsung,combiner-nr = <20>;
561 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
585 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
586 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
588 /* fimc_[0-3] are configured outside, under phandles */
589 fimc_lite_0: fimc-lite@12390000 {
590 compatible = "samsung,exynos4212-fimc-lite";
591 reg = <0x12390000 0x1000>;
592 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
593 power-domains = <&pd_isp>;
594 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
595 clock-names = "flite";
596 iommus = <&sysmmu_fimc_lite0>;
600 fimc_lite_1: fimc-lite@123a0000 {
601 compatible = "samsung,exynos4212-fimc-lite";
602 reg = <0x123A0000 0x1000>;
603 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
604 power-domains = <&pd_isp>;
605 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
606 clock-names = "flite";
607 iommus = <&sysmmu_fimc_lite1>;
611 fimc_is: fimc-is@12000000 {
612 compatible = "samsung,exynos4212-fimc-is";
613 reg = <0x12000000 0x260000>;
614 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
616 power-domains = <&pd_isp>;
617 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
618 <&isp_clock CLK_ISP_FIMC_LITE1>,
619 <&isp_clock CLK_ISP_PPMUISPX>,
620 <&isp_clock CLK_ISP_PPMUISPMX>,
621 <&isp_clock CLK_ISP_FIMC_ISP>,
622 <&isp_clock CLK_ISP_FIMC_DRC>,
623 <&isp_clock CLK_ISP_FIMC_FD>,
624 <&isp_clock CLK_ISP_MCUISP>,
625 <&isp_clock CLK_ISP_GICISP>,
626 <&isp_clock CLK_ISP_MCUCTL_ISP>,
627 <&isp_clock CLK_ISP_PWM_ISP>,
628 <&isp_clock CLK_ISP_DIV_ISP0>,
629 <&isp_clock CLK_ISP_DIV_ISP1>,
630 <&isp_clock CLK_ISP_DIV_MCUISP0>,
631 <&isp_clock CLK_ISP_DIV_MCUISP1>,
632 <&clock CLK_MOUT_MPLL_USER_T>,
633 <&clock CLK_ACLK200>,
634 <&clock CLK_ACLK400_MCUISP>,
635 <&clock CLK_DIV_ACLK200>,
636 <&clock CLK_DIV_ACLK400_MCUISP>,
637 <&clock CLK_UART_ISP_SCLK>;
638 clock-names = "lite0", "lite1", "ppmuispx",
640 "drc", "fd", "mcuisp",
641 "gicisp", "mcuctl_isp", "pwm_isp",
642 "ispdiv0", "ispdiv1", "mcuispdiv0",
643 "mcuispdiv1", "mpll", "aclk200",
644 "aclk400mcuisp", "div_aclk200",
645 "div_aclk400mcuisp", "uart";
646 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
647 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
648 iommu-names = "isp", "drc", "fd", "mcuctl";
649 #address-cells = <1>;
655 reg = <0x10020000 0x3000>;
658 i2c1_isp: i2c-isp@12140000 {
659 compatible = "samsung,exynos4212-i2c-isp";
660 reg = <0x12140000 0x100>;
661 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
662 clock-names = "i2c_isp";
663 #address-cells = <1>;
670 compatible = "samsung,exynos4x12-usb2-phy";
671 samsung,sysreg-phandle = <&sys_reg>;
675 compatible = "samsung,exynos4212-fimc";
676 samsung,pix-limits = <4224 8192 1920 4224>;
677 samsung,mainscaler-ext;
683 compatible = "samsung,exynos4212-fimc";
684 samsung,pix-limits = <4224 8192 1920 4224>;
685 samsung,mainscaler-ext;
691 compatible = "samsung,exynos4212-fimc";
692 samsung,pix-limits = <4224 8192 1920 4224>;
693 samsung,mainscaler-ext;
700 compatible = "samsung,exynos4212-fimc";
701 samsung,pix-limits = <1920 8192 1366 1920>;
702 samsung,rotators = <0>;
703 samsung,mainscaler-ext;
709 cpu-offset = <0x4000>;
713 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "gp",
735 operating-points-v2 = <&gpu_opp_table>;
737 gpu_opp_table: opp-table {
738 compatible = "operating-points-v2";
741 opp-hz = /bits/ 64 <160000000>;
742 opp-microvolt = <875000>;
745 opp-hz = /bits/ 64 <267000000>;
746 opp-microvolt = <900000>;
749 opp-hz = /bits/ 64 <350000000>;
750 opp-microvolt = <950000>;
753 opp-hz = /bits/ 64 <440000000>;
754 opp-microvolt = <1025000>;
760 compatible = "samsung,exynos4212-hdmi";
764 compatible = "samsung,exynos4212-jpeg";
768 compatible = "samsung,exynos4212-rotator";
772 compatible = "samsung,exynos4212-mixer";
773 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
774 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
775 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
779 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
780 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
784 &pmu_system_controller {
785 compatible = "samsung,exynos4412-pmu", "syscon";
786 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
787 "clkout4", "clkout8", "clkout9";
788 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
789 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
790 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
795 compatible = "samsung,exynos4412-tmu";
796 interrupt-parent = <&combiner>;
798 reg = <0x100C0000 0x100>;
799 clocks = <&clock 383>;
800 clock-names = "tmu_apbif";
804 #include "exynos4412-pinctrl.dtsi"