2 * Samsung's Exynos4412 SoC device tree source
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "exynos4.dtsi"
21 #include "exynos4412-pinctrl.dtsi"
22 #include "exynos4-cpu-thermal.dtsi"
25 compatible = "samsung,exynos4412", "samsung,exynos4";
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 pinctrl3 = &pinctrl_3;
32 fimc-lite0 = &fimc_lite_0;
33 fimc-lite1 = &fimc_lite_1;
43 compatible = "arm,cortex-a9";
45 clocks = <&clock CLK_ARM_CLK>;
47 operating-points-v2 = <&cpu0_opp_table>;
48 cooling-min-level = <13>;
49 cooling-max-level = <7>;
50 #cooling-cells = <2>; /* min followed by max */
55 compatible = "arm,cortex-a9";
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a9";
64 operating-points-v2 = <&cpu0_opp_table>;
69 compatible = "arm,cortex-a9";
71 operating-points-v2 = <&cpu0_opp_table>;
75 cpu0_opp_table: opp_table0 {
76 compatible = "operating-points-v2";
80 opp-hz = /bits/ 64 <200000000>;
81 opp-microvolt = <900000>;
82 clock-latency-ns = <200000>;
85 opp-hz = /bits/ 64 <300000000>;
86 opp-microvolt = <900000>;
87 clock-latency-ns = <200000>;
90 opp-hz = /bits/ 64 <400000000>;
91 opp-microvolt = <925000>;
92 clock-latency-ns = <200000>;
95 opp-hz = /bits/ 64 <500000000>;
96 opp-microvolt = <950000>;
97 clock-latency-ns = <200000>;
100 opp-hz = /bits/ 64 <600000000>;
101 opp-microvolt = <975000>;
102 clock-latency-ns = <200000>;
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = <987500>;
107 clock-latency-ns = <200000>;
110 opp-hz = /bits/ 64 <800000000>;
111 opp-microvolt = <1000000>;
112 clock-latency-ns = <200000>;
116 opp-hz = /bits/ 64 <900000000>;
117 opp-microvolt = <1037500>;
118 clock-latency-ns = <200000>;
121 opp-hz = /bits/ 64 <1000000000>;
122 opp-microvolt = <1087500>;
123 clock-latency-ns = <200000>;
126 opp-hz = /bits/ 64 <1100000000>;
127 opp-microvolt = <1137500>;
128 clock-latency-ns = <200000>;
131 opp-hz = /bits/ 64 <1200000000>;
132 opp-microvolt = <1187500>;
133 clock-latency-ns = <200000>;
136 opp-hz = /bits/ 64 <1300000000>;
137 opp-microvolt = <1250000>;
138 clock-latency-ns = <200000>;
141 opp-hz = /bits/ 64 <1400000000>;
142 opp-microvolt = <1287500>;
143 clock-latency-ns = <200000>;
145 cpu0_opp_1500: opp@1500000000 {
146 opp-hz = /bits/ 64 <1500000000>;
147 opp-microvolt = <1350000>;
148 clock-latency-ns = <200000>;
154 compatible = "mmio-sram";
155 reg = <0x02020000 0x40000>;
156 #address-cells = <1>;
158 ranges = <0 0x02020000 0x40000>;
161 compatible = "samsung,exynos4210-sysram";
166 compatible = "samsung,exynos4210-sysram-ns";
167 reg = <0x2f000 0x1000>;
171 pd_isp: isp-power-domain@10023CA0 {
172 compatible = "samsung,exynos4210-pd";
173 reg = <0x10023CA0 0x20>;
174 #power-domain-cells = <0>;
178 l2c: l2-cache-controller@10502000 {
179 compatible = "arm,pl310-cache";
180 reg = <0x10502000 0x1000>;
183 arm,tag-latency = <2 2 1>;
184 arm,data-latency = <3 2 1>;
185 arm,double-linefill = <1>;
186 arm,double-linefill-incr = <0>;
187 arm,double-linefill-wrap = <1>;
188 arm,prefetch-drop = <1>;
189 arm,prefetch-offset = <7>;
192 clock: clock-controller@10030000 {
193 compatible = "samsung,exynos4412-clock";
194 reg = <0x10030000 0x20000>;
199 compatible = "samsung,exynos4412-mct";
200 reg = <0x10050000 0x800>;
201 interrupt-parent = <&mct_map>;
202 interrupts = <0>, <1>, <2>, <3>, <4>;
203 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
204 clock-names = "fin_pll", "mct";
207 #interrupt-cells = <1>;
208 #address-cells = <0>;
210 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
214 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
218 watchdog: watchdog@10060000 {
219 compatible = "samsung,exynos5250-wdt";
220 reg = <0x10060000 0x100>;
221 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&clock CLK_WDT>;
223 clock-names = "watchdog";
224 samsung,syscon-phandle = <&pmu_system_controller>;
228 compatible = "samsung,exynos-adc-v1";
229 reg = <0x126C0000 0x100>;
230 interrupt-parent = <&combiner>;
232 clocks = <&clock CLK_TSADC>;
234 #io-channel-cells = <1>;
236 samsung,syscon-phandle = <&pmu_system_controller>;
241 compatible = "samsung,exynos4212-g2d";
242 reg = <0x10800000 0x1000>;
243 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
245 clock-names = "sclk_fimg2d", "fimg2d";
246 iommus = <&sysmmu_g2d>;
250 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
251 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
252 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
254 /* fimc_[0-3] are configured outside, under phandles */
255 fimc_lite_0: fimc-lite@12390000 {
256 compatible = "samsung,exynos4212-fimc-lite";
257 reg = <0x12390000 0x1000>;
258 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
259 power-domains = <&pd_isp>;
260 clocks = <&clock CLK_FIMC_LITE0>;
261 clock-names = "flite";
262 iommus = <&sysmmu_fimc_lite0>;
266 fimc_lite_1: fimc-lite@123A0000 {
267 compatible = "samsung,exynos4212-fimc-lite";
268 reg = <0x123A0000 0x1000>;
269 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
270 power-domains = <&pd_isp>;
271 clocks = <&clock CLK_FIMC_LITE1>;
272 clock-names = "flite";
273 iommus = <&sysmmu_fimc_lite1>;
277 fimc_is: fimc-is@12000000 {
278 compatible = "samsung,exynos4212-fimc-is";
279 reg = <0x12000000 0x260000>;
280 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
282 power-domains = <&pd_isp>;
283 clocks = <&clock CLK_FIMC_LITE0>,
284 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
285 <&clock CLK_PPMUISPMX>,
286 <&clock CLK_MOUT_MPLL_USER_T>,
287 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
288 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
289 <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
290 <&clock CLK_PWM_ISP>,
291 <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
292 <&clock CLK_DIV_MCUISP0>,
293 <&clock CLK_DIV_MCUISP1>,
294 <&clock CLK_UART_ISP_SCLK>,
295 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
296 <&clock CLK_ACLK400_MCUISP>,
297 <&clock CLK_DIV_ACLK400_MCUISP>;
298 clock-names = "lite0", "lite1", "ppmuispx",
299 "ppmuispmx", "mpll", "isp",
300 "drc", "fd", "mcuisp",
301 "gicisp", "mcuctl_isp", "pwm_isp",
302 "ispdiv0", "ispdiv1", "mcuispdiv0",
303 "mcuispdiv1", "uart", "aclk200",
304 "div_aclk200", "aclk400mcuisp",
306 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
307 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
308 iommu-names = "isp", "drc", "fd", "mcuctl";
309 #address-cells = <1>;
315 reg = <0x10020000 0x3000>;
318 i2c1_isp: i2c-isp@12140000 {
319 compatible = "samsung,exynos4212-i2c-isp";
320 reg = <0x12140000 0x100>;
321 clocks = <&clock CLK_I2C1_ISP>;
322 clock-names = "i2c_isp";
323 #address-cells = <1>;
329 mshc_0: mmc@12550000 {
330 compatible = "samsung,exynos4412-dw-mshc";
331 reg = <0x12550000 0x1000>;
332 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
336 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
337 clock-names = "biu", "ciu";
341 sysmmu_g2d: sysmmu@10A40000{
342 compatible = "samsung,exynos-sysmmu";
343 reg = <0x10A40000 0x1000>;
344 interrupt-parent = <&combiner>;
346 clock-names = "sysmmu", "master";
347 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
351 sysmmu_fimc_isp: sysmmu@12260000 {
352 compatible = "samsung,exynos-sysmmu";
353 reg = <0x12260000 0x1000>;
354 interrupt-parent = <&combiner>;
356 power-domains = <&pd_isp>;
357 clock-names = "sysmmu";
358 clocks = <&clock CLK_SMMU_ISP>;
362 sysmmu_fimc_drc: sysmmu@12270000 {
363 compatible = "samsung,exynos-sysmmu";
364 reg = <0x12270000 0x1000>;
365 interrupt-parent = <&combiner>;
367 power-domains = <&pd_isp>;
368 clock-names = "sysmmu";
369 clocks = <&clock CLK_SMMU_DRC>;
373 sysmmu_fimc_fd: sysmmu@122A0000 {
374 compatible = "samsung,exynos-sysmmu";
375 reg = <0x122A0000 0x1000>;
376 interrupt-parent = <&combiner>;
378 power-domains = <&pd_isp>;
379 clock-names = "sysmmu";
380 clocks = <&clock CLK_SMMU_FD>;
384 sysmmu_fimc_mcuctl: sysmmu@122B0000 {
385 compatible = "samsung,exynos-sysmmu";
386 reg = <0x122B0000 0x1000>;
387 interrupt-parent = <&combiner>;
389 power-domains = <&pd_isp>;
390 clock-names = "sysmmu";
391 clocks = <&clock CLK_SMMU_ISPCX>;
395 sysmmu_fimc_lite0: sysmmu@123B0000 {
396 compatible = "samsung,exynos-sysmmu";
397 reg = <0x123B0000 0x1000>;
398 interrupt-parent = <&combiner>;
400 power-domains = <&pd_isp>;
401 clock-names = "sysmmu", "master";
402 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
406 sysmmu_fimc_lite1: sysmmu@123C0000 {
407 compatible = "samsung,exynos-sysmmu";
408 reg = <0x123C0000 0x1000>;
409 interrupt-parent = <&combiner>;
411 power-domains = <&pd_isp>;
412 clock-names = "sysmmu", "master";
413 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
418 compatible = "samsung,exynos-bus";
419 clocks = <&clock CLK_DIV_DMC>;
421 operating-points-v2 = <&bus_dmc_opp_table>;
426 compatible = "samsung,exynos-bus";
427 clocks = <&clock CLK_DIV_ACP>;
429 operating-points-v2 = <&bus_acp_opp_table>;
434 compatible = "samsung,exynos-bus";
435 clocks = <&clock CLK_DIV_C2C>;
437 operating-points-v2 = <&bus_dmc_opp_table>;
441 bus_dmc_opp_table: opp_table1 {
442 compatible = "operating-points-v2";
446 opp-hz = /bits/ 64 <100000000>;
447 opp-microvolt = <900000>;
450 opp-hz = /bits/ 64 <134000000>;
451 opp-microvolt = <900000>;
454 opp-hz = /bits/ 64 <160000000>;
455 opp-microvolt = <900000>;
458 opp-hz = /bits/ 64 <267000000>;
459 opp-microvolt = <950000>;
462 opp-hz = /bits/ 64 <400000000>;
463 opp-microvolt = <1050000>;
467 bus_acp_opp_table: opp_table2 {
468 compatible = "operating-points-v2";
472 opp-hz = /bits/ 64 <100000000>;
475 opp-hz = /bits/ 64 <134000000>;
478 opp-hz = /bits/ 64 <160000000>;
481 opp-hz = /bits/ 64 <267000000>;
485 bus_leftbus: bus_leftbus {
486 compatible = "samsung,exynos-bus";
487 clocks = <&clock CLK_DIV_GDL>;
489 operating-points-v2 = <&bus_leftbus_opp_table>;
493 bus_rightbus: bus_rightbus {
494 compatible = "samsung,exynos-bus";
495 clocks = <&clock CLK_DIV_GDR>;
497 operating-points-v2 = <&bus_leftbus_opp_table>;
501 bus_display: bus_display {
502 compatible = "samsung,exynos-bus";
503 clocks = <&clock CLK_ACLK160>;
505 operating-points-v2 = <&bus_display_opp_table>;
510 compatible = "samsung,exynos-bus";
511 clocks = <&clock CLK_ACLK133>;
513 operating-points-v2 = <&bus_fsys_opp_table>;
518 compatible = "samsung,exynos-bus";
519 clocks = <&clock CLK_ACLK100>;
521 operating-points-v2 = <&bus_peri_opp_table>;
526 compatible = "samsung,exynos-bus";
527 clocks = <&clock CLK_SCLK_MFC>;
529 operating-points-v2 = <&bus_leftbus_opp_table>;
533 bus_leftbus_opp_table: opp_table3 {
534 compatible = "operating-points-v2";
538 opp-hz = /bits/ 64 <100000000>;
539 opp-microvolt = <900000>;
542 opp-hz = /bits/ 64 <134000000>;
543 opp-microvolt = <925000>;
546 opp-hz = /bits/ 64 <160000000>;
547 opp-microvolt = <950000>;
550 opp-hz = /bits/ 64 <200000000>;
551 opp-microvolt = <1000000>;
555 bus_display_opp_table: opp_table4 {
556 compatible = "operating-points-v2";
560 opp-hz = /bits/ 64 <160000000>;
563 opp-hz = /bits/ 64 <200000000>;
567 bus_fsys_opp_table: opp_table5 {
568 compatible = "operating-points-v2";
572 opp-hz = /bits/ 64 <100000000>;
575 opp-hz = /bits/ 64 <134000000>;
579 bus_peri_opp_table: opp_table6 {
580 compatible = "operating-points-v2";
584 opp-hz = /bits/ 64 <50000000>;
587 opp-hz = /bits/ 64 <100000000>;
592 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
597 samsung,combiner-nr = <20>;
598 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
621 compatible = "samsung,exynos4x12-usb2-phy";
622 samsung,sysreg-phandle = <&sys_reg>;
626 compatible = "samsung,exynos4212-fimc";
627 samsung,pix-limits = <4224 8192 1920 4224>;
628 samsung,mainscaler-ext;
634 compatible = "samsung,exynos4212-fimc";
635 samsung,pix-limits = <4224 8192 1920 4224>;
636 samsung,mainscaler-ext;
642 compatible = "samsung,exynos4212-fimc";
643 samsung,pix-limits = <4224 8192 1920 4224>;
644 samsung,mainscaler-ext;
651 compatible = "samsung,exynos4212-fimc";
652 samsung,pix-limits = <1920 8192 1366 1920>;
653 samsung,rotators = <0>;
654 samsung,mainscaler-ext;
660 cpu-offset = <0x4000>;
664 compatible = "samsung,exynos4212-hdmi";
668 compatible = "samsung,exynos4212-jpeg";
672 compatible = "samsung,exynos4212-rotator";
676 compatible = "samsung,exynos4212-mixer";
677 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
678 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
679 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
683 compatible = "samsung,exynos4x12-pinctrl";
684 reg = <0x11400000 0x1000>;
685 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
689 compatible = "samsung,exynos4x12-pinctrl";
690 reg = <0x11000000 0x1000>;
691 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
693 wakup_eint: wakeup-interrupt-controller {
694 compatible = "samsung,exynos4210-wakeup-eint";
695 interrupt-parent = <&gic>;
696 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
701 compatible = "samsung,exynos4x12-pinctrl";
702 reg = <0x03860000 0x1000>;
703 interrupt-parent = <&combiner>;
708 compatible = "samsung,exynos4x12-pinctrl";
709 reg = <0x106E0000 0x1000>;
710 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
713 &pmu_system_controller {
714 compatible = "samsung,exynos4412-pmu", "syscon";
715 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
716 "clkout4", "clkout8", "clkout9";
717 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
718 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
719 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
724 compatible = "samsung,exynos4412-tmu";
725 interrupt-parent = <&combiner>;
727 reg = <0x100C0000 0x100>;
728 clocks = <&clock 383>;
729 clock-names = "tmu_apbif";