1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4412 SoC device tree source
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
17 #include "exynos4.dtsi"
19 #include "exynos4-cpu-thermal.dtsi"
22 compatible = "samsung,exynos4412", "samsung,exynos4";
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
57 compatible = "arm,cortex-a9";
59 clocks = <&clock CLK_ARM_CLK>;
61 operating-points-v2 = <&cpu0_opp_table>;
62 #cooling-cells = <2>; /* min followed by max */
67 compatible = "arm,cortex-a9";
69 clocks = <&clock CLK_ARM_CLK>;
71 operating-points-v2 = <&cpu0_opp_table>;
72 #cooling-cells = <2>; /* min followed by max */
77 compatible = "arm,cortex-a9";
79 clocks = <&clock CLK_ARM_CLK>;
81 operating-points-v2 = <&cpu0_opp_table>;
82 #cooling-cells = <2>; /* min followed by max */
87 compatible = "arm,cortex-a9";
89 clocks = <&clock CLK_ARM_CLK>;
91 operating-points-v2 = <&cpu0_opp_table>;
92 #cooling-cells = <2>; /* min followed by max */
96 cpu0_opp_table: opp-table-0 {
97 compatible = "operating-points-v2";
101 opp-hz = /bits/ 64 <200000000>;
102 opp-microvolt = <900000>;
103 clock-latency-ns = <200000>;
106 opp-hz = /bits/ 64 <300000000>;
107 opp-microvolt = <900000>;
108 clock-latency-ns = <200000>;
111 opp-hz = /bits/ 64 <400000000>;
112 opp-microvolt = <925000>;
113 clock-latency-ns = <200000>;
116 opp-hz = /bits/ 64 <500000000>;
117 opp-microvolt = <950000>;
118 clock-latency-ns = <200000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <975000>;
123 clock-latency-ns = <200000>;
126 opp-hz = /bits/ 64 <700000000>;
127 opp-microvolt = <987500>;
128 clock-latency-ns = <200000>;
131 opp-hz = /bits/ 64 <800000000>;
132 opp-microvolt = <1000000>;
133 clock-latency-ns = <200000>;
137 opp-hz = /bits/ 64 <900000000>;
138 opp-microvolt = <1037500>;
139 clock-latency-ns = <200000>;
142 opp-hz = /bits/ 64 <1000000000>;
143 opp-microvolt = <1087500>;
144 clock-latency-ns = <200000>;
147 opp-hz = /bits/ 64 <1100000000>;
148 opp-microvolt = <1137500>;
149 clock-latency-ns = <200000>;
152 opp-hz = /bits/ 64 <1200000000>;
153 opp-microvolt = <1187500>;
154 clock-latency-ns = <200000>;
157 opp-hz = /bits/ 64 <1300000000>;
158 opp-microvolt = <1250000>;
159 clock-latency-ns = <200000>;
162 opp-hz = /bits/ 64 <1400000000>;
163 opp-microvolt = <1287500>;
164 clock-latency-ns = <200000>;
166 cpu0_opp_1500: opp-1500000000 {
167 opp-hz = /bits/ 64 <1500000000>;
168 opp-microvolt = <1350000>;
169 clock-latency-ns = <200000>;
177 pinctrl_0: pinctrl@11400000 {
178 compatible = "samsung,exynos4x12-pinctrl";
179 reg = <0x11400000 0x1000>;
180 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
183 pinctrl_1: pinctrl@11000000 {
184 compatible = "samsung,exynos4x12-pinctrl";
185 reg = <0x11000000 0x1000>;
186 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
188 wakup_eint: wakeup-interrupt-controller {
189 compatible = "samsung,exynos4210-wakeup-eint";
190 interrupt-parent = <&gic>;
191 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
195 pinctrl_2: pinctrl@3860000 {
196 compatible = "samsung,exynos4x12-pinctrl";
197 reg = <0x03860000 0x1000>;
198 interrupt-parent = <&combiner>;
202 pinctrl_3: pinctrl@106e0000 {
203 compatible = "samsung,exynos4x12-pinctrl";
204 reg = <0x106e0000 0x1000>;
205 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
209 compatible = "mmio-sram";
210 reg = <0x02020000 0x40000>;
211 #address-cells = <1>;
213 ranges = <0 0x02020000 0x40000>;
216 compatible = "samsung,exynos4210-sysram";
221 compatible = "samsung,exynos4210-sysram-ns";
222 reg = <0x2f000 0x1000>;
226 pd_isp: power-domain@10023ca0 {
227 compatible = "samsung,exynos4210-pd";
228 reg = <0x10023ca0 0x20>;
229 #power-domain-cells = <0>;
233 l2c: cache-controller@10502000 {
234 compatible = "arm,pl310-cache";
235 reg = <0x10502000 0x1000>;
239 prefetch-instr = <1>;
240 arm,tag-latency = <2 2 1>;
241 arm,data-latency = <3 2 1>;
242 arm,double-linefill = <1>;
243 arm,double-linefill-incr = <0>;
244 arm,double-linefill-wrap = <1>;
245 arm,prefetch-drop = <1>;
246 arm,prefetch-offset = <7>;
249 clock: clock-controller@10030000 {
250 compatible = "samsung,exynos4412-clock";
251 reg = <0x10030000 0x18000>;
255 isp_clock: clock-controller@10048000 {
256 compatible = "samsung,exynos4412-isp-clock";
257 reg = <0x10048000 0x1000>;
259 power-domains = <&pd_isp>;
260 clocks = <&clock CLK_ACLK200>,
261 <&clock CLK_ACLK400_MCUISP>;
262 clock-names = "aclk200", "aclk400_mcuisp";
266 compatible = "samsung,exynos4412-mct";
267 reg = <0x10050000 0x800>;
268 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
269 clock-names = "fin_pll", "mct";
270 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
274 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
277 watchdog: watchdog@10060000 {
278 compatible = "samsung,exynos5250-wdt";
279 reg = <0x10060000 0x100>;
280 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clock CLK_WDT>;
282 clock-names = "watchdog";
283 samsung,syscon-phandle = <&pmu_system_controller>;
287 compatible = "samsung,exynos4212-adc";
288 reg = <0x126c0000 0x100>;
289 interrupt-parent = <&combiner>;
291 clocks = <&clock CLK_TSADC>;
293 #io-channel-cells = <1>;
294 samsung,syscon-phandle = <&pmu_system_controller>;
299 compatible = "samsung,exynos4212-g2d";
300 reg = <0x10800000 0x1000>;
301 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
303 clock-names = "sclk_fimg2d", "fimg2d";
304 iommus = <&sysmmu_g2d>;
307 mshc_0: mmc@12550000 {
308 compatible = "samsung,exynos4412-dw-mshc";
309 reg = <0x12550000 0x1000>;
310 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
311 #address-cells = <1>;
314 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
315 clock-names = "biu", "ciu";
319 sysmmu_g2d: sysmmu@10a40000 {
320 compatible = "samsung,exynos-sysmmu";
321 reg = <0x10a40000 0x1000>;
322 interrupt-parent = <&combiner>;
324 clock-names = "sysmmu", "master";
325 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
329 sysmmu_fimc_isp: sysmmu@12260000 {
330 compatible = "samsung,exynos-sysmmu";
331 reg = <0x12260000 0x1000>;
332 interrupt-parent = <&combiner>;
334 power-domains = <&pd_isp>;
335 clock-names = "sysmmu";
336 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
340 sysmmu_fimc_drc: sysmmu@12270000 {
341 compatible = "samsung,exynos-sysmmu";
342 reg = <0x12270000 0x1000>;
343 interrupt-parent = <&combiner>;
345 power-domains = <&pd_isp>;
346 clock-names = "sysmmu";
347 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
351 sysmmu_fimc_fd: sysmmu@122a0000 {
352 compatible = "samsung,exynos-sysmmu";
353 reg = <0x122a0000 0x1000>;
354 interrupt-parent = <&combiner>;
356 power-domains = <&pd_isp>;
357 clock-names = "sysmmu";
358 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
362 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
363 compatible = "samsung,exynos-sysmmu";
364 reg = <0x122b0000 0x1000>;
365 interrupt-parent = <&combiner>;
367 power-domains = <&pd_isp>;
368 clock-names = "sysmmu";
369 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
373 sysmmu_fimc_lite0: sysmmu@123b0000 {
374 compatible = "samsung,exynos-sysmmu";
375 reg = <0x123b0000 0x1000>;
376 interrupt-parent = <&combiner>;
378 power-domains = <&pd_isp>;
379 clock-names = "sysmmu", "master";
380 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
381 <&isp_clock CLK_ISP_FIMC_LITE0>;
385 sysmmu_fimc_lite1: sysmmu@123c0000 {
386 compatible = "samsung,exynos-sysmmu";
387 reg = <0x123c0000 0x1000>;
388 interrupt-parent = <&combiner>;
390 power-domains = <&pd_isp>;
391 clock-names = "sysmmu", "master";
392 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
393 <&isp_clock CLK_ISP_FIMC_LITE1>;
398 compatible = "samsung,exynos-bus";
399 clocks = <&clock CLK_DIV_DMC>;
401 operating-points-v2 = <&bus_dmc_opp_table>;
402 samsung,data-clock-ratio = <4>;
403 #interconnect-cells = <0>;
408 compatible = "samsung,exynos-bus";
409 clocks = <&clock CLK_DIV_ACP>;
411 operating-points-v2 = <&bus_acp_opp_table>;
416 compatible = "samsung,exynos-bus";
417 clocks = <&clock CLK_DIV_C2C>;
419 operating-points-v2 = <&bus_dmc_opp_table>;
423 bus_dmc_opp_table: opp-table-1 {
424 compatible = "operating-points-v2";
427 opp-hz = /bits/ 64 <100000000>;
428 opp-microvolt = <900000>;
431 opp-hz = /bits/ 64 <134000000>;
432 opp-microvolt = <900000>;
435 opp-hz = /bits/ 64 <160000000>;
436 opp-microvolt = <900000>;
439 opp-hz = /bits/ 64 <267000000>;
440 opp-microvolt = <950000>;
443 opp-hz = /bits/ 64 <400000000>;
444 opp-microvolt = <1050000>;
449 bus_acp_opp_table: opp-table-2 {
450 compatible = "operating-points-v2";
453 opp-hz = /bits/ 64 <100000000>;
456 opp-hz = /bits/ 64 <134000000>;
459 opp-hz = /bits/ 64 <160000000>;
462 opp-hz = /bits/ 64 <267000000>;
466 bus_leftbus: bus-leftbus {
467 compatible = "samsung,exynos-bus";
468 clocks = <&clock CLK_DIV_GDL>;
470 operating-points-v2 = <&bus_leftbus_opp_table>;
471 interconnects = <&bus_dmc>;
472 #interconnect-cells = <0>;
476 bus_rightbus: bus-rightbus {
477 compatible = "samsung,exynos-bus";
478 clocks = <&clock CLK_DIV_GDR>;
480 operating-points-v2 = <&bus_leftbus_opp_table>;
484 bus_display: bus-display {
485 compatible = "samsung,exynos-bus";
486 clocks = <&clock CLK_ACLK160>;
488 operating-points-v2 = <&bus_display_opp_table>;
489 interconnects = <&bus_leftbus &bus_dmc>;
490 #interconnect-cells = <0>;
495 compatible = "samsung,exynos-bus";
496 clocks = <&clock CLK_ACLK133>;
498 operating-points-v2 = <&bus_fsys_opp_table>;
503 compatible = "samsung,exynos-bus";
504 clocks = <&clock CLK_ACLK100>;
506 operating-points-v2 = <&bus_peri_opp_table>;
511 compatible = "samsung,exynos-bus";
512 clocks = <&clock CLK_SCLK_MFC>;
514 operating-points-v2 = <&bus_leftbus_opp_table>;
518 bus_leftbus_opp_table: opp-table-3 {
519 compatible = "operating-points-v2";
522 opp-hz = /bits/ 64 <100000000>;
523 opp-microvolt = <900000>;
526 opp-hz = /bits/ 64 <134000000>;
527 opp-microvolt = <925000>;
530 opp-hz = /bits/ 64 <160000000>;
531 opp-microvolt = <950000>;
534 opp-hz = /bits/ 64 <200000000>;
535 opp-microvolt = <1000000>;
540 bus_display_opp_table: opp-table-4 {
541 compatible = "operating-points-v2";
544 opp-hz = /bits/ 64 <160000000>;
547 opp-hz = /bits/ 64 <200000000>;
551 bus_fsys_opp_table: opp-table-5 {
552 compatible = "operating-points-v2";
555 opp-hz = /bits/ 64 <100000000>;
558 opp-hz = /bits/ 64 <134000000>;
562 bus_peri_opp_table: opp-table-6 {
563 compatible = "operating-points-v2";
566 opp-hz = /bits/ 64 <50000000>;
569 opp-hz = /bits/ 64 <100000000>;
576 samsung,combiner-nr = <20>;
577 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
601 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
602 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
604 /* fimc_[0-3] are configured outside, under phandles */
605 fimc_lite_0: fimc-lite@12390000 {
606 compatible = "samsung,exynos4212-fimc-lite";
607 reg = <0x12390000 0x1000>;
608 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
609 power-domains = <&pd_isp>;
610 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
611 clock-names = "flite";
612 iommus = <&sysmmu_fimc_lite0>;
616 fimc_lite_1: fimc-lite@123a0000 {
617 compatible = "samsung,exynos4212-fimc-lite";
618 reg = <0x123a0000 0x1000>;
619 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
620 power-domains = <&pd_isp>;
621 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
622 clock-names = "flite";
623 iommus = <&sysmmu_fimc_lite1>;
627 fimc_is: fimc-is@12000000 {
628 compatible = "samsung,exynos4212-fimc-is";
629 reg = <0x12000000 0x260000>;
630 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
632 power-domains = <&pd_isp>;
633 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
634 <&isp_clock CLK_ISP_FIMC_LITE1>,
635 <&isp_clock CLK_ISP_PPMUISPX>,
636 <&isp_clock CLK_ISP_PPMUISPMX>,
637 <&isp_clock CLK_ISP_FIMC_ISP>,
638 <&isp_clock CLK_ISP_FIMC_DRC>,
639 <&isp_clock CLK_ISP_FIMC_FD>,
640 <&isp_clock CLK_ISP_MCUISP>,
641 <&isp_clock CLK_ISP_GICISP>,
642 <&isp_clock CLK_ISP_MCUCTL_ISP>,
643 <&isp_clock CLK_ISP_PWM_ISP>,
644 <&isp_clock CLK_ISP_DIV_ISP0>,
645 <&isp_clock CLK_ISP_DIV_ISP1>,
646 <&isp_clock CLK_ISP_DIV_MCUISP0>,
647 <&isp_clock CLK_ISP_DIV_MCUISP1>,
648 <&clock CLK_MOUT_MPLL_USER_T>,
649 <&clock CLK_ACLK200>,
650 <&clock CLK_ACLK400_MCUISP>,
651 <&clock CLK_DIV_ACLK200>,
652 <&clock CLK_DIV_ACLK400_MCUISP>,
653 <&clock CLK_UART_ISP_SCLK>;
654 clock-names = "lite0", "lite1", "ppmuispx",
656 "drc", "fd", "mcuisp",
657 "gicisp", "mcuctl_isp", "pwm_isp",
658 "ispdiv0", "ispdiv1", "mcuispdiv0",
659 "mcuispdiv1", "mpll", "aclk200",
660 "aclk400mcuisp", "div_aclk200",
661 "div_aclk400mcuisp", "uart";
662 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
663 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
664 iommu-names = "isp", "drc", "fd", "mcuctl";
665 #address-cells = <1>;
671 reg = <0x10020000 0x3000>;
674 i2c1_isp: i2c-isp@12140000 {
675 compatible = "samsung,exynos4212-i2c-isp";
676 reg = <0x12140000 0x100>;
677 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
678 clock-names = "i2c_isp";
679 #address-cells = <1>;
686 compatible = "samsung,exynos4x12-usb2-phy";
687 samsung,sysreg-phandle = <&sys_reg>;
691 compatible = "samsung,exynos4212-fimc";
692 samsung,pix-limits = <4224 8192 1920 4224>;
693 samsung,mainscaler-ext;
699 compatible = "samsung,exynos4212-fimc";
700 samsung,pix-limits = <4224 8192 1920 4224>;
701 samsung,mainscaler-ext;
707 compatible = "samsung,exynos4212-fimc";
708 samsung,pix-limits = <4224 8192 1920 4224>;
709 samsung,mainscaler-ext;
716 compatible = "samsung,exynos4212-fimc";
717 samsung,pix-limits = <1920 8192 1366 1920>;
718 samsung,rotators = <0>;
719 samsung,mainscaler-ext;
725 cpu-offset = <0x4000>;
729 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
740 interrupt-names = "gp",
751 operating-points-v2 = <&gpu_opp_table>;
753 gpu_opp_table: opp-table {
754 compatible = "operating-points-v2";
757 opp-hz = /bits/ 64 <160000000>;
758 opp-microvolt = <875000>;
761 opp-hz = /bits/ 64 <267000000>;
762 opp-microvolt = <900000>;
765 opp-hz = /bits/ 64 <350000000>;
766 opp-microvolt = <950000>;
769 opp-hz = /bits/ 64 <440000000>;
770 opp-microvolt = <1025000>;
776 compatible = "samsung,exynos4212-hdmi";
780 compatible = "samsung,exynos4212-jpeg";
784 compatible = "samsung,exynos4212-rotator";
788 compatible = "samsung,exynos4212-mixer";
789 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
790 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
791 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
792 interconnects = <&bus_display &bus_dmc>;
796 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
797 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
801 &pmu_system_controller {
802 compatible = "samsung,exynos4412-pmu", "syscon";
803 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
804 "clkout4", "clkout8", "clkout9";
805 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
806 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
807 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
812 compatible = "samsung,exynos4412-tmu";
813 interrupt-parent = <&combiner>;
815 reg = <0x100c0000 0x100>;
816 clocks = <&clock CLK_TMU_APBIF>;
817 clock-names = "tmu_apbif";
821 #include "exynos4412-pinctrl.dtsi"