arch/arm/boot/dts/exynos4412.dtsi

   1 /*
   2  * Samsung's Exynos4412 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4412-pinctrl.dtsi"
  22 #include "exynos4-cpu-thermal.dtsi"
  23
  24 / {
  25         compatible = "samsung,exynos4412", "samsung,exynos4";
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 fimc-lite0 = &fimc_lite_0;
  33                 fimc-lite1 = &fimc_lite_1;
  34                 mshc0 = &mshc_0;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@A00 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <0xA00>;
  45                         clocks = <&clock CLK_ARM_CLK>;
  46                         clock-names = "cpu";
  47                         operating-points-v2 = <&cpu0_opp_table>;
  48                         cooling-min-level = <13>;
  49                         cooling-max-level = <7>;
  50                         #cooling-cells = <2>; /* min followed by max */
  51                 };
  52
  53                 cpu@A01 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a9";
  56                         reg = <0xA01>;
  57                         operating-points-v2 = <&cpu0_opp_table>;
  58                 };
  59
  60                 cpu@A02 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a9";
  63                         reg = <0xA02>;
  64                         operating-points-v2 = <&cpu0_opp_table>;
  65                 };
  66
  67                 cpu@A03 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a9";
  70                         reg = <0xA03>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73         };
  74
  75         cpu0_opp_table: opp_table0 {
  76                 compatible = "operating-points-v2";
  77                 opp-shared;
  78
  79                 opp@200000000 {
  80                         opp-hz = /bits/ 64 <200000000>;
  81                         opp-microvolt = <900000>;
  82                         clock-latency-ns = <200000>;
  83                 };
  84                 opp@300000000 {
  85                         opp-hz = /bits/ 64 <300000000>;
  86                         opp-microvolt = <900000>;
  87                         clock-latency-ns = <200000>;
  88                 };
  89                 opp@400000000 {
  90                         opp-hz = /bits/ 64 <400000000>;
  91                         opp-microvolt = <925000>;
  92                         clock-latency-ns = <200000>;
  93                 };
  94                 opp@500000000 {
  95                         opp-hz = /bits/ 64 <500000000>;
  96                         opp-microvolt = <950000>;
  97                         clock-latency-ns = <200000>;
  98                 };
  99                 opp@600000000 {
 100                         opp-hz = /bits/ 64 <600000000>;
 101                         opp-microvolt = <975000>;
 102                         clock-latency-ns = <200000>;
 103                 };
 104                 opp@700000000 {
 105                         opp-hz = /bits/ 64 <700000000>;
 106                         opp-microvolt = <987500>;
 107                         clock-latency-ns = <200000>;
 108                 };
 109                 opp@800000000 {
 110                         opp-hz = /bits/ 64 <800000000>;
 111                         opp-microvolt = <1000000>;
 112                         clock-latency-ns = <200000>;
 113                         opp-suspend;
 114                 };
 115                 opp@900000000 {
 116                         opp-hz = /bits/ 64 <900000000>;
 117                         opp-microvolt = <1037500>;
 118                         clock-latency-ns = <200000>;
 119                 };
 120                 opp@1000000000 {
 121                         opp-hz = /bits/ 64 <1000000000>;
 122                         opp-microvolt = <1087500>;
 123                         clock-latency-ns = <200000>;
 124                 };
 125                 opp@1100000000 {
 126                         opp-hz = /bits/ 64 <1100000000>;
 127                         opp-microvolt = <1137500>;
 128                         clock-latency-ns = <200000>;
 129                 };
 130                 opp@1200000000 {
 131                         opp-hz = /bits/ 64 <1200000000>;
 132                         opp-microvolt = <1187500>;
 133                         clock-latency-ns = <200000>;
 134                 };
 135                 opp@1300000000 {
 136                         opp-hz = /bits/ 64 <1300000000>;
 137                         opp-microvolt = <1250000>;
 138                         clock-latency-ns = <200000>;
 139                 };
 140                 opp@1400000000 {
 141                         opp-hz = /bits/ 64 <1400000000>;
 142                         opp-microvolt = <1287500>;
 143                         clock-latency-ns = <200000>;
 144                 };
 145                 cpu0_opp_1500: opp@1500000000 {
 146                         opp-hz = /bits/ 64 <1500000000>;
 147                         opp-microvolt = <1350000>;
 148                         clock-latency-ns = <200000>;
 149                         turbo-mode;
 150                 };
 151         };
 152
 153         sysram@02020000 {
 154                 compatible = "mmio-sram";
 155                 reg = <0x02020000 0x40000>;
 156                 #address-cells = <1>;
 157                 #size-cells = <1>;
 158                 ranges = <0 0x02020000 0x40000>;
 159
 160                 smp-sysram@0 {
 161                         compatible = "samsung,exynos4210-sysram";
 162                         reg = <0x0 0x1000>;
 163                 };
 164
 165                 smp-sysram@2f000 {
 166                         compatible = "samsung,exynos4210-sysram-ns";
 167                         reg = <0x2f000 0x1000>;
 168                 };
 169         };
 170
 171         pd_isp: isp-power-domain@10023CA0 {
 172                 compatible = "samsung,exynos4210-pd";
 173                 reg = <0x10023CA0 0x20>;
 174                 #power-domain-cells = <0>;
 175                 label = "ISP";
 176         };
 177
 178         l2c: l2-cache-controller@10502000 {
 179                 compatible = "arm,pl310-cache";
 180                 reg = <0x10502000 0x1000>;
 181                 cache-unified;
 182                 cache-level = <2>;
 183                 arm,tag-latency = <2 2 1>;
 184                 arm,data-latency = <3 2 1>;
 185                 arm,double-linefill = <1>;
 186                 arm,double-linefill-incr = <0>;
 187                 arm,double-linefill-wrap = <1>;
 188                 arm,prefetch-drop = <1>;
 189                 arm,prefetch-offset = <7>;
 190         };
 191
 192         clock: clock-controller@10030000 {
 193                 compatible = "samsung,exynos4412-clock";
 194                 reg = <0x10030000 0x20000>;
 195                 #clock-cells = <1>;
 196         };
 197
 198         mct@10050000 {
 199                 compatible = "samsung,exynos4412-mct";
 200                 reg = <0x10050000 0x800>;
 201                 interrupt-parent = <&mct_map>;
 202                 interrupts = <0>, <1>, <2>, <3>, <4>;
 203                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 204                 clock-names = "fin_pll", "mct";
 205
 206                 mct_map: mct-map {
 207                         #interrupt-cells = <1>;
 208                         #address-cells = <0>;
 209                         #size-cells = <0>;
 210                         interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
 211                                         <1 &combiner 12 5>,
 212                                         <2 &combiner 12 6>,
 213                                         <3 &combiner 12 7>,
 214                                         <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
 215                 };
 216         };
 217
 218         adc: adc@126C0000 {
 219                 compatible = "samsung,exynos-adc-v1";
 220                 reg = <0x126C0000 0x100>;
 221                 interrupt-parent = <&combiner>;
 222                 interrupts = <10 3>;
 223                 clocks = <&clock CLK_TSADC>;
 224                 clock-names = "adc";
 225                 #io-channel-cells = <1>;
 226                 io-channel-ranges;
 227                 samsung,syscon-phandle = <&pmu_system_controller>;
 228                 status = "disabled";
 229         };
 230
 231         g2d: g2d@10800000 {
 232                 compatible = "samsung,exynos4212-g2d";
 233                 reg = <0x10800000 0x1000>;
 234                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 235                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 236                 clock-names = "sclk_fimg2d", "fimg2d";
 237                 iommus = <&sysmmu_g2d>;
 238         };
 239
 240         camera {
 241                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 242                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 243                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 244
 245                 /* fimc_[0-3] are configured outside, under phandles */
 246                 fimc_lite_0: fimc-lite@12390000 {
 247                         compatible = "samsung,exynos4212-fimc-lite";
 248                         reg = <0x12390000 0x1000>;
 249                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 250                         power-domains = <&pd_isp>;
 251                         clocks = <&clock CLK_FIMC_LITE0>;
 252                         clock-names = "flite";
 253                         iommus = <&sysmmu_fimc_lite0>;
 254                         status = "disabled";
 255                 };
 256
 257                 fimc_lite_1: fimc-lite@123A0000 {
 258                         compatible = "samsung,exynos4212-fimc-lite";
 259                         reg = <0x123A0000 0x1000>;
 260                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 261                         power-domains = <&pd_isp>;
 262                         clocks = <&clock CLK_FIMC_LITE1>;
 263                         clock-names = "flite";
 264                         iommus = <&sysmmu_fimc_lite1>;
 265                         status = "disabled";
 266                 };
 267
 268                 fimc_is: fimc-is@12000000 {
 269                         compatible = "samsung,exynos4212-fimc-is";
 270                         reg = <0x12000000 0x260000>;
 271                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 273                         power-domains = <&pd_isp>;
 274                         clocks = <&clock CLK_FIMC_LITE0>,
 275                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 276                                  <&clock CLK_PPMUISPMX>,
 277                                  <&clock CLK_MOUT_MPLL_USER_T>,
 278                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 279                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 280                                  <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>,
 281                                  <&clock CLK_PWM_ISP>,
 282                                  <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>,
 283                                  <&clock CLK_DIV_MCUISP0>,
 284                                  <&clock CLK_DIV_MCUISP1>,
 285                                  <&clock CLK_UART_ISP_SCLK>,
 286                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 287                                  <&clock CLK_ACLK400_MCUISP>,
 288                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 289                         clock-names = "lite0", "lite1", "ppmuispx",
 290                                       "ppmuispmx", "mpll", "isp",
 291                                       "drc", "fd", "mcuisp",
 292                                       "gicisp", "mcuctl_isp", "pwm_isp",
 293                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 294                                       "mcuispdiv1", "uart", "aclk200",
 295                                       "div_aclk200", "aclk400mcuisp",
 296                                       "div_aclk400mcuisp";
 297                         iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
 298                                  <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
 299                         iommu-names = "isp", "drc", "fd", "mcuctl";
 300                         #address-cells = <1>;
 301                         #size-cells = <1>;
 302                         ranges;
 303                         status = "disabled";
 304
 305                         pmu@10020000 {
 306                                 reg = <0x10020000 0x3000>;
 307                         };
 308
 309                         i2c1_isp: i2c-isp@12140000 {
 310                                 compatible = "samsung,exynos4212-i2c-isp";
 311                                 reg = <0x12140000 0x100>;
 312                                 clocks = <&clock CLK_I2C1_ISP>;
 313                                 clock-names = "i2c_isp";
 314                                 #address-cells = <1>;
 315                                 #size-cells = <0>;
 316                         };
 317                 };
 318         };
 319
 320         mshc_0: mmc@12550000 {
 321                 compatible = "samsung,exynos4412-dw-mshc";
 322                 reg = <0x12550000 0x1000>;
 323                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 fifo-depth = <0x80>;
 327                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 328                 clock-names = "biu", "ciu";
 329                 status = "disabled";
 330         };
 331
 332         sysmmu_g2d: sysmmu@10A40000{
 333                 compatible = "samsung,exynos-sysmmu";
 334                 reg = <0x10A40000 0x1000>;
 335                 interrupt-parent = <&combiner>;
 336                 interrupts = <4 7>;
 337                 clock-names = "sysmmu", "master";
 338                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 339                 #iommu-cells = <0>;
 340         };
 341
 342         sysmmu_fimc_isp: sysmmu@12260000 {
 343                 compatible = "samsung,exynos-sysmmu";
 344                 reg = <0x12260000 0x1000>;
 345                 interrupt-parent = <&combiner>;
 346                 interrupts = <16 2>;
 347                 power-domains = <&pd_isp>;
 348                 clock-names = "sysmmu";
 349                 clocks = <&clock CLK_SMMU_ISP>;
 350                 #iommu-cells = <0>;
 351         };
 352
 353         sysmmu_fimc_drc: sysmmu@12270000 {
 354                 compatible = "samsung,exynos-sysmmu";
 355                 reg = <0x12270000 0x1000>;
 356                 interrupt-parent = <&combiner>;
 357                 interrupts = <16 3>;
 358                 power-domains = <&pd_isp>;
 359                 clock-names = "sysmmu";
 360                 clocks = <&clock CLK_SMMU_DRC>;
 361                 #iommu-cells = <0>;
 362         };
 363
 364         sysmmu_fimc_fd: sysmmu@122A0000 {
 365                 compatible = "samsung,exynos-sysmmu";
 366                 reg = <0x122A0000 0x1000>;
 367                 interrupt-parent = <&combiner>;
 368                 interrupts = <16 4>;
 369                 power-domains = <&pd_isp>;
 370                 clock-names = "sysmmu";
 371                 clocks = <&clock CLK_SMMU_FD>;
 372                 #iommu-cells = <0>;
 373         };
 374
 375         sysmmu_fimc_mcuctl: sysmmu@122B0000 {
 376                 compatible = "samsung,exynos-sysmmu";
 377                 reg = <0x122B0000 0x1000>;
 378                 interrupt-parent = <&combiner>;
 379                 interrupts = <16 5>;
 380                 power-domains = <&pd_isp>;
 381                 clock-names = "sysmmu";
 382                 clocks = <&clock CLK_SMMU_ISPCX>;
 383                 #iommu-cells = <0>;
 384         };
 385
 386         sysmmu_fimc_lite0: sysmmu@123B0000 {
 387                 compatible = "samsung,exynos-sysmmu";
 388                 reg = <0x123B0000 0x1000>;
 389                 interrupt-parent = <&combiner>;
 390                 interrupts = <16 0>;
 391                 power-domains = <&pd_isp>;
 392                 clock-names = "sysmmu", "master";
 393                 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
 394                 #iommu-cells = <0>;
 395         };
 396
 397         sysmmu_fimc_lite1: sysmmu@123C0000 {
 398                 compatible = "samsung,exynos-sysmmu";
 399                 reg = <0x123C0000 0x1000>;
 400                 interrupt-parent = <&combiner>;
 401                 interrupts = <16 1>;
 402                 power-domains = <&pd_isp>;
 403                 clock-names = "sysmmu", "master";
 404                 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
 405                 #iommu-cells = <0>;
 406         };
 407
 408         bus_dmc: bus_dmc {
 409                 compatible = "samsung,exynos-bus";
 410                 clocks = <&clock CLK_DIV_DMC>;
 411                 clock-names = "bus";
 412                 operating-points-v2 = <&bus_dmc_opp_table>;
 413                 status = "disabled";
 414         };
 415
 416         bus_acp: bus_acp {
 417                 compatible = "samsung,exynos-bus";
 418                 clocks = <&clock CLK_DIV_ACP>;
 419                 clock-names = "bus";
 420                 operating-points-v2 = <&bus_acp_opp_table>;
 421                 status = "disabled";
 422         };
 423
 424         bus_c2c: bus_c2c {
 425                 compatible = "samsung,exynos-bus";
 426                 clocks = <&clock CLK_DIV_C2C>;
 427                 clock-names = "bus";
 428                 operating-points-v2 = <&bus_dmc_opp_table>;
 429                 status = "disabled";
 430         };
 431
 432         bus_dmc_opp_table: opp_table1 {
 433                 compatible = "operating-points-v2";
 434                 opp-shared;
 435
 436                 opp@100000000 {
 437                         opp-hz = /bits/ 64 <100000000>;
 438                         opp-microvolt = <900000>;
 439                 };
 440                 opp@134000000 {
 441                         opp-hz = /bits/ 64 <134000000>;
 442                         opp-microvolt = <900000>;
 443                 };
 444                 opp@160000000 {
 445                         opp-hz = /bits/ 64 <160000000>;
 446                         opp-microvolt = <900000>;
 447                 };
 448                 opp@267000000 {
 449                         opp-hz = /bits/ 64 <267000000>;
 450                         opp-microvolt = <950000>;
 451                 };
 452                 opp@400000000 {
 453                         opp-hz = /bits/ 64 <400000000>;
 454                         opp-microvolt = <1050000>;
 455                 };
 456         };
 457
 458         bus_acp_opp_table: opp_table2 {
 459                 compatible = "operating-points-v2";
 460                 opp-shared;
 461
 462                 opp@100000000 {
 463                         opp-hz = /bits/ 64 <100000000>;
 464                 };
 465                 opp@134000000 {
 466                         opp-hz = /bits/ 64 <134000000>;
 467                 };
 468                 opp@160000000 {
 469                         opp-hz = /bits/ 64 <160000000>;
 470                 };
 471                 opp@267000000 {
 472                         opp-hz = /bits/ 64 <267000000>;
 473                 };
 474         };
 475
 476         bus_leftbus: bus_leftbus {
 477                 compatible = "samsung,exynos-bus";
 478                 clocks = <&clock CLK_DIV_GDL>;
 479                 clock-names = "bus";
 480                 operating-points-v2 = <&bus_leftbus_opp_table>;
 481                 status = "disabled";
 482         };
 483
 484         bus_rightbus: bus_rightbus {
 485                 compatible = "samsung,exynos-bus";
 486                 clocks = <&clock CLK_DIV_GDR>;
 487                 clock-names = "bus";
 488                 operating-points-v2 = <&bus_leftbus_opp_table>;
 489                 status = "disabled";
 490         };
 491
 492         bus_display: bus_display {
 493                 compatible = "samsung,exynos-bus";
 494                 clocks = <&clock CLK_ACLK160>;
 495                 clock-names = "bus";
 496                 operating-points-v2 = <&bus_display_opp_table>;
 497                 status = "disabled";
 498         };
 499
 500         bus_fsys: bus_fsys {
 501                 compatible = "samsung,exynos-bus";
 502                 clocks = <&clock CLK_ACLK133>;
 503                 clock-names = "bus";
 504                 operating-points-v2 = <&bus_fsys_opp_table>;
 505                 status = "disabled";
 506         };
 507
 508         bus_peri: bus_peri {
 509                 compatible = "samsung,exynos-bus";
 510                 clocks = <&clock CLK_ACLK100>;
 511                 clock-names = "bus";
 512                 operating-points-v2 = <&bus_peri_opp_table>;
 513                 status = "disabled";
 514         };
 515
 516         bus_mfc: bus_mfc {
 517                 compatible = "samsung,exynos-bus";
 518                 clocks = <&clock CLK_SCLK_MFC>;
 519                 clock-names = "bus";
 520                 operating-points-v2 = <&bus_leftbus_opp_table>;
 521                 status = "disabled";
 522         };
 523
 524         bus_leftbus_opp_table: opp_table3 {
 525                 compatible = "operating-points-v2";
 526                 opp-shared;
 527
 528                 opp@100000000 {
 529                         opp-hz = /bits/ 64 <100000000>;
 530                         opp-microvolt = <900000>;
 531                 };
 532                 opp@134000000 {
 533                         opp-hz = /bits/ 64 <134000000>;
 534                         opp-microvolt = <925000>;
 535                 };
 536                 opp@160000000 {
 537                         opp-hz = /bits/ 64 <160000000>;
 538                         opp-microvolt = <950000>;
 539                 };
 540                 opp@200000000 {
 541                         opp-hz = /bits/ 64 <200000000>;
 542                         opp-microvolt = <1000000>;
 543                 };
 544         };
 545
 546         bus_display_opp_table: opp_table4 {
 547                 compatible = "operating-points-v2";
 548                 opp-shared;
 549
 550                 opp@160000000 {
 551                         opp-hz = /bits/ 64 <160000000>;
 552                 };
 553                 opp@200000000 {
 554                         opp-hz = /bits/ 64 <200000000>;
 555                 };
 556         };
 557
 558         bus_fsys_opp_table: opp_table5 {
 559                 compatible = "operating-points-v2";
 560                 opp-shared;
 561
 562                 opp@100000000 {
 563                         opp-hz = /bits/ 64 <100000000>;
 564                 };
 565                 opp@134000000 {
 566                         opp-hz = /bits/ 64 <134000000>;
 567                 };
 568         };
 569
 570         bus_peri_opp_table: opp_table6 {
 571                 compatible = "operating-points-v2";
 572                 opp-shared;
 573
 574                 opp@50000000 {
 575                         opp-hz = /bits/ 64 <50000000>;
 576                 };
 577                 opp@100000000 {
 578                         opp-hz = /bits/ 64 <100000000>;
 579                 };
 580         };
 581
 582         pmu {
 583                 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
 584         };
 585 };
 586
 587 &combiner {
 588         samsung,combiner-nr = <20>;
 589         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 590                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 591                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 592                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 593                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 594                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 595                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 596                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 597                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 598                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 599                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 600                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 601                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 602                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 603                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 604                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 605                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 606                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 607                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 608                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 609 };
 610
 611 &exynos_usbphy {
 612         compatible = "samsung,exynos4x12-usb2-phy";
 613         samsung,sysreg-phandle = <&sys_reg>;
 614 };
 615
 616 &fimc_0 {
 617         compatible = "samsung,exynos4212-fimc";
 618         samsung,pix-limits = <4224 8192 1920 4224>;
 619         samsung,mainscaler-ext;
 620         samsung,isp-wb;
 621         samsung,cam-if;
 622 };
 623
 624 &fimc_1 {
 625         compatible = "samsung,exynos4212-fimc";
 626         samsung,pix-limits = <4224 8192 1920 4224>;
 627         samsung,mainscaler-ext;
 628         samsung,isp-wb;
 629         samsung,cam-if;
 630 };
 631
 632 &fimc_2 {
 633         compatible = "samsung,exynos4212-fimc";
 634         samsung,pix-limits = <4224 8192 1920 4224>;
 635         samsung,mainscaler-ext;
 636         samsung,isp-wb;
 637         samsung,lcd-wb;
 638         samsung,cam-if;
 639 };
 640
 641 &fimc_3 {
 642         compatible = "samsung,exynos4212-fimc";
 643         samsung,pix-limits = <1920 8192 1366 1920>;
 644         samsung,rotators = <0>;
 645         samsung,mainscaler-ext;
 646         samsung,isp-wb;
 647         samsung,lcd-wb;
 648 };
 649
 650 &gic {
 651         cpu-offset = <0x4000>;
 652 };
 653
 654 &hdmi {
 655         compatible = "samsung,exynos4212-hdmi";
 656 };
 657
 658 &jpeg_codec {
 659         compatible = "samsung,exynos4212-jpeg";
 660 };
 661
 662 &rotator {
 663         compatible = "samsung,exynos4212-rotator";
 664 };
 665
 666 &mixer {
 667         compatible = "samsung,exynos4212-mixer";
 668         clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
 669         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 670                  <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
 671 };
 672
 673 &pinctrl_0 {
 674         compatible = "samsung,exynos4x12-pinctrl";
 675         reg = <0x11400000 0x1000>;
 676         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 677 };
 678
 679 &pinctrl_1 {
 680         compatible = "samsung,exynos4x12-pinctrl";
 681         reg = <0x11000000 0x1000>;
 682         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 683
 684         wakup_eint: wakeup-interrupt-controller {
 685                 compatible = "samsung,exynos4210-wakeup-eint";
 686                 interrupt-parent = <&gic>;
 687                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 688         };
 689 };
 690
 691 &pinctrl_2 {
 692         compatible = "samsung,exynos4x12-pinctrl";
 693         reg = <0x03860000 0x1000>;
 694         interrupt-parent = <&combiner>;
 695         interrupts = <10 0>;
 696 };
 697
 698 &pinctrl_3 {
 699         compatible = "samsung,exynos4x12-pinctrl";
 700         reg = <0x106E0000 0x1000>;
 701         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 702 };
 703
 704 &pmu_system_controller {
 705         compatible = "samsung,exynos4412-pmu", "syscon";
 706         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 707                         "clkout4", "clkout8", "clkout9";
 708         clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 709                 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 710                 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
 711         #clock-cells = <1>;
 712 };
 713
 714 &tmu {
 715         compatible = "samsung,exynos4412-tmu";
 716         interrupt-parent = <&combiner>;
 717         interrupts = <2 4>;
 718         reg = <0x100C0000 0x100>;
 719         clocks = <&clock 383>;
 720         clock-names = "tmu_apbif";
 721         status = "disabled";
 722 };