1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC device tree source
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
19 #include "exynos4.dtsi"
20 #include "exynos4-cpu-thermal.dtsi"
23 compatible = "samsung,exynos4210", "samsung,exynos4";
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
48 compatible = "arm,cortex-a9";
50 clocks = <&clock CLK_ARM_CLK>;
52 clock-latency = <160000>;
62 #cooling-cells = <2>; /* min followed by max */
67 compatible = "arm,cortex-a9";
69 clocks = <&clock CLK_ARM_CLK>;
71 clock-latency = <160000>;
81 #cooling-cells = <2>; /* min followed by max */
86 sysram: sram@2020000 {
87 compatible = "mmio-sram";
88 reg = <0x02020000 0x20000>;
91 ranges = <0 0x02020000 0x20000>;
94 compatible = "samsung,exynos4210-sysram";
99 compatible = "samsung,exynos4210-sysram-ns";
100 reg = <0x1f000 0x1000>;
104 pd_lcd1: power-domain@10023ca0 {
105 compatible = "samsung,exynos4210-pd";
106 reg = <0x10023CA0 0x20>;
107 #power-domain-cells = <0>;
111 l2c: cache-controller@10502000 {
112 compatible = "arm,pl310-cache";
113 reg = <0x10502000 0x1000>;
117 prefetch-instr = <1>;
118 arm,tag-latency = <2 2 1>;
119 arm,data-latency = <2 2 1>;
122 mct: timer@10050000 {
123 compatible = "samsung,exynos4210-mct";
124 reg = <0x10050000 0x800>;
125 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
126 clock-names = "fin_pll", "mct";
127 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
128 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
131 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
132 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
135 watchdog: watchdog@10060000 {
136 compatible = "samsung,s3c6410-wdt";
137 reg = <0x10060000 0x100>;
138 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&clock CLK_WDT>;
140 clock-names = "watchdog";
143 clock: clock-controller@10030000 {
144 compatible = "samsung,exynos4210-clock";
145 reg = <0x10030000 0x20000>;
149 pinctrl_0: pinctrl@11400000 {
150 compatible = "samsung,exynos4210-pinctrl";
151 reg = <0x11400000 0x1000>;
152 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
155 pinctrl_1: pinctrl@11000000 {
156 compatible = "samsung,exynos4210-pinctrl";
157 reg = <0x11000000 0x1000>;
158 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
160 wakup_eint: wakeup-interrupt-controller {
161 compatible = "samsung,exynos4210-wakeup-eint";
162 interrupt-parent = <&gic>;
163 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
167 pinctrl_2: pinctrl@3860000 {
168 compatible = "samsung,exynos4210-pinctrl";
169 reg = <0x03860000 0x1000>;
173 compatible = "samsung,s5pv210-g2d";
174 reg = <0x12800000 0x1000>;
175 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
177 clock-names = "sclk_fimg2d", "fimg2d";
178 power-domains = <&pd_lcd0>;
179 iommus = <&sysmmu_g2d>;
182 ppmu_acp: ppmu@10ae0000 {
183 compatible = "samsung,exynos-ppmu";
184 reg = <0x10ae0000 0x2000>;
188 ppmu_lcd1: ppmu@12240000 {
189 compatible = "samsung,exynos-ppmu";
190 reg = <0x12240000 0x2000>;
191 clocks = <&clock CLK_PPMULCD1>;
192 clock-names = "ppmu";
196 sysmmu_g2d: sysmmu@12a20000 {
197 compatible = "samsung,exynos-sysmmu";
198 reg = <0x12A20000 0x1000>;
199 interrupt-parent = <&combiner>;
201 clock-names = "sysmmu", "master";
202 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
203 power-domains = <&pd_lcd0>;
207 sysmmu_fimd1: sysmmu@12220000 {
208 compatible = "samsung,exynos-sysmmu";
209 interrupt-parent = <&combiner>;
210 reg = <0x12220000 0x1000>;
212 clock-names = "sysmmu", "master";
213 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
214 power-domains = <&pd_lcd1>;
219 compatible = "samsung,exynos-bus";
220 clocks = <&clock CLK_DIV_DMC>;
222 operating-points-v2 = <&bus_dmc_opp_table>;
227 compatible = "samsung,exynos-bus";
228 clocks = <&clock CLK_DIV_ACP>;
230 operating-points-v2 = <&bus_acp_opp_table>;
235 compatible = "samsung,exynos-bus";
236 clocks = <&clock CLK_ACLK100>;
238 operating-points-v2 = <&bus_peri_opp_table>;
243 compatible = "samsung,exynos-bus";
244 clocks = <&clock CLK_ACLK133>;
246 operating-points-v2 = <&bus_fsys_opp_table>;
250 bus_display: bus-display {
251 compatible = "samsung,exynos-bus";
252 clocks = <&clock CLK_ACLK160>;
254 operating-points-v2 = <&bus_display_opp_table>;
259 compatible = "samsung,exynos-bus";
260 clocks = <&clock CLK_ACLK200>;
262 operating-points-v2 = <&bus_leftbus_opp_table>;
266 bus_leftbus: bus-leftbus {
267 compatible = "samsung,exynos-bus";
268 clocks = <&clock CLK_DIV_GDL>;
270 operating-points-v2 = <&bus_leftbus_opp_table>;
274 bus_rightbus: bus-rightbus {
275 compatible = "samsung,exynos-bus";
276 clocks = <&clock CLK_DIV_GDR>;
278 operating-points-v2 = <&bus_leftbus_opp_table>;
283 compatible = "samsung,exynos-bus";
284 clocks = <&clock CLK_SCLK_MFC>;
286 operating-points-v2 = <&bus_leftbus_opp_table>;
290 bus_dmc_opp_table: opp-table1 {
291 compatible = "operating-points-v2";
295 opp-hz = /bits/ 64 <134000000>;
296 opp-microvolt = <1025000>;
299 opp-hz = /bits/ 64 <267000000>;
300 opp-microvolt = <1050000>;
303 opp-hz = /bits/ 64 <400000000>;
304 opp-microvolt = <1150000>;
309 bus_acp_opp_table: opp-table2 {
310 compatible = "operating-points-v2";
314 opp-hz = /bits/ 64 <134000000>;
317 opp-hz = /bits/ 64 <160000000>;
320 opp-hz = /bits/ 64 <200000000>;
324 bus_peri_opp_table: opp-table3 {
325 compatible = "operating-points-v2";
329 opp-hz = /bits/ 64 <5000000>;
332 opp-hz = /bits/ 64 <100000000>;
336 bus_fsys_opp_table: opp-table4 {
337 compatible = "operating-points-v2";
341 opp-hz = /bits/ 64 <10000000>;
344 opp-hz = /bits/ 64 <134000000>;
348 bus_display_opp_table: opp-table5 {
349 compatible = "operating-points-v2";
353 opp-hz = /bits/ 64 <100000000>;
356 opp-hz = /bits/ 64 <134000000>;
359 opp-hz = /bits/ 64 <160000000>;
363 bus_leftbus_opp_table: opp-table6 {
364 compatible = "operating-points-v2";
368 opp-hz = /bits/ 64 <100000000>;
371 opp-hz = /bits/ 64 <160000000>;
374 opp-hz = /bits/ 64 <200000000>;
382 temperature = <85000>; /* millicelsius */
386 temperature = <100000>; /* millicelsius */
390 temperature = <110000>; /* millicelsius */
394 polling-delay-passive = <0>;
396 thermal-sensors = <&tmu 0>;
400 cpu-offset = <0x8000>;
404 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
405 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
406 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
410 samsung,combiner-nr = <16>;
411 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
430 samsung,pix-limits = <4224 8192 1920 4224>;
431 samsung,mainscaler-ext;
436 samsung,pix-limits = <4224 8192 1920 4224>;
437 samsung,mainscaler-ext;
442 samsung,pix-limits = <4224 8192 1920 4224>;
443 samsung,mainscaler-ext;
448 samsung,pix-limits = <1920 8192 1366 1920>;
449 samsung,rotators = <0>;
450 samsung,mainscaler-ext;
455 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "gp",
475 operating-points-v2 = <&gpu_opp_table>;
477 gpu_opp_table: opp-table {
478 compatible = "operating-points-v2";
481 opp-hz = /bits/ 64 <160000000>;
482 opp-microvolt = <950000>;
485 opp-hz = /bits/ 64 <267000000>;
486 opp-microvolt = <1050000>;
492 power-domains = <&pd_lcd0>;
496 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
498 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
499 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
500 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
504 interrupts = <2 2>, <3 2>;
505 interrupt-affinity = <&cpu0>, <&cpu1>;
509 &pmu_system_controller {
510 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
511 "clkout4", "clkout8", "clkout9";
512 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
513 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
514 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
519 power-domains = <&pd_lcd0>;
523 power-domains = <&pd_lcd0>;
527 compatible = "samsung,exynos4210-tmu";
528 clocks = <&clock CLK_TMU_APBIF>;
529 clock-names = "tmu_apbif";
530 samsung,tmu_gain = <15>;
531 samsung,tmu_reference_voltage = <7>;
534 #include "exynos4210-pinctrl.dtsi"