1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos3250 SoC device tree source
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>;
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
50 compatible = "samsung,exynos-bus";
51 clocks = <&cmu_dmc CLK_DIV_DMC>;
53 operating-points-v2 = <&bus_dmc_opp_table>;
56 bus_dmc_opp_table: opp-table {
57 compatible = "operating-points-v2";
60 opp-hz = /bits/ 64 <50000000>;
61 opp-microvolt = <800000>;
64 opp-hz = /bits/ 64 <100000000>;
65 opp-microvolt = <800000>;
68 opp-hz = /bits/ 64 <134000000>;
69 opp-microvolt = <800000>;
72 opp-hz = /bits/ 64 <200000000>;
73 opp-microvolt = <825000>;
76 opp-hz = /bits/ 64 <400000000>;
77 opp-microvolt = <875000>;
83 compatible = "samsung,exynos-bus";
84 clocks = <&cmu CLK_DIV_ACLK_200>;
86 operating-points-v2 = <&bus_leftbus_opp_table>;
91 compatible = "samsung,exynos-bus";
92 clocks = <&cmu CLK_DIV_ACLK_266>;
94 operating-points-v2 = <&bus_isp_opp_table>;
97 bus_isp_opp_table: opp-table {
98 compatible = "operating-points-v2";
101 opp-hz = /bits/ 64 <50000000>;
104 opp-hz = /bits/ 64 <80000000>;
107 opp-hz = /bits/ 64 <100000000>;
110 opp-hz = /bits/ 64 <200000000>;
113 opp-hz = /bits/ 64 <300000000>;
119 compatible = "samsung,exynos-bus";
120 clocks = <&cmu CLK_DIV_ACLK_160>;
122 operating-points-v2 = <&bus_leftbus_opp_table>;
126 bus_leftbus: bus-leftbus {
127 compatible = "samsung,exynos-bus";
128 clocks = <&cmu CLK_DIV_GDL>;
130 operating-points-v2 = <&bus_leftbus_opp_table>;
134 bus_mcuisp: bus-mcuisp {
135 compatible = "samsung,exynos-bus";
136 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
138 operating-points-v2 = <&bus_mcuisp_opp_table>;
141 bus_mcuisp_opp_table: opp-table {
142 compatible = "operating-points-v2";
145 opp-hz = /bits/ 64 <50000000>;
148 opp-hz = /bits/ 64 <80000000>;
151 opp-hz = /bits/ 64 <100000000>;
154 opp-hz = /bits/ 64 <200000000>;
157 opp-hz = /bits/ 64 <400000000>;
163 compatible = "samsung,exynos-bus";
164 clocks = <&cmu CLK_SCLK_MFC>;
166 operating-points-v2 = <&bus_leftbus_opp_table>;
170 bus_peril: bus-peril {
171 compatible = "samsung,exynos-bus";
172 clocks = <&cmu CLK_DIV_ACLK_100>;
174 operating-points-v2 = <&bus_peril_opp_table>;
177 bus_peril_opp_table: opp-table {
178 compatible = "operating-points-v2";
181 opp-hz = /bits/ 64 <50000000>;
184 opp-hz = /bits/ 64 <80000000>;
187 opp-hz = /bits/ 64 <100000000>;
192 bus_rightbus: bus-rightbus {
193 compatible = "samsung,exynos-bus";
194 clocks = <&cmu CLK_DIV_GDR>;
196 operating-points-v2 = <&bus_leftbus_opp_table>;
201 #address-cells = <1>;
217 compatible = "arm,cortex-a7";
219 clock-frequency = <1000000000>;
220 clocks = <&cmu CLK_ARM_CLK>;
222 #cooling-cells = <2>;
240 compatible = "arm,cortex-a7";
242 clock-frequency = <1000000000>;
243 clocks = <&cmu CLK_ARM_CLK>;
245 #cooling-cells = <2>;
263 compatible = "fixed-clock";
264 clock-frequency = <0>;
266 clock-output-names = "xusbxti";
270 compatible = "fixed-clock";
271 clock-frequency = <0>;
273 clock-output-names = "xxti";
277 compatible = "fixed-clock";
278 clock-frequency = <0>;
280 clock-output-names = "xtcxo";
283 bus_leftbus_opp_table: opp-table-0 {
284 compatible = "operating-points-v2";
287 opp-hz = /bits/ 64 <50000000>;
288 opp-microvolt = <900000>;
291 opp-hz = /bits/ 64 <80000000>;
292 opp-microvolt = <900000>;
295 opp-hz = /bits/ 64 <100000000>;
296 opp-microvolt = <1000000>;
299 opp-hz = /bits/ 64 <134000000>;
300 opp-microvolt = <1000000>;
303 opp-hz = /bits/ 64 <200000000>;
304 opp-microvolt = <1000000>;
309 compatible = "arm,cortex-a7-pmu";
310 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
315 compatible = "simple-bus";
316 #address-cells = <1>;
321 compatible = "mmio-sram";
322 reg = <0x02020000 0x40000>;
323 #address-cells = <1>;
325 ranges = <0 0x02020000 0x40000>;
328 compatible = "samsung,exynos4210-sysram";
333 compatible = "samsung,exynos4210-sysram-ns";
334 reg = <0x3f000 0x1000>;
339 compatible = "samsung,exynos4210-chipid";
340 reg = <0x10000000 0x100>;
343 sys_reg: syscon@10010000 {
344 compatible = "samsung,exynos3-sysreg", "syscon";
345 reg = <0x10010000 0x400>;
348 pmu_system_controller: system-controller@10020000 {
349 compatible = "samsung,exynos3250-pmu", "syscon";
350 reg = <0x10020000 0x4000>;
351 interrupt-controller;
352 #interrupt-cells = <3>;
353 interrupt-parent = <&gic>;
354 clock-names = "clkout8";
355 clocks = <&cmu CLK_FIN_PLL>;
359 mipi_phy: video-phy {
360 compatible = "samsung,s5pv210-mipi-video-phy";
362 syscon = <&pmu_system_controller>;
365 pd_cam: power-domain@10023c00 {
366 compatible = "samsung,exynos4210-pd";
367 reg = <0x10023c00 0x20>;
368 #power-domain-cells = <0>;
372 pd_mfc: power-domain@10023c40 {
373 compatible = "samsung,exynos4210-pd";
374 reg = <0x10023c40 0x20>;
375 #power-domain-cells = <0>;
379 pd_g3d: power-domain@10023c60 {
380 compatible = "samsung,exynos4210-pd";
381 reg = <0x10023c60 0x20>;
382 #power-domain-cells = <0>;
386 pd_lcd0: power-domain@10023c80 {
387 compatible = "samsung,exynos4210-pd";
388 reg = <0x10023c80 0x20>;
389 #power-domain-cells = <0>;
393 pd_isp: power-domain@10023ca0 {
394 compatible = "samsung,exynos4210-pd";
395 reg = <0x10023ca0 0x20>;
396 #power-domain-cells = <0>;
400 cmu: clock-controller@10030000 {
401 compatible = "samsung,exynos3250-cmu";
402 reg = <0x10030000 0x20000>;
404 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
405 <&cmu CLK_MOUT_ACLK_266_SUB>;
406 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
410 cmu_dmc: clock-controller@105c0000 {
411 compatible = "samsung,exynos3250-cmu-dmc";
412 reg = <0x105c0000 0x2000>;
417 compatible = "samsung,s3c6410-rtc";
418 reg = <0x10070000 0x100>;
419 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
421 interrupt-parent = <&pmu_system_controller>;
426 compatible = "samsung,exynos3250-tmu";
427 reg = <0x100c0000 0x100>;
428 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cmu CLK_TMU_APBIF>;
430 clock-names = "tmu_apbif";
431 #thermal-sensor-cells = <0>;
435 gic: interrupt-controller@10481000 {
436 compatible = "arm,cortex-a15-gic";
437 #interrupt-cells = <3>;
438 interrupt-controller;
439 reg = <0x10481000 0x1000>,
443 interrupts = <GIC_PPI 9
444 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
448 compatible = "samsung,exynos3250-mct",
449 "samsung,exynos4210-mct";
450 reg = <0x10050000 0x800>;
451 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
460 clock-names = "fin_pll", "mct";
463 pinctrl_1: pinctrl@11000000 {
464 compatible = "samsung,exynos3250-pinctrl";
465 reg = <0x11000000 0x1000>;
466 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
468 wakeup-interrupt-controller {
469 compatible = "samsung,exynos4210-wakeup-eint";
470 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
474 pinctrl_0: pinctrl@11400000 {
475 compatible = "samsung,exynos3250-pinctrl";
476 reg = <0x11400000 0x1000>;
477 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
480 jpeg: codec@11830000 {
481 compatible = "samsung,exynos3250-jpeg";
482 reg = <0x11830000 0x1000>;
483 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
485 clock-names = "jpeg", "sclk";
486 power-domains = <&pd_cam>;
487 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
488 assigned-clock-rates = <0>, <150000000>;
489 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
490 iommus = <&sysmmu_jpeg>;
494 sysmmu_jpeg: sysmmu@11a60000 {
495 compatible = "samsung,exynos-sysmmu";
496 reg = <0x11a60000 0x1000>;
497 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
498 clock-names = "sysmmu", "master";
499 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
500 power-domains = <&pd_cam>;
504 fimd: fimd@11c00000 {
505 compatible = "samsung,exynos3250-fimd";
506 reg = <0x11c00000 0x30000>;
507 interrupt-names = "fifo", "vsync", "lcd_sys";
508 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
512 clock-names = "sclk_fimd", "fimd";
513 power-domains = <&pd_lcd0>;
514 iommus = <&sysmmu_fimd0>;
515 samsung,sysreg = <&sys_reg>;
519 dsi_0: dsi@11c80000 {
520 compatible = "samsung,exynos3250-mipi-dsi";
521 reg = <0x11c80000 0x10000>;
522 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
523 samsung,phy-type = <0>;
524 power-domains = <&pd_lcd0>;
525 phys = <&mipi_phy 1>;
527 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
528 clock-names = "bus_clk", "pll_clk";
529 #address-cells = <1>;
534 sysmmu_fimd0: sysmmu@11e20000 {
535 compatible = "samsung,exynos-sysmmu";
536 reg = <0x11e20000 0x1000>;
537 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
538 clock-names = "sysmmu", "master";
539 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
540 power-domains = <&pd_lcd0>;
544 hsotg: usb@12480000 {
545 compatible = "samsung,s3c6400-hsotg";
546 reg = <0x12480000 0x20000>;
547 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cmu CLK_USBOTG>;
550 phys = <&exynos_usbphy 0>;
551 phy-names = "usb2-phy";
555 mshc_0: mmc@12510000 {
556 compatible = "samsung,exynos5420-dw-mshc";
557 reg = <0x12510000 0x1000>;
558 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
560 clock-names = "biu", "ciu";
562 #address-cells = <1>;
567 mshc_1: mmc@12520000 {
568 compatible = "samsung,exynos5420-dw-mshc";
569 reg = <0x12520000 0x1000>;
570 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
572 clock-names = "biu", "ciu";
574 #address-cells = <1>;
579 mshc_2: mmc@12530000 {
580 compatible = "samsung,exynos5250-dw-mshc";
581 reg = <0x12530000 0x1000>;
582 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
584 clock-names = "biu", "ciu";
586 #address-cells = <1>;
591 exynos_usbphy: usb-phy@125b0000 {
592 compatible = "samsung,exynos3250-usb2-phy";
593 reg = <0x125b0000 0x100>;
594 samsung,pmureg-phandle = <&pmu_system_controller>;
595 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
596 clock-names = "phy", "ref";
601 pdma0: dma-controller@12680000 {
602 compatible = "arm,pl330", "arm,primecell";
603 reg = <0x12680000 0x1000>;
604 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&cmu CLK_PDMA0>;
606 clock-names = "apb_pclk";
610 pdma1: dma-controller@12690000 {
611 compatible = "arm,pl330", "arm,primecell";
612 reg = <0x12690000 0x1000>;
613 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cmu CLK_PDMA1>;
615 clock-names = "apb_pclk";
620 compatible = "samsung,exynos3250-adc";
621 reg = <0x126c0000 0x100>;
622 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
623 clock-names = "adc", "sclk";
624 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
625 #io-channel-cells = <1>;
626 samsung,syscon-phandle = <&pmu_system_controller>;
631 compatible = "samsung,exynos4210-mali", "arm,mali-400";
632 reg = <0x13000000 0x10000>;
633 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
644 interrupt-names = "gp",
655 clocks = <&cmu CLK_G3D>,
657 clock-names = "bus", "core";
658 power-domains = <&pd_g3d>;
660 /* TODO: operating points for DVFS, assigned clock as 134 MHz */
663 mfc: codec@13400000 {
664 compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7";
665 reg = <0x13400000 0x10000>;
666 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
667 clock-names = "mfc", "sclk_mfc";
668 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
669 power-domains = <&pd_mfc>;
670 iommus = <&sysmmu_mfc>;
673 sysmmu_mfc: sysmmu@13620000 {
674 compatible = "samsung,exynos-sysmmu";
675 reg = <0x13620000 0x1000>;
676 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
677 clock-names = "sysmmu", "master";
678 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
679 power-domains = <&pd_mfc>;
683 serial_0: serial@13800000 {
684 compatible = "samsung,exynos4210-uart";
685 reg = <0x13800000 0x100>;
686 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
688 clock-names = "uart", "clk_uart_baud0";
689 pinctrl-names = "default";
690 pinctrl-0 = <&uart0_data &uart0_fctl>;
694 serial_1: serial@13810000 {
695 compatible = "samsung,exynos4210-uart";
696 reg = <0x13810000 0x100>;
697 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
699 clock-names = "uart", "clk_uart_baud0";
700 pinctrl-names = "default";
701 pinctrl-0 = <&uart1_data>;
705 serial_2: serial@13820000 {
706 compatible = "samsung,exynos4210-uart";
707 reg = <0x13820000 0x100>;
708 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
710 clock-names = "uart", "clk_uart_baud0";
711 pinctrl-names = "default";
712 pinctrl-0 = <&uart2_data>;
716 i2c_0: i2c@13860000 {
717 #address-cells = <1>;
719 compatible = "samsung,s3c2440-i2c";
720 reg = <0x13860000 0x100>;
721 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&cmu CLK_I2C0>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&i2c0_bus>;
729 i2c_1: i2c@13870000 {
730 #address-cells = <1>;
732 compatible = "samsung,s3c2440-i2c";
733 reg = <0x13870000 0x100>;
734 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&cmu CLK_I2C1>;
737 pinctrl-names = "default";
738 pinctrl-0 = <&i2c1_bus>;
742 i2c_2: i2c@13880000 {
743 #address-cells = <1>;
745 compatible = "samsung,s3c2440-i2c";
746 reg = <0x13880000 0x100>;
747 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&cmu CLK_I2C2>;
750 pinctrl-names = "default";
751 pinctrl-0 = <&i2c2_bus>;
755 i2c_3: i2c@13890000 {
756 #address-cells = <1>;
758 compatible = "samsung,s3c2440-i2c";
759 reg = <0x13890000 0x100>;
760 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&cmu CLK_I2C3>;
763 pinctrl-names = "default";
764 pinctrl-0 = <&i2c3_bus>;
768 i2c_4: i2c@138a0000 {
769 #address-cells = <1>;
771 compatible = "samsung,s3c2440-i2c";
772 reg = <0x138a0000 0x100>;
773 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cmu CLK_I2C4>;
776 pinctrl-names = "default";
777 pinctrl-0 = <&i2c4_bus>;
781 i2c_5: i2c@138b0000 {
782 #address-cells = <1>;
784 compatible = "samsung,s3c2440-i2c";
785 reg = <0x138b0000 0x100>;
786 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&cmu CLK_I2C5>;
789 pinctrl-names = "default";
790 pinctrl-0 = <&i2c5_bus>;
794 i2c_6: i2c@138c0000 {
795 #address-cells = <1>;
797 compatible = "samsung,s3c2440-i2c";
798 reg = <0x138c0000 0x100>;
799 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&cmu CLK_I2C6>;
802 pinctrl-names = "default";
803 pinctrl-0 = <&i2c6_bus>;
807 i2c_7: i2c@138d0000 {
808 #address-cells = <1>;
810 compatible = "samsung,s3c2440-i2c";
811 reg = <0x138d0000 0x100>;
812 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&cmu CLK_I2C7>;
815 pinctrl-names = "default";
816 pinctrl-0 = <&i2c7_bus>;
820 spi_0: spi@13920000 {
821 compatible = "samsung,exynos4210-spi";
822 reg = <0x13920000 0x100>;
823 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
824 dmas = <&pdma0 7>, <&pdma0 6>;
825 dma-names = "tx", "rx";
826 #address-cells = <1>;
828 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
829 clock-names = "spi", "spi_busclk0";
830 samsung,spi-src-clk = <0>;
831 pinctrl-names = "default";
832 pinctrl-0 = <&spi0_bus>;
836 spi_1: spi@13930000 {
837 compatible = "samsung,exynos4210-spi";
838 reg = <0x13930000 0x100>;
839 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
840 dmas = <&pdma1 7>, <&pdma1 6>;
841 dma-names = "tx", "rx";
842 #address-cells = <1>;
844 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
845 clock-names = "spi", "spi_busclk0";
846 samsung,spi-src-clk = <0>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&spi1_bus>;
853 compatible = "samsung,s3c6410-i2s";
854 reg = <0x13970000 0x100>;
855 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
857 clock-names = "iis", "i2s_opclk0";
858 dmas = <&pdma0 14>, <&pdma0 13>;
859 dma-names = "tx", "rx";
860 pinctrl-0 = <&i2s2_bus>;
861 pinctrl-names = "default";
866 compatible = "samsung,exynos4210-pwm";
867 reg = <0x139d0000 0x1000>;
868 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
872 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
877 ppmu_dmc0: ppmu@106a0000 {
878 compatible = "samsung,exynos-ppmu";
879 reg = <0x106a0000 0x2000>;
883 ppmu_dmc1: ppmu@106b0000 {
884 compatible = "samsung,exynos-ppmu";
885 reg = <0x106b0000 0x2000>;
889 ppmu_cpu: ppmu@106c0000 {
890 compatible = "samsung,exynos-ppmu";
891 reg = <0x106c0000 0x2000>;
895 ppmu_rightbus: ppmu@112a0000 {
896 compatible = "samsung,exynos-ppmu";
897 reg = <0x112a0000 0x2000>;
898 clocks = <&cmu CLK_PPMURIGHT>;
899 clock-names = "ppmu";
903 ppmu_leftbus: ppmu@116a0000 {
904 compatible = "samsung,exynos-ppmu";
905 reg = <0x116a0000 0x2000>;
906 clocks = <&cmu CLK_PPMULEFT>;
907 clock-names = "ppmu";
911 ppmu_camif: ppmu@11ac0000 {
912 compatible = "samsung,exynos-ppmu";
913 reg = <0x11ac0000 0x2000>;
914 clocks = <&cmu CLK_PPMUCAMIF>;
915 clock-names = "ppmu";
919 ppmu_lcd0: ppmu@11e40000 {
920 compatible = "samsung,exynos-ppmu";
921 reg = <0x11e40000 0x2000>;
922 clocks = <&cmu CLK_PPMULCD0>;
923 clock-names = "ppmu";
927 ppmu_fsys: ppmu@12630000 {
928 compatible = "samsung,exynos-ppmu";
929 reg = <0x12630000 0x2000>;
930 clocks = <&cmu CLK_PPMUFILE>;
931 clock-names = "ppmu";
935 ppmu_g3d: ppmu@13220000 {
936 compatible = "samsung,exynos-ppmu";
937 reg = <0x13220000 0x2000>;
938 clocks = <&cmu CLK_PPMUG3D>;
939 clock-names = "ppmu";
943 ppmu_mfc: ppmu@13660000 {
944 compatible = "samsung,exynos-ppmu";
945 reg = <0x13660000 0x2000>;
946 clocks = <&cmu CLK_PPMUMFC_L>;
947 clock-names = "ppmu";
953 #include "exynos3250-pinctrl.dtsi"
954 #include "exynos-syscon-restart.dtsi"