arch/arm/boot/dts/exynos3250.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos3250 SoC device tree source
   4  *
   5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   9  * based board files can include this file and provide values for board specfic
  10  * bindings.
  11  *
  12  * Note: This file does not include device nodes for all the controllers in
  13  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  14  * nodes can be added to this file.
  15  */
  16
  17 #include "exynos4-cpu-thermal.dtsi"
  18 #include <dt-bindings/clock/exynos3250.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/interrupt-controller/irq.h>
  21
  22 / {
  23         compatible = "samsung,exynos3250";
  24         interrupt-parent = <&gic>;
  25         #address-cells = <1>;
  26         #size-cells = <1>;
  27
  28         aliases {
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 mshc0 = &mshc_0;
  32                 mshc1 = &mshc_1;
  33                 mshc2 = &mshc_2;
  34                 spi0 = &spi_0;
  35                 spi1 = &spi_1;
  36                 i2c0 = &i2c_0;
  37                 i2c1 = &i2c_1;
  38                 i2c2 = &i2c_2;
  39                 i2c3 = &i2c_3;
  40                 i2c4 = &i2c_4;
  41                 i2c5 = &i2c_5;
  42                 i2c6 = &i2c_6;
  43                 i2c7 = &i2c_7;
  44                 serial0 = &serial_0;
  45                 serial1 = &serial_1;
  46                 serial2 = &serial_2;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a7";
  56                         reg = <0>;
  57                         clock-frequency = <1000000000>;
  58                         clocks = <&cmu CLK_ARM_CLK>;
  59                         clock-names = "cpu";
  60                         #cooling-cells = <2>;
  61
  62                         operating-points = <
  63                                 1000000 1150000
  64                                 900000  1112500
  65                                 800000  1075000
  66                                 700000  1037500
  67                                 600000  1000000
  68                                 500000  962500
  69                                 400000  925000
  70                                 300000  887500
  71                                 200000  850000
  72                                 100000  850000
  73                         >;
  74                 };
  75
  76                 cpu1: cpu@1 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <1>;
  80                         clock-frequency = <1000000000>;
  81                         clocks = <&cmu CLK_ARM_CLK>;
  82                         clock-names = "cpu";
  83                         #cooling-cells = <2>;
  84
  85                         operating-points = <
  86                                 1000000 1150000
  87                                 900000  1112500
  88                                 800000  1075000
  89                                 700000  1037500
  90                                 600000  1000000
  91                                 500000  962500
  92                                 400000  925000
  93                                 300000  887500
  94                                 200000  850000
  95                                 100000  850000
  96                         >;
  97                 };
  98         };
  99
 100         fixed-rate-clocks {
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103
 104                 xusbxti: clock@0 {
 105                         compatible = "fixed-clock";
 106                         reg = <0>;
 107                         clock-frequency = <0>;
 108                         #clock-cells = <0>;
 109                         clock-output-names = "xusbxti";
 110                 };
 111
 112                 xxti: clock@1 {
 113                         compatible = "fixed-clock";
 114                         reg = <1>;
 115                         clock-frequency = <0>;
 116                         #clock-cells = <0>;
 117                         clock-output-names = "xxti";
 118                 };
 119
 120                 xtcxo: clock@2 {
 121                         compatible = "fixed-clock";
 122                         reg = <2>;
 123                         clock-frequency = <0>;
 124                         #clock-cells = <0>;
 125                         clock-output-names = "xtcxo";
 126                 };
 127         };
 128
 129         pmu {
 130                 compatible = "arm,cortex-a7-pmu";
 131                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 132                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 133         };
 134
 135         soc: soc {
 136                 compatible = "simple-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 sram@2020000 {
 142                         compatible = "mmio-sram";
 143                         reg = <0x02020000 0x40000>;
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146                         ranges = <0 0x02020000 0x40000>;
 147
 148                         smp-sram@0 {
 149                                 compatible = "samsung,exynos4210-sysram";
 150                                 reg = <0x0 0x1000>;
 151                         };
 152
 153                         smp-sram@3f000 {
 154                                 compatible = "samsung,exynos4210-sysram-ns";
 155                                 reg = <0x3f000 0x1000>;
 156                         };
 157                 };
 158
 159                 chipid@10000000 {
 160                         compatible = "samsung,exynos4210-chipid";
 161                         reg = <0x10000000 0x100>;
 162                 };
 163
 164                 sys_reg: syscon@10010000 {
 165                         compatible = "samsung,exynos3-sysreg", "syscon";
 166                         reg = <0x10010000 0x400>;
 167                 };
 168
 169                 pmu_system_controller: system-controller@10020000 {
 170                         compatible = "samsung,exynos3250-pmu", "syscon";
 171                         reg = <0x10020000 0x4000>;
 172                         interrupt-controller;
 173                         #interrupt-cells = <3>;
 174                         interrupt-parent = <&gic>;
 175                         clock-names = "clkout8";
 176                         clocks = <&cmu CLK_FIN_PLL>;
 177                         #clock-cells = <1>;
 178                 };
 179
 180                 mipi_phy: video-phy {
 181                         compatible = "samsung,s5pv210-mipi-video-phy";
 182                         #phy-cells = <1>;
 183                         syscon = <&pmu_system_controller>;
 184                 };
 185
 186                 pd_cam: power-domain@10023c00 {
 187                         compatible = "samsung,exynos4210-pd";
 188                         reg = <0x10023C00 0x20>;
 189                         #power-domain-cells = <0>;
 190                         label = "CAM";
 191                 };
 192
 193                 pd_mfc: power-domain@10023c40 {
 194                         compatible = "samsung,exynos4210-pd";
 195                         reg = <0x10023C40 0x20>;
 196                         #power-domain-cells = <0>;
 197                         label = "MFC";
 198                 };
 199
 200                 pd_g3d: power-domain@10023c60 {
 201                         compatible = "samsung,exynos4210-pd";
 202                         reg = <0x10023C60 0x20>;
 203                         #power-domain-cells = <0>;
 204                         label = "G3D";
 205                 };
 206
 207                 pd_lcd0: power-domain@10023c80 {
 208                         compatible = "samsung,exynos4210-pd";
 209                         reg = <0x10023C80 0x20>;
 210                         #power-domain-cells = <0>;
 211                         label = "LCD0";
 212                 };
 213
 214                 pd_isp: power-domain@10023ca0 {
 215                         compatible = "samsung,exynos4210-pd";
 216                         reg = <0x10023CA0 0x20>;
 217                         #power-domain-cells = <0>;
 218                         label = "ISP";
 219                 };
 220
 221                 cmu: clock-controller@10030000 {
 222                         compatible = "samsung,exynos3250-cmu";
 223                         reg = <0x10030000 0x20000>;
 224                         #clock-cells = <1>;
 225                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
 226                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
 227                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
 228                                                  <&cmu CLK_FIN_PLL>;
 229                 };
 230
 231                 cmu_dmc: clock-controller@105c0000 {
 232                         compatible = "samsung,exynos3250-cmu-dmc";
 233                         reg = <0x105C0000 0x2000>;
 234                         #clock-cells = <1>;
 235                 };
 236
 237                 rtc: rtc@10070000 {
 238                         compatible = "samsung,s3c6410-rtc";
 239                         reg = <0x10070000 0x100>;
 240                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 242                         interrupt-parent = <&pmu_system_controller>;
 243                         status = "disabled";
 244                 };
 245
 246                 tmu: tmu@100c0000 {
 247                         compatible = "samsung,exynos3250-tmu";
 248                         reg = <0x100C0000 0x100>;
 249                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&cmu CLK_TMU_APBIF>;
 251                         clock-names = "tmu_apbif";
 252                         #thermal-sensor-cells = <0>;
 253                         status = "disabled";
 254                 };
 255
 256                 gic: interrupt-controller@10481000 {
 257                         compatible = "arm,cortex-a15-gic";
 258                         #interrupt-cells = <3>;
 259                         interrupt-controller;
 260                         reg = <0x10481000 0x1000>,
 261                               <0x10482000 0x2000>,
 262                               <0x10484000 0x2000>,
 263                               <0x10486000 0x2000>;
 264                         interrupts = <GIC_PPI 9
 265                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 266                 };
 267
 268                 timer@10050000 {
 269                         compatible = "samsung,exynos4210-mct";
 270                         reg = <0x10050000 0x800>;
 271                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 272                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 273                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
 275                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
 276                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 277                                      <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
 278                                      <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 280                         clock-names = "fin_pll", "mct";
 281                 };
 282
 283                 pinctrl_1: pinctrl@11000000 {
 284                         compatible = "samsung,exynos3250-pinctrl";
 285                         reg = <0x11000000 0x1000>;
 286                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 287
 288                         wakeup-interrupt-controller {
 289                                 compatible = "samsung,exynos4210-wakeup-eint";
 290                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 291                         };
 292                 };
 293
 294                 pinctrl_0: pinctrl@11400000 {
 295                         compatible = "samsung,exynos3250-pinctrl";
 296                         reg = <0x11400000 0x1000>;
 297                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 298                 };
 299
 300                 jpeg: codec@11830000 {
 301                         compatible = "samsung,exynos3250-jpeg";
 302                         reg = <0x11830000 0x1000>;
 303                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
 305                         clock-names = "jpeg", "sclk";
 306                         power-domains = <&pd_cam>;
 307                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
 308                         assigned-clock-rates = <0>, <150000000>;
 309                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
 310                         iommus = <&sysmmu_jpeg>;
 311                         status = "disabled";
 312                 };
 313
 314                 sysmmu_jpeg: sysmmu@11a60000 {
 315                         compatible = "samsung,exynos-sysmmu";
 316                         reg = <0x11a60000 0x1000>;
 317                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 318                         clock-names = "sysmmu", "master";
 319                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
 320                         power-domains = <&pd_cam>;
 321                         #iommu-cells = <0>;
 322                 };
 323
 324                 fimd: fimd@11c00000 {
 325                         compatible = "samsung,exynos3250-fimd";
 326                         reg = <0x11c00000 0x30000>;
 327                         interrupt-names = "fifo", "vsync", "lcd_sys";
 328                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 330                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 332                         clock-names = "sclk_fimd", "fimd";
 333                         power-domains = <&pd_lcd0>;
 334                         iommus = <&sysmmu_fimd0>;
 335                         samsung,sysreg = <&sys_reg>;
 336                         status = "disabled";
 337                 };
 338
 339                 dsi_0: dsi@11c80000 {
 340                         compatible = "samsung,exynos3250-mipi-dsi";
 341                         reg = <0x11C80000 0x10000>;
 342                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 343                         samsung,phy-type = <0>;
 344                         power-domains = <&pd_lcd0>;
 345                         phys = <&mipi_phy 1>;
 346                         phy-names = "dsim";
 347                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 348                         clock-names = "bus_clk", "pll_clk";
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351                         status = "disabled";
 352                 };
 353
 354                 sysmmu_fimd0: sysmmu@11e20000 {
 355                         compatible = "samsung,exynos-sysmmu";
 356                         reg = <0x11e20000 0x1000>;
 357                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 358                         clock-names = "sysmmu", "master";
 359                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
 360                         power-domains = <&pd_lcd0>;
 361                         #iommu-cells = <0>;
 362                 };
 363
 364                 hsotg: hsotg@12480000 {
 365                         compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
 366                         reg = <0x12480000 0x20000>;
 367                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&cmu CLK_USBOTG>;
 369                         clock-names = "otg";
 370                         phys = <&exynos_usbphy 0>;
 371                         phy-names = "usb2-phy";
 372                         status = "disabled";
 373                 };
 374
 375                 mshc_0: mshc@12510000 {
 376                         compatible = "samsung,exynos5420-dw-mshc";
 377                         reg = <0x12510000 0x1000>;
 378                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 379                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 380                         clock-names = "biu", "ciu";
 381                         fifo-depth = <0x80>;
 382                         #address-cells = <1>;
 383                         #size-cells = <0>;
 384                         status = "disabled";
 385                 };
 386
 387                 mshc_1: mshc@12520000 {
 388                         compatible = "samsung,exynos5420-dw-mshc";
 389                         reg = <0x12520000 0x1000>;
 390                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 391                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 392                         clock-names = "biu", "ciu";
 393                         fifo-depth = <0x80>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         status = "disabled";
 397                 };
 398
 399                 mshc_2: mshc@12530000 {
 400                         compatible = "samsung,exynos5250-dw-mshc";
 401                         reg = <0x12530000 0x1000>;
 402                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 403                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
 404                         clock-names = "biu", "ciu";
 405                         fifo-depth = <0x80>;
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         status = "disabled";
 409                 };
 410
 411                 exynos_usbphy: exynos-usbphy@125b0000 {
 412                         compatible = "samsung,exynos3250-usb2-phy";
 413                         reg = <0x125B0000 0x100>;
 414                         samsung,pmureg-phandle = <&pmu_system_controller>;
 415                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 416                         clock-names = "phy", "ref";
 417                         #phy-cells = <1>;
 418                         status = "disabled";
 419                 };
 420
 421                 pdma0: pdma@12680000 {
 422                         compatible = "arm,pl330", "arm,primecell";
 423                         reg = <0x12680000 0x1000>;
 424                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 425                         clocks = <&cmu CLK_PDMA0>;
 426                         clock-names = "apb_pclk";
 427                         #dma-cells = <1>;
 428                         #dma-channels = <8>;
 429                         #dma-requests = <32>;
 430                 };
 431
 432                 pdma1: pdma@12690000 {
 433                         compatible = "arm,pl330", "arm,primecell";
 434                         reg = <0x12690000 0x1000>;
 435                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&cmu CLK_PDMA1>;
 437                         clock-names = "apb_pclk";
 438                         #dma-cells = <1>;
 439                         #dma-channels = <8>;
 440                         #dma-requests = <32>;
 441                 };
 442
 443                 adc: adc@126c0000 {
 444                         compatible = "samsung,exynos3250-adc";
 445                         reg = <0x126C0000 0x100>;
 446                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 447                         clock-names = "adc", "sclk";
 448                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 449                         #io-channel-cells = <1>;
 450                         io-channel-ranges;
 451                         samsung,syscon-phandle = <&pmu_system_controller>;
 452                         status = "disabled";
 453                 };
 454
 455                 gpu: gpu@13000000 {
 456                         compatible = "samsung,exynos4210-mali", "arm,mali-400";
 457                         reg = <0x13000000 0x10000>;
 458                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 459                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 460                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 461                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 462                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 463                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 464                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 465                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 466                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 467                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 468                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 469                         interrupt-names = "gp",
 470                                           "gpmmu",
 471                                           "pp0",
 472                                           "ppmmu0",
 473                                           "pp1",
 474                                           "ppmmu1",
 475                                           "pp2",
 476                                           "ppmmu2",
 477                                           "pp3",
 478                                           "ppmmu3",
 479                                           "pmu";
 480                         clocks = <&cmu CLK_G3D>,
 481                                  <&cmu CLK_SCLK_G3D>;
 482                         clock-names = "bus", "core";
 483                         power-domains = <&pd_g3d>;
 484                         status = "disabled";
 485                         /* TODO: operating points for DVFS, assigned clock as 134 MHz */
 486                 };
 487
 488                 mfc: codec@13400000 {
 489                         compatible = "samsung,mfc-v7";
 490                         reg = <0x13400000 0x10000>;
 491                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 492                         clock-names = "mfc", "sclk_mfc";
 493                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 494                         power-domains = <&pd_mfc>;
 495                         iommus = <&sysmmu_mfc>;
 496                 };
 497
 498                 sysmmu_mfc: sysmmu@13620000 {
 499                         compatible = "samsung,exynos-sysmmu";
 500                         reg = <0x13620000 0x1000>;
 501                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 502                         clock-names = "sysmmu", "master";
 503                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
 504                         power-domains = <&pd_mfc>;
 505                         #iommu-cells = <0>;
 506                 };
 507
 508                 serial_0: serial@13800000 {
 509                         compatible = "samsung,exynos4210-uart";
 510                         reg = <0x13800000 0x100>;
 511                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 513                         clock-names = "uart", "clk_uart_baud0";
 514                         pinctrl-names = "default";
 515                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 516                         status = "disabled";
 517                 };
 518
 519                 serial_1: serial@13810000 {
 520                         compatible = "samsung,exynos4210-uart";
 521                         reg = <0x13810000 0x100>;
 522                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 524                         clock-names = "uart", "clk_uart_baud0";
 525                         pinctrl-names = "default";
 526                         pinctrl-0 = <&uart1_data>;
 527                         status = "disabled";
 528                 };
 529
 530                 serial_2: serial@13820000 {
 531                         compatible = "samsung,exynos4210-uart";
 532                         reg = <0x13820000 0x100>;
 533                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
 535                         clock-names = "uart", "clk_uart_baud0";
 536                         pinctrl-names = "default";
 537                         pinctrl-0 = <&uart2_data>;
 538                         status = "disabled";
 539                 };
 540
 541                 i2c_0: i2c@13860000 {
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544                         compatible = "samsung,s3c2440-i2c";
 545                         reg = <0x13860000 0x100>;
 546                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&cmu CLK_I2C0>;
 548                         clock-names = "i2c";
 549                         pinctrl-names = "default";
 550                         pinctrl-0 = <&i2c0_bus>;
 551                         status = "disabled";
 552                 };
 553
 554                 i2c_1: i2c@13870000 {
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         compatible = "samsung,s3c2440-i2c";
 558                         reg = <0x13870000 0x100>;
 559                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 560                         clocks = <&cmu CLK_I2C1>;
 561                         clock-names = "i2c";
 562                         pinctrl-names = "default";
 563                         pinctrl-0 = <&i2c1_bus>;
 564                         status = "disabled";
 565                 };
 566
 567                 i2c_2: i2c@13880000 {
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                         compatible = "samsung,s3c2440-i2c";
 571                         reg = <0x13880000 0x100>;
 572                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 573                         clocks = <&cmu CLK_I2C2>;
 574                         clock-names = "i2c";
 575                         pinctrl-names = "default";
 576                         pinctrl-0 = <&i2c2_bus>;
 577                         status = "disabled";
 578                 };
 579
 580                 i2c_3: i2c@13890000 {
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         compatible = "samsung,s3c2440-i2c";
 584                         reg = <0x13890000 0x100>;
 585                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 586                         clocks = <&cmu CLK_I2C3>;
 587                         clock-names = "i2c";
 588                         pinctrl-names = "default";
 589                         pinctrl-0 = <&i2c3_bus>;
 590                         status = "disabled";
 591                 };
 592
 593                 i2c_4: i2c@138a0000 {
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         compatible = "samsung,s3c2440-i2c";
 597                         reg = <0x138A0000 0x100>;
 598                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&cmu CLK_I2C4>;
 600                         clock-names = "i2c";
 601                         pinctrl-names = "default";
 602                         pinctrl-0 = <&i2c4_bus>;
 603                         status = "disabled";
 604                 };
 605
 606                 i2c_5: i2c@138b0000 {
 607                         #address-cells = <1>;
 608                         #size-cells = <0>;
 609                         compatible = "samsung,s3c2440-i2c";
 610                         reg = <0x138B0000 0x100>;
 611                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&cmu CLK_I2C5>;
 613                         clock-names = "i2c";
 614                         pinctrl-names = "default";
 615                         pinctrl-0 = <&i2c5_bus>;
 616                         status = "disabled";
 617                 };
 618
 619                 i2c_6: i2c@138c0000 {
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                         compatible = "samsung,s3c2440-i2c";
 623                         reg = <0x138C0000 0x100>;
 624                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 625                         clocks = <&cmu CLK_I2C6>;
 626                         clock-names = "i2c";
 627                         pinctrl-names = "default";
 628                         pinctrl-0 = <&i2c6_bus>;
 629                         status = "disabled";
 630                 };
 631
 632                 i2c_7: i2c@138d0000 {
 633                         #address-cells = <1>;
 634                         #size-cells = <0>;
 635                         compatible = "samsung,s3c2440-i2c";
 636                         reg = <0x138D0000 0x100>;
 637                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 638                         clocks = <&cmu CLK_I2C7>;
 639                         clock-names = "i2c";
 640                         pinctrl-names = "default";
 641                         pinctrl-0 = <&i2c7_bus>;
 642                         status = "disabled";
 643                 };
 644
 645                 spi_0: spi@13920000 {
 646                         compatible = "samsung,exynos4210-spi";
 647                         reg = <0x13920000 0x100>;
 648                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 649                         dmas = <&pdma0 7>, <&pdma0 6>;
 650                         dma-names = "tx", "rx";
 651                         #address-cells = <1>;
 652                         #size-cells = <0>;
 653                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 654                         clock-names = "spi", "spi_busclk0";
 655                         samsung,spi-src-clk = <0>;
 656                         pinctrl-names = "default";
 657                         pinctrl-0 = <&spi0_bus>;
 658                         status = "disabled";
 659                 };
 660
 661                 spi_1: spi@13930000 {
 662                         compatible = "samsung,exynos4210-spi";
 663                         reg = <0x13930000 0x100>;
 664                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 665                         dmas = <&pdma1 7>, <&pdma1 6>;
 666                         dma-names = "tx", "rx";
 667                         #address-cells = <1>;
 668                         #size-cells = <0>;
 669                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 670                         clock-names = "spi", "spi_busclk0";
 671                         samsung,spi-src-clk = <0>;
 672                         pinctrl-names = "default";
 673                         pinctrl-0 = <&spi1_bus>;
 674                         status = "disabled";
 675                 };
 676
 677                 i2s2: i2s@13970000 {
 678                         compatible = "samsung,s3c6410-i2s";
 679                         reg = <0x13970000 0x100>;
 680                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 682                         clock-names = "iis", "i2s_opclk0";
 683                         dmas = <&pdma0 14>, <&pdma0 13>;
 684                         dma-names = "tx", "rx";
 685                         pinctrl-0 = <&i2s2_bus>;
 686                         pinctrl-names = "default";
 687                         status = "disabled";
 688                 };
 689
 690                 pwm: pwm@139d0000 {
 691                         compatible = "samsung,exynos4210-pwm";
 692                         reg = <0x139D0000 0x1000>;
 693                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 698                         #pwm-cells = <3>;
 699                         status = "disabled";
 700                 };
 701
 702                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 703                         compatible = "samsung,exynos-ppmu";
 704                         reg = <0x106a0000 0x2000>;
 705                         status = "disabled";
 706                 };
 707
 708                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 709                         compatible = "samsung,exynos-ppmu";
 710                         reg = <0x106b0000 0x2000>;
 711                         status = "disabled";
 712                 };
 713
 714                 ppmu_cpu: ppmu_cpu@106c0000 {
 715                         compatible = "samsung,exynos-ppmu";
 716                         reg = <0x106c0000 0x2000>;
 717                         status = "disabled";
 718                 };
 719
 720                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 721                         compatible = "samsung,exynos-ppmu";
 722                         reg = <0x112a0000 0x2000>;
 723                         clocks = <&cmu CLK_PPMURIGHT>;
 724                         clock-names = "ppmu";
 725                         status = "disabled";
 726                 };
 727
 728                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 729                         compatible = "samsung,exynos-ppmu";
 730                         reg = <0x116a0000 0x2000>;
 731                         clocks = <&cmu CLK_PPMULEFT>;
 732                         clock-names = "ppmu";
 733                         status = "disabled";
 734                 };
 735
 736                 ppmu_camif: ppmu_camif@11ac0000 {
 737                         compatible = "samsung,exynos-ppmu";
 738                         reg = <0x11ac0000 0x2000>;
 739                         clocks = <&cmu CLK_PPMUCAMIF>;
 740                         clock-names = "ppmu";
 741                         status = "disabled";
 742                 };
 743
 744                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 745                         compatible = "samsung,exynos-ppmu";
 746                         reg = <0x11e40000 0x2000>;
 747                         clocks = <&cmu CLK_PPMULCD0>;
 748                         clock-names = "ppmu";
 749                         status = "disabled";
 750                 };
 751
 752                 ppmu_fsys: ppmu_fsys@12630000 {
 753                         compatible = "samsung,exynos-ppmu";
 754                         reg = <0x12630000 0x2000>;
 755                         clocks = <&cmu CLK_PPMUFILE>;
 756                         clock-names = "ppmu";
 757                         status = "disabled";
 758                 };
 759
 760                 ppmu_g3d: ppmu_g3d@13220000 {
 761                         compatible = "samsung,exynos-ppmu";
 762                         reg = <0x13220000 0x2000>;
 763                         clocks = <&cmu CLK_PPMUG3D>;
 764                         clock-names = "ppmu";
 765                         status = "disabled";
 766                 };
 767
 768                 ppmu_mfc: ppmu_mfc@13660000 {
 769                         compatible = "samsung,exynos-ppmu";
 770                         reg = <0x13660000 0x2000>;
 771                         clocks = <&cmu CLK_PPMUMFC_L>;
 772                         clock-names = "ppmu";
 773                         status = "disabled";
 774                 };
 775
 776                 bus_dmc: bus_dmc {
 777                         compatible = "samsung,exynos-bus";
 778                         clocks = <&cmu_dmc CLK_DIV_DMC>;
 779                         clock-names = "bus";
 780                         operating-points-v2 = <&bus_dmc_opp_table>;
 781                         status = "disabled";
 782                 };
 783
 784                 bus_dmc_opp_table: opp_table1 {
 785                         compatible = "operating-points-v2";
 786                         opp-shared;
 787
 788                         opp-50000000 {
 789                                 opp-hz = /bits/ 64 <50000000>;
 790                                 opp-microvolt = <800000>;
 791                         };
 792                         opp-100000000 {
 793                                 opp-hz = /bits/ 64 <100000000>;
 794                                 opp-microvolt = <800000>;
 795                         };
 796                         opp-134000000 {
 797                                 opp-hz = /bits/ 64 <134000000>;
 798                                 opp-microvolt = <800000>;
 799                         };
 800                         opp-200000000 {
 801                                 opp-hz = /bits/ 64 <200000000>;
 802                                 opp-microvolt = <825000>;
 803                         };
 804                         opp-400000000 {
 805                                 opp-hz = /bits/ 64 <400000000>;
 806                                 opp-microvolt = <875000>;
 807                         };
 808                 };
 809
 810                 bus_leftbus: bus_leftbus {
 811                         compatible = "samsung,exynos-bus";
 812                         clocks = <&cmu CLK_DIV_GDL>;
 813                         clock-names = "bus";
 814                         operating-points-v2 = <&bus_leftbus_opp_table>;
 815                         status = "disabled";
 816                 };
 817
 818                 bus_rightbus: bus_rightbus {
 819                         compatible = "samsung,exynos-bus";
 820                         clocks = <&cmu CLK_DIV_GDR>;
 821                         clock-names = "bus";
 822                         operating-points-v2 = <&bus_leftbus_opp_table>;
 823                         status = "disabled";
 824                 };
 825
 826                 bus_lcd0: bus_lcd0 {
 827                         compatible = "samsung,exynos-bus";
 828                         clocks = <&cmu CLK_DIV_ACLK_160>;
 829                         clock-names = "bus";
 830                         operating-points-v2 = <&bus_leftbus_opp_table>;
 831                         status = "disabled";
 832                 };
 833
 834                 bus_fsys: bus_fsys {
 835                         compatible = "samsung,exynos-bus";
 836                         clocks = <&cmu CLK_DIV_ACLK_200>;
 837                         clock-names = "bus";
 838                         operating-points-v2 = <&bus_leftbus_opp_table>;
 839                         status = "disabled";
 840                 };
 841
 842                 bus_mcuisp: bus_mcuisp {
 843                         compatible = "samsung,exynos-bus";
 844                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
 845                         clock-names = "bus";
 846                         operating-points-v2 = <&bus_mcuisp_opp_table>;
 847                         status = "disabled";
 848                 };
 849
 850                 bus_isp: bus_isp {
 851                         compatible = "samsung,exynos-bus";
 852                         clocks = <&cmu CLK_DIV_ACLK_266>;
 853                         clock-names = "bus";
 854                         operating-points-v2 = <&bus_isp_opp_table>;
 855                         status = "disabled";
 856                 };
 857
 858                 bus_peril: bus_peril {
 859                         compatible = "samsung,exynos-bus";
 860                         clocks = <&cmu CLK_DIV_ACLK_100>;
 861                         clock-names = "bus";
 862                         operating-points-v2 = <&bus_peril_opp_table>;
 863                         status = "disabled";
 864                 };
 865
 866                 bus_mfc: bus_mfc {
 867                         compatible = "samsung,exynos-bus";
 868                         clocks = <&cmu CLK_SCLK_MFC>;
 869                         clock-names = "bus";
 870                         operating-points-v2 = <&bus_leftbus_opp_table>;
 871                         status = "disabled";
 872                 };
 873
 874                 bus_leftbus_opp_table: opp_table2 {
 875                         compatible = "operating-points-v2";
 876                         opp-shared;
 877
 878                         opp-50000000 {
 879                                 opp-hz = /bits/ 64 <50000000>;
 880                                 opp-microvolt = <900000>;
 881                         };
 882                         opp-80000000 {
 883                                 opp-hz = /bits/ 64 <80000000>;
 884                                 opp-microvolt = <900000>;
 885                         };
 886                         opp-100000000 {
 887                                 opp-hz = /bits/ 64 <100000000>;
 888                                 opp-microvolt = <1000000>;
 889                         };
 890                         opp-134000000 {
 891                                 opp-hz = /bits/ 64 <134000000>;
 892                                 opp-microvolt = <1000000>;
 893                         };
 894                         opp-200000000 {
 895                                 opp-hz = /bits/ 64 <200000000>;
 896                                 opp-microvolt = <1000000>;
 897                         };
 898                 };
 899
 900                 bus_mcuisp_opp_table: opp_table3 {
 901                         compatible = "operating-points-v2";
 902                         opp-shared;
 903
 904                         opp-50000000 {
 905                                 opp-hz = /bits/ 64 <50000000>;
 906                         };
 907                         opp-80000000 {
 908                                 opp-hz = /bits/ 64 <80000000>;
 909                         };
 910                         opp-100000000 {
 911                                 opp-hz = /bits/ 64 <100000000>;
 912                         };
 913                         opp-200000000 {
 914                                 opp-hz = /bits/ 64 <200000000>;
 915                         };
 916                         opp-400000000 {
 917                                 opp-hz = /bits/ 64 <400000000>;
 918                         };
 919                 };
 920
 921                 bus_isp_opp_table: opp_table4 {
 922                         compatible = "operating-points-v2";
 923                         opp-shared;
 924
 925                         opp-50000000 {
 926                                 opp-hz = /bits/ 64 <50000000>;
 927                         };
 928                         opp-80000000 {
 929                                 opp-hz = /bits/ 64 <80000000>;
 930                         };
 931                         opp-100000000 {
 932                                 opp-hz = /bits/ 64 <100000000>;
 933                         };
 934                         opp-200000000 {
 935                                 opp-hz = /bits/ 64 <200000000>;
 936                         };
 937                         opp-300000000 {
 938                                 opp-hz = /bits/ 64 <300000000>;
 939                         };
 940                 };
 941
 942                 bus_peril_opp_table: opp_table5 {
 943                         compatible = "operating-points-v2";
 944                         opp-shared;
 945
 946                         opp-50000000 {
 947                                 opp-hz = /bits/ 64 <50000000>;
 948                         };
 949                         opp-80000000 {
 950                                 opp-hz = /bits/ 64 <80000000>;
 951                         };
 952                         opp-100000000 {
 953                                 opp-hz = /bits/ 64 <100000000>;
 954                         };
 955                 };
 956         };
 957 };
 958
 959 #include "exynos3250-pinctrl.dtsi"
 960 #include "exynos-syscon-restart.dtsi"