2 * Samsung's Exynos3250 SoC device tree source
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
13 * nodes can be added to this file.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include "skeleton.dtsi"
21 #include <dt-bindings/clock/exynos3250.h>
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
52 compatible = "arm,cortex-a7";
54 clock-frequency = <1000000000>;
59 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
66 compatible = "simple-bus";
76 compatible = "fixed-clock";
80 clock-frequency = <0>;
82 clock-output-names = "xusbxti";
86 compatible = "fixed-clock";
88 clock-frequency = <0>;
90 clock-output-names = "xxti";
94 compatible = "fixed-clock";
96 clock-frequency = <0>;
98 clock-output-names = "xtcxo";
103 compatible = "mmio-sram";
104 reg = <0x02020000 0x40000>;
105 #address-cells = <1>;
107 ranges = <0 0x02020000 0x40000>;
110 compatible = "samsung,exynos4210-sysram";
115 compatible = "samsung,exynos4210-sysram-ns";
116 reg = <0x3f000 0x1000>;
121 compatible = "samsung,exynos4210-chipid";
122 reg = <0x10000000 0x100>;
125 sys_reg: syscon@10010000 {
126 compatible = "samsung,exynos3-sysreg", "syscon";
127 reg = <0x10010000 0x400>;
130 pmu_system_controller: system-controller@10020000 {
131 compatible = "samsung,exynos3250-pmu", "syscon";
132 reg = <0x10020000 0x4000>;
135 mipi_phy: video-phy@10020710 {
136 compatible = "samsung,s5pv210-mipi-video-phy";
137 reg = <0x10020710 8>;
141 pd_cam: cam-power-domain@10023C00 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10023C00 0x20>;
146 pd_mfc: mfc-power-domain@10023C40 {
147 compatible = "samsung,exynos4210-pd";
148 reg = <0x10023C40 0x20>;
151 pd_g3d: g3d-power-domain@10023C60 {
152 compatible = "samsung,exynos4210-pd";
153 reg = <0x10023C60 0x20>;
156 pd_lcd0: lcd0-power-domain@10023C80 {
157 compatible = "samsung,exynos4210-pd";
158 reg = <0x10023C80 0x20>;
161 pd_isp: isp-power-domain@10023CA0 {
162 compatible = "samsung,exynos4210-pd";
163 reg = <0x10023CA0 0x20>;
166 cmu: clock-controller@10030000 {
167 compatible = "samsung,exynos3250-cmu";
168 reg = <0x10030000 0x20000>;
173 compatible = "samsung,exynos3250-rtc";
174 reg = <0x10070000 0x100>;
175 interrupts = <0 73 0>, <0 74 0>;
180 compatible = "samsung,exynos3250-tmu";
181 reg = <0x100C0000 0x100>;
182 interrupts = <0 216 0>;
183 clocks = <&cmu CLK_TMU_APBIF>;
184 clock-names = "tmu_apbif";
188 gic: interrupt-controller@10481000 {
189 compatible = "arm,cortex-a15-gic";
190 #interrupt-cells = <3>;
191 interrupt-controller;
192 reg = <0x10481000 0x1000>,
196 interrupts = <1 9 0xf04>;
200 compatible = "samsung,exynos4210-mct";
201 reg = <0x10050000 0x800>;
202 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
203 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
204 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
205 clock-names = "fin_pll", "mct";
208 pinctrl_1: pinctrl@11000000 {
209 compatible = "samsung,exynos3250-pinctrl";
210 reg = <0x11000000 0x1000>;
211 interrupts = <0 225 0>;
213 wakeup-interrupt-controller {
214 compatible = "samsung,exynos4210-wakeup-eint";
215 interrupts = <0 48 0>;
219 pinctrl_0: pinctrl@11400000 {
220 compatible = "samsung,exynos3250-pinctrl";
221 reg = <0x11400000 0x1000>;
222 interrupts = <0 240 0>;
225 fimd: fimd@11c00000 {
226 compatible = "samsung,exynos3250-fimd";
227 reg = <0x11c00000 0x30000>;
228 interrupt-names = "fifo", "vsync", "lcd_sys";
229 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
230 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
231 clock-names = "sclk_fimd", "fimd";
232 samsung,power-domain = <&pd_lcd0>;
233 samsung,sysreg = <&sys_reg>;
237 dsi_0: dsi@11C80000 {
238 compatible = "samsung,exynos3250-mipi-dsi";
239 reg = <0x11C80000 0x10000>;
240 interrupts = <0 83 0>;
241 samsung,phy-type = <0>;
242 samsung,power-domain = <&pd_lcd0>;
243 phys = <&mipi_phy 1>;
245 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
246 clock-names = "bus_clk", "pll_clk";
247 #address-cells = <1>;
252 mshc_0: mshc@12510000 {
253 compatible = "samsung,exynos5250-dw-mshc";
254 reg = <0x12510000 0x1000>;
255 interrupts = <0 142 0>;
256 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
257 clock-names = "biu", "ciu";
259 #address-cells = <1>;
264 mshc_1: mshc@12520000 {
265 compatible = "samsung,exynos5250-dw-mshc";
266 reg = <0x12520000 0x1000>;
267 interrupts = <0 143 0>;
268 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
269 clock-names = "biu", "ciu";
271 #address-cells = <1>;
277 compatible = "arm,amba-bus";
278 #address-cells = <1>;
282 pdma0: pdma@12680000 {
283 compatible = "arm,pl330", "arm,primecell";
284 reg = <0x12680000 0x1000>;
285 interrupts = <0 138 0>;
286 clocks = <&cmu CLK_PDMA0>;
287 clock-names = "apb_pclk";
290 #dma-requests = <32>;
293 pdma1: pdma@12690000 {
294 compatible = "arm,pl330", "arm,primecell";
295 reg = <0x12690000 0x1000>;
296 interrupts = <0 139 0>;
297 clocks = <&cmu CLK_PDMA1>;
298 clock-names = "apb_pclk";
301 #dma-requests = <32>;
306 compatible = "samsung,exynos3250-adc",
307 "samsung,exynos-adc-v2";
308 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
309 interrupts = <0 137 0>;
310 clock-names = "adc", "sclk";
311 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
312 #io-channel-cells = <1>;
317 serial_0: serial@13800000 {
318 compatible = "samsung,exynos4210-uart";
319 reg = <0x13800000 0x100>;
320 interrupts = <0 109 0>;
321 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
322 clock-names = "uart", "clk_uart_baud0";
323 pinctrl-names = "default";
324 pinctrl-0 = <&uart0_data &uart0_fctl>;
328 serial_1: serial@13810000 {
329 compatible = "samsung,exynos4210-uart";
330 reg = <0x13810000 0x100>;
331 interrupts = <0 110 0>;
332 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
333 clock-names = "uart", "clk_uart_baud0";
334 pinctrl-names = "default";
335 pinctrl-0 = <&uart1_data>;
339 i2c_0: i2c@13860000 {
340 #address-cells = <1>;
342 compatible = "samsung,s3c2440-i2c";
343 reg = <0x13860000 0x100>;
344 interrupts = <0 113 0>;
345 clocks = <&cmu CLK_I2C0>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c0_bus>;
352 i2c_1: i2c@13870000 {
353 #address-cells = <1>;
355 compatible = "samsung,s3c2440-i2c";
356 reg = <0x13870000 0x100>;
357 interrupts = <0 114 0>;
358 clocks = <&cmu CLK_I2C1>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c1_bus>;
365 i2c_2: i2c@13880000 {
366 #address-cells = <1>;
368 compatible = "samsung,s3c2440-i2c";
369 reg = <0x13880000 0x100>;
370 interrupts = <0 115 0>;
371 clocks = <&cmu CLK_I2C2>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&i2c2_bus>;
378 i2c_3: i2c@13890000 {
379 #address-cells = <1>;
381 compatible = "samsung,s3c2440-i2c";
382 reg = <0x13890000 0x100>;
383 interrupts = <0 116 0>;
384 clocks = <&cmu CLK_I2C3>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&i2c3_bus>;
391 i2c_4: i2c@138A0000 {
392 #address-cells = <1>;
394 compatible = "samsung,s3c2440-i2c";
395 reg = <0x138A0000 0x100>;
396 interrupts = <0 117 0>;
397 clocks = <&cmu CLK_I2C4>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c4_bus>;
404 i2c_5: i2c@138B0000 {
405 #address-cells = <1>;
407 compatible = "samsung,s3c2440-i2c";
408 reg = <0x138B0000 0x100>;
409 interrupts = <0 118 0>;
410 clocks = <&cmu CLK_I2C5>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&i2c5_bus>;
417 i2c_6: i2c@138C0000 {
418 #address-cells = <1>;
420 compatible = "samsung,s3c2440-i2c";
421 reg = <0x138C0000 0x100>;
422 interrupts = <0 119 0>;
423 clocks = <&cmu CLK_I2C6>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&i2c6_bus>;
430 i2c_7: i2c@138D0000 {
431 #address-cells = <1>;
433 compatible = "samsung,s3c2440-i2c";
434 reg = <0x138D0000 0x100>;
435 interrupts = <0 120 0>;
436 clocks = <&cmu CLK_I2C7>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&i2c7_bus>;
443 spi_0: spi@13920000 {
444 compatible = "samsung,exynos4210-spi";
445 reg = <0x13920000 0x100>;
446 interrupts = <0 121 0>;
447 dmas = <&pdma0 7>, <&pdma0 6>;
448 dma-names = "tx", "rx";
449 #address-cells = <1>;
451 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
452 clock-names = "spi", "spi_busclk0";
453 samsung,spi-src-clk = <0>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&spi0_bus>;
459 spi_1: spi@13930000 {
460 compatible = "samsung,exynos4210-spi";
461 reg = <0x13930000 0x100>;
462 interrupts = <0 122 0>;
463 dmas = <&pdma1 7>, <&pdma1 6>;
464 dma-names = "tx", "rx";
465 #address-cells = <1>;
467 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
468 clock-names = "spi", "spi_busclk0";
469 samsung,spi-src-clk = <0>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&spi1_bus>;
476 compatible = "samsung,s3c6410-i2s";
477 reg = <0x13970000 0x100>;
478 interrupts = <0 126 0>;
479 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
480 clock-names = "iis", "i2s_opclk0";
481 dmas = <&pdma0 14>, <&pdma0 13>;
482 dma-names = "tx", "rx";
483 pinctrl-0 = <&i2s2_bus>;
484 pinctrl-names = "default";
489 compatible = "samsung,exynos4210-pwm";
490 reg = <0x139D0000 0x1000>;
491 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
492 <0 107 0>, <0 108 0>;
498 compatible = "arm,cortex-a7-pmu";
499 interrupts = <0 18 0>, <0 19 0>;
504 #include "exynos3250-pinctrl.dtsi"