Merge branch 'for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq
[linux-2.6-microblaze.git] / arch / arm / boot / dts / exynos3250.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Samsung's Exynos3250 SoC device tree source
4  *
5  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6  *              http://www.samsung.com
7  *
8  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9  * based board files can include this file and provide values for board specfic
10  * bindings.
11  *
12  * Note: This file does not include device nodes for all the controllers in
13  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14  * nodes can be added to this file.
15  */
16
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
21
22 / {
23         compatible = "samsung,exynos3250";
24         interrupt-parent = <&gic>;
25         #address-cells = <1>;
26         #size-cells = <1>;
27
28         aliases {
29                 pinctrl0 = &pinctrl_0;
30                 pinctrl1 = &pinctrl_1;
31                 mshc0 = &mshc_0;
32                 mshc1 = &mshc_1;
33                 mshc2 = &mshc_2;
34                 spi0 = &spi_0;
35                 spi1 = &spi_1;
36                 i2c0 = &i2c_0;
37                 i2c1 = &i2c_1;
38                 i2c2 = &i2c_2;
39                 i2c3 = &i2c_3;
40                 i2c4 = &i2c_4;
41                 i2c5 = &i2c_5;
42                 i2c6 = &i2c_6;
43                 i2c7 = &i2c_7;
44                 serial0 = &serial_0;
45                 serial1 = &serial_1;
46                 serial2 = &serial_2;
47         };
48
49         cpus {
50                 #address-cells = <1>;
51                 #size-cells = <0>;
52
53                 cpu0: cpu@0 {
54                         device_type = "cpu";
55                         compatible = "arm,cortex-a7";
56                         reg = <0>;
57                         clock-frequency = <1000000000>;
58                         clocks = <&cmu CLK_ARM_CLK>;
59                         clock-names = "cpu";
60                         #cooling-cells = <2>;
61
62                         operating-points = <
63                                 1000000 1150000
64                                 900000  1112500
65                                 800000  1075000
66                                 700000  1037500
67                                 600000  1000000
68                                 500000  962500
69                                 400000  925000
70                                 300000  887500
71                                 200000  850000
72                                 100000  850000
73                         >;
74                 };
75
76                 cpu1: cpu@1 {
77                         device_type = "cpu";
78                         compatible = "arm,cortex-a7";
79                         reg = <1>;
80                         clock-frequency = <1000000000>;
81                         clocks = <&cmu CLK_ARM_CLK>;
82                         clock-names = "cpu";
83                         #cooling-cells = <2>;
84
85                         operating-points = <
86                                 1000000 1150000
87                                 900000  1112500
88                                 800000  1075000
89                                 700000  1037500
90                                 600000  1000000
91                                 500000  962500
92                                 400000  925000
93                                 300000  887500
94                                 200000  850000
95                                 100000  850000
96                         >;
97                 };
98         };
99
100         xusbxti: clock-0 {
101                 compatible = "fixed-clock";
102                 clock-frequency = <0>;
103                 #clock-cells = <0>;
104                 clock-output-names = "xusbxti";
105         };
106
107         xxti: clock-1 {
108                 compatible = "fixed-clock";
109                 clock-frequency = <0>;
110                 #clock-cells = <0>;
111                 clock-output-names = "xxti";
112         };
113
114         xtcxo: clock-2 {
115                 compatible = "fixed-clock";
116                 clock-frequency = <0>;
117                 #clock-cells = <0>;
118                 clock-output-names = "xtcxo";
119         };
120
121         pmu {
122                 compatible = "arm,cortex-a7-pmu";
123                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
124                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
125         };
126
127         soc: soc {
128                 compatible = "simple-bus";
129                 #address-cells = <1>;
130                 #size-cells = <1>;
131                 ranges;
132
133                 sram@2020000 {
134                         compatible = "mmio-sram";
135                         reg = <0x02020000 0x40000>;
136                         #address-cells = <1>;
137                         #size-cells = <1>;
138                         ranges = <0 0x02020000 0x40000>;
139
140                         smp-sram@0 {
141                                 compatible = "samsung,exynos4210-sysram";
142                                 reg = <0x0 0x1000>;
143                         };
144
145                         smp-sram@3f000 {
146                                 compatible = "samsung,exynos4210-sysram-ns";
147                                 reg = <0x3f000 0x1000>;
148                         };
149                 };
150
151                 chipid@10000000 {
152                         compatible = "samsung,exynos4210-chipid";
153                         reg = <0x10000000 0x100>;
154                 };
155
156                 sys_reg: syscon@10010000 {
157                         compatible = "samsung,exynos3-sysreg", "syscon";
158                         reg = <0x10010000 0x400>;
159                 };
160
161                 pmu_system_controller: system-controller@10020000 {
162                         compatible = "samsung,exynos3250-pmu", "syscon";
163                         reg = <0x10020000 0x4000>;
164                         interrupt-controller;
165                         #interrupt-cells = <3>;
166                         interrupt-parent = <&gic>;
167                         clock-names = "clkout8";
168                         clocks = <&cmu CLK_FIN_PLL>;
169                         #clock-cells = <1>;
170                 };
171
172                 mipi_phy: video-phy {
173                         compatible = "samsung,s5pv210-mipi-video-phy";
174                         #phy-cells = <1>;
175                         syscon = <&pmu_system_controller>;
176                 };
177
178                 pd_cam: power-domain@10023c00 {
179                         compatible = "samsung,exynos4210-pd";
180                         reg = <0x10023C00 0x20>;
181                         #power-domain-cells = <0>;
182                         label = "CAM";
183                 };
184
185                 pd_mfc: power-domain@10023c40 {
186                         compatible = "samsung,exynos4210-pd";
187                         reg = <0x10023C40 0x20>;
188                         #power-domain-cells = <0>;
189                         label = "MFC";
190                 };
191
192                 pd_g3d: power-domain@10023c60 {
193                         compatible = "samsung,exynos4210-pd";
194                         reg = <0x10023C60 0x20>;
195                         #power-domain-cells = <0>;
196                         label = "G3D";
197                 };
198
199                 pd_lcd0: power-domain@10023c80 {
200                         compatible = "samsung,exynos4210-pd";
201                         reg = <0x10023C80 0x20>;
202                         #power-domain-cells = <0>;
203                         label = "LCD0";
204                 };
205
206                 pd_isp: power-domain@10023ca0 {
207                         compatible = "samsung,exynos4210-pd";
208                         reg = <0x10023CA0 0x20>;
209                         #power-domain-cells = <0>;
210                         label = "ISP";
211                 };
212
213                 cmu: clock-controller@10030000 {
214                         compatible = "samsung,exynos3250-cmu";
215                         reg = <0x10030000 0x20000>;
216                         #clock-cells = <1>;
217                         assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
218                                           <&cmu CLK_MOUT_ACLK_266_SUB>;
219                         assigned-clock-parents = <&cmu CLK_FIN_PLL>,
220                                                  <&cmu CLK_FIN_PLL>;
221                 };
222
223                 cmu_dmc: clock-controller@105c0000 {
224                         compatible = "samsung,exynos3250-cmu-dmc";
225                         reg = <0x105C0000 0x2000>;
226                         #clock-cells = <1>;
227                 };
228
229                 rtc: rtc@10070000 {
230                         compatible = "samsung,s3c6410-rtc";
231                         reg = <0x10070000 0x100>;
232                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
233                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
234                         interrupt-parent = <&pmu_system_controller>;
235                         status = "disabled";
236                 };
237
238                 tmu: tmu@100c0000 {
239                         compatible = "samsung,exynos3250-tmu";
240                         reg = <0x100C0000 0x100>;
241                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
242                         clocks = <&cmu CLK_TMU_APBIF>;
243                         clock-names = "tmu_apbif";
244                         #thermal-sensor-cells = <0>;
245                         status = "disabled";
246                 };
247
248                 gic: interrupt-controller@10481000 {
249                         compatible = "arm,cortex-a15-gic";
250                         #interrupt-cells = <3>;
251                         interrupt-controller;
252                         reg = <0x10481000 0x1000>,
253                               <0x10482000 0x2000>,
254                               <0x10484000 0x2000>,
255                               <0x10486000 0x2000>;
256                         interrupts = <GIC_PPI 9
257                                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
258                 };
259
260                 timer@10050000 {
261                         compatible = "samsung,exynos4210-mct";
262                         reg = <0x10050000 0x800>;
263                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
264                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
265                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
266                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
267                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
268                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
269                                      <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
270                                      <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
271                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
272                         clock-names = "fin_pll", "mct";
273                 };
274
275                 pinctrl_1: pinctrl@11000000 {
276                         compatible = "samsung,exynos3250-pinctrl";
277                         reg = <0x11000000 0x1000>;
278                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
279
280                         wakeup-interrupt-controller {
281                                 compatible = "samsung,exynos4210-wakeup-eint";
282                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
283                         };
284                 };
285
286                 pinctrl_0: pinctrl@11400000 {
287                         compatible = "samsung,exynos3250-pinctrl";
288                         reg = <0x11400000 0x1000>;
289                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
290                 };
291
292                 jpeg: codec@11830000 {
293                         compatible = "samsung,exynos3250-jpeg";
294                         reg = <0x11830000 0x1000>;
295                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
296                         clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
297                         clock-names = "jpeg", "sclk";
298                         power-domains = <&pd_cam>;
299                         assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
300                         assigned-clock-rates = <0>, <150000000>;
301                         assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
302                         iommus = <&sysmmu_jpeg>;
303                         status = "disabled";
304                 };
305
306                 sysmmu_jpeg: sysmmu@11a60000 {
307                         compatible = "samsung,exynos-sysmmu";
308                         reg = <0x11a60000 0x1000>;
309                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
310                         clock-names = "sysmmu", "master";
311                         clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
312                         power-domains = <&pd_cam>;
313                         #iommu-cells = <0>;
314                 };
315
316                 fimd: fimd@11c00000 {
317                         compatible = "samsung,exynos3250-fimd";
318                         reg = <0x11c00000 0x30000>;
319                         interrupt-names = "fifo", "vsync", "lcd_sys";
320                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
321                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
322                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
323                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
324                         clock-names = "sclk_fimd", "fimd";
325                         power-domains = <&pd_lcd0>;
326                         iommus = <&sysmmu_fimd0>;
327                         samsung,sysreg = <&sys_reg>;
328                         status = "disabled";
329                 };
330
331                 dsi_0: dsi@11c80000 {
332                         compatible = "samsung,exynos3250-mipi-dsi";
333                         reg = <0x11C80000 0x10000>;
334                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
335                         samsung,phy-type = <0>;
336                         power-domains = <&pd_lcd0>;
337                         phys = <&mipi_phy 1>;
338                         phy-names = "dsim";
339                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
340                         clock-names = "bus_clk", "pll_clk";
341                         #address-cells = <1>;
342                         #size-cells = <0>;
343                         status = "disabled";
344                 };
345
346                 sysmmu_fimd0: sysmmu@11e20000 {
347                         compatible = "samsung,exynos-sysmmu";
348                         reg = <0x11e20000 0x1000>;
349                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
350                         clock-names = "sysmmu", "master";
351                         clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
352                         power-domains = <&pd_lcd0>;
353                         #iommu-cells = <0>;
354                 };
355
356                 hsotg: hsotg@12480000 {
357                         compatible = "samsung,s3c6400-hsotg";
358                         reg = <0x12480000 0x20000>;
359                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
360                         clocks = <&cmu CLK_USBOTG>;
361                         clock-names = "otg";
362                         phys = <&exynos_usbphy 0>;
363                         phy-names = "usb2-phy";
364                         status = "disabled";
365                 };
366
367                 mshc_0: mshc@12510000 {
368                         compatible = "samsung,exynos5420-dw-mshc";
369                         reg = <0x12510000 0x1000>;
370                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
371                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
372                         clock-names = "biu", "ciu";
373                         fifo-depth = <0x80>;
374                         #address-cells = <1>;
375                         #size-cells = <0>;
376                         status = "disabled";
377                 };
378
379                 mshc_1: mshc@12520000 {
380                         compatible = "samsung,exynos5420-dw-mshc";
381                         reg = <0x12520000 0x1000>;
382                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
383                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
384                         clock-names = "biu", "ciu";
385                         fifo-depth = <0x80>;
386                         #address-cells = <1>;
387                         #size-cells = <0>;
388                         status = "disabled";
389                 };
390
391                 mshc_2: mshc@12530000 {
392                         compatible = "samsung,exynos5250-dw-mshc";
393                         reg = <0x12530000 0x1000>;
394                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
395                         clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
396                         clock-names = "biu", "ciu";
397                         fifo-depth = <0x80>;
398                         #address-cells = <1>;
399                         #size-cells = <0>;
400                         status = "disabled";
401                 };
402
403                 exynos_usbphy: exynos-usbphy@125b0000 {
404                         compatible = "samsung,exynos3250-usb2-phy";
405                         reg = <0x125B0000 0x100>;
406                         samsung,pmureg-phandle = <&pmu_system_controller>;
407                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
408                         clock-names = "phy", "ref";
409                         #phy-cells = <1>;
410                         status = "disabled";
411                 };
412
413                 pdma0: pdma@12680000 {
414                         compatible = "arm,pl330", "arm,primecell";
415                         reg = <0x12680000 0x1000>;
416                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
417                         clocks = <&cmu CLK_PDMA0>;
418                         clock-names = "apb_pclk";
419                         #dma-cells = <1>;
420                         #dma-channels = <8>;
421                         #dma-requests = <32>;
422                 };
423
424                 pdma1: pdma@12690000 {
425                         compatible = "arm,pl330", "arm,primecell";
426                         reg = <0x12690000 0x1000>;
427                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
428                         clocks = <&cmu CLK_PDMA1>;
429                         clock-names = "apb_pclk";
430                         #dma-cells = <1>;
431                         #dma-channels = <8>;
432                         #dma-requests = <32>;
433                 };
434
435                 adc: adc@126c0000 {
436                         compatible = "samsung,exynos3250-adc";
437                         reg = <0x126C0000 0x100>;
438                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
439                         clock-names = "adc", "sclk";
440                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
441                         #io-channel-cells = <1>;
442                         samsung,syscon-phandle = <&pmu_system_controller>;
443                         status = "disabled";
444                 };
445
446                 gpu: gpu@13000000 {
447                         compatible = "samsung,exynos4210-mali", "arm,mali-400";
448                         reg = <0x13000000 0x10000>;
449                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
450                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
451                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
452                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
453                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
454                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
455                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
456                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
457                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
458                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
459                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
460                         interrupt-names = "gp",
461                                           "gpmmu",
462                                           "pp0",
463                                           "ppmmu0",
464                                           "pp1",
465                                           "ppmmu1",
466                                           "pp2",
467                                           "ppmmu2",
468                                           "pp3",
469                                           "ppmmu3",
470                                           "pmu";
471                         clocks = <&cmu CLK_G3D>,
472                                  <&cmu CLK_SCLK_G3D>;
473                         clock-names = "bus", "core";
474                         power-domains = <&pd_g3d>;
475                         status = "disabled";
476                         /* TODO: operating points for DVFS, assigned clock as 134 MHz */
477                 };
478
479                 mfc: codec@13400000 {
480                         compatible = "samsung,mfc-v7";
481                         reg = <0x13400000 0x10000>;
482                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
483                         clock-names = "mfc", "sclk_mfc";
484                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
485                         power-domains = <&pd_mfc>;
486                         iommus = <&sysmmu_mfc>;
487                 };
488
489                 sysmmu_mfc: sysmmu@13620000 {
490                         compatible = "samsung,exynos-sysmmu";
491                         reg = <0x13620000 0x1000>;
492                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
493                         clock-names = "sysmmu", "master";
494                         clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
495                         power-domains = <&pd_mfc>;
496                         #iommu-cells = <0>;
497                 };
498
499                 serial_0: serial@13800000 {
500                         compatible = "samsung,exynos4210-uart";
501                         reg = <0x13800000 0x100>;
502                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
503                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
504                         clock-names = "uart", "clk_uart_baud0";
505                         pinctrl-names = "default";
506                         pinctrl-0 = <&uart0_data &uart0_fctl>;
507                         status = "disabled";
508                 };
509
510                 serial_1: serial@13810000 {
511                         compatible = "samsung,exynos4210-uart";
512                         reg = <0x13810000 0x100>;
513                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
514                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
515                         clock-names = "uart", "clk_uart_baud0";
516                         pinctrl-names = "default";
517                         pinctrl-0 = <&uart1_data>;
518                         status = "disabled";
519                 };
520
521                 serial_2: serial@13820000 {
522                         compatible = "samsung,exynos4210-uart";
523                         reg = <0x13820000 0x100>;
524                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
525                         clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
526                         clock-names = "uart", "clk_uart_baud0";
527                         pinctrl-names = "default";
528                         pinctrl-0 = <&uart2_data>;
529                         status = "disabled";
530                 };
531
532                 i2c_0: i2c@13860000 {
533                         #address-cells = <1>;
534                         #size-cells = <0>;
535                         compatible = "samsung,s3c2440-i2c";
536                         reg = <0x13860000 0x100>;
537                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
538                         clocks = <&cmu CLK_I2C0>;
539                         clock-names = "i2c";
540                         pinctrl-names = "default";
541                         pinctrl-0 = <&i2c0_bus>;
542                         status = "disabled";
543                 };
544
545                 i2c_1: i2c@13870000 {
546                         #address-cells = <1>;
547                         #size-cells = <0>;
548                         compatible = "samsung,s3c2440-i2c";
549                         reg = <0x13870000 0x100>;
550                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
551                         clocks = <&cmu CLK_I2C1>;
552                         clock-names = "i2c";
553                         pinctrl-names = "default";
554                         pinctrl-0 = <&i2c1_bus>;
555                         status = "disabled";
556                 };
557
558                 i2c_2: i2c@13880000 {
559                         #address-cells = <1>;
560                         #size-cells = <0>;
561                         compatible = "samsung,s3c2440-i2c";
562                         reg = <0x13880000 0x100>;
563                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
564                         clocks = <&cmu CLK_I2C2>;
565                         clock-names = "i2c";
566                         pinctrl-names = "default";
567                         pinctrl-0 = <&i2c2_bus>;
568                         status = "disabled";
569                 };
570
571                 i2c_3: i2c@13890000 {
572                         #address-cells = <1>;
573                         #size-cells = <0>;
574                         compatible = "samsung,s3c2440-i2c";
575                         reg = <0x13890000 0x100>;
576                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
577                         clocks = <&cmu CLK_I2C3>;
578                         clock-names = "i2c";
579                         pinctrl-names = "default";
580                         pinctrl-0 = <&i2c3_bus>;
581                         status = "disabled";
582                 };
583
584                 i2c_4: i2c@138a0000 {
585                         #address-cells = <1>;
586                         #size-cells = <0>;
587                         compatible = "samsung,s3c2440-i2c";
588                         reg = <0x138A0000 0x100>;
589                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
590                         clocks = <&cmu CLK_I2C4>;
591                         clock-names = "i2c";
592                         pinctrl-names = "default";
593                         pinctrl-0 = <&i2c4_bus>;
594                         status = "disabled";
595                 };
596
597                 i2c_5: i2c@138b0000 {
598                         #address-cells = <1>;
599                         #size-cells = <0>;
600                         compatible = "samsung,s3c2440-i2c";
601                         reg = <0x138B0000 0x100>;
602                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
603                         clocks = <&cmu CLK_I2C5>;
604                         clock-names = "i2c";
605                         pinctrl-names = "default";
606                         pinctrl-0 = <&i2c5_bus>;
607                         status = "disabled";
608                 };
609
610                 i2c_6: i2c@138c0000 {
611                         #address-cells = <1>;
612                         #size-cells = <0>;
613                         compatible = "samsung,s3c2440-i2c";
614                         reg = <0x138C0000 0x100>;
615                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
616                         clocks = <&cmu CLK_I2C6>;
617                         clock-names = "i2c";
618                         pinctrl-names = "default";
619                         pinctrl-0 = <&i2c6_bus>;
620                         status = "disabled";
621                 };
622
623                 i2c_7: i2c@138d0000 {
624                         #address-cells = <1>;
625                         #size-cells = <0>;
626                         compatible = "samsung,s3c2440-i2c";
627                         reg = <0x138D0000 0x100>;
628                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
629                         clocks = <&cmu CLK_I2C7>;
630                         clock-names = "i2c";
631                         pinctrl-names = "default";
632                         pinctrl-0 = <&i2c7_bus>;
633                         status = "disabled";
634                 };
635
636                 spi_0: spi@13920000 {
637                         compatible = "samsung,exynos4210-spi";
638                         reg = <0x13920000 0x100>;
639                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
640                         dmas = <&pdma0 7>, <&pdma0 6>;
641                         dma-names = "tx", "rx";
642                         #address-cells = <1>;
643                         #size-cells = <0>;
644                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
645                         clock-names = "spi", "spi_busclk0";
646                         samsung,spi-src-clk = <0>;
647                         pinctrl-names = "default";
648                         pinctrl-0 = <&spi0_bus>;
649                         status = "disabled";
650                 };
651
652                 spi_1: spi@13930000 {
653                         compatible = "samsung,exynos4210-spi";
654                         reg = <0x13930000 0x100>;
655                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
656                         dmas = <&pdma1 7>, <&pdma1 6>;
657                         dma-names = "tx", "rx";
658                         #address-cells = <1>;
659                         #size-cells = <0>;
660                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
661                         clock-names = "spi", "spi_busclk0";
662                         samsung,spi-src-clk = <0>;
663                         pinctrl-names = "default";
664                         pinctrl-0 = <&spi1_bus>;
665                         status = "disabled";
666                 };
667
668                 i2s2: i2s@13970000 {
669                         compatible = "samsung,s3c6410-i2s";
670                         reg = <0x13970000 0x100>;
671                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
672                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
673                         clock-names = "iis", "i2s_opclk0";
674                         dmas = <&pdma0 14>, <&pdma0 13>;
675                         dma-names = "tx", "rx";
676                         pinctrl-0 = <&i2s2_bus>;
677                         pinctrl-names = "default";
678                         status = "disabled";
679                 };
680
681                 pwm: pwm@139d0000 {
682                         compatible = "samsung,exynos4210-pwm";
683                         reg = <0x139D0000 0x1000>;
684                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
685                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
686                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
687                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
688                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
689                         #pwm-cells = <3>;
690                         status = "disabled";
691                 };
692
693                 ppmu_dmc0: ppmu@106a0000 {
694                         compatible = "samsung,exynos-ppmu";
695                         reg = <0x106a0000 0x2000>;
696                         status = "disabled";
697                 };
698
699                 ppmu_dmc1: ppmu@106b0000 {
700                         compatible = "samsung,exynos-ppmu";
701                         reg = <0x106b0000 0x2000>;
702                         status = "disabled";
703                 };
704
705                 ppmu_cpu: ppmu@106c0000 {
706                         compatible = "samsung,exynos-ppmu";
707                         reg = <0x106c0000 0x2000>;
708                         status = "disabled";
709                 };
710
711                 ppmu_rightbus: ppmu@112a0000 {
712                         compatible = "samsung,exynos-ppmu";
713                         reg = <0x112a0000 0x2000>;
714                         clocks = <&cmu CLK_PPMURIGHT>;
715                         clock-names = "ppmu";
716                         status = "disabled";
717                 };
718
719                 ppmu_leftbus: ppmu@116a0000 {
720                         compatible = "samsung,exynos-ppmu";
721                         reg = <0x116a0000 0x2000>;
722                         clocks = <&cmu CLK_PPMULEFT>;
723                         clock-names = "ppmu";
724                         status = "disabled";
725                 };
726
727                 ppmu_camif: ppmu@11ac0000 {
728                         compatible = "samsung,exynos-ppmu";
729                         reg = <0x11ac0000 0x2000>;
730                         clocks = <&cmu CLK_PPMUCAMIF>;
731                         clock-names = "ppmu";
732                         status = "disabled";
733                 };
734
735                 ppmu_lcd0: ppmu@11e40000 {
736                         compatible = "samsung,exynos-ppmu";
737                         reg = <0x11e40000 0x2000>;
738                         clocks = <&cmu CLK_PPMULCD0>;
739                         clock-names = "ppmu";
740                         status = "disabled";
741                 };
742
743                 ppmu_fsys: ppmu@12630000 {
744                         compatible = "samsung,exynos-ppmu";
745                         reg = <0x12630000 0x2000>;
746                         clocks = <&cmu CLK_PPMUFILE>;
747                         clock-names = "ppmu";
748                         status = "disabled";
749                 };
750
751                 ppmu_g3d: ppmu@13220000 {
752                         compatible = "samsung,exynos-ppmu";
753                         reg = <0x13220000 0x2000>;
754                         clocks = <&cmu CLK_PPMUG3D>;
755                         clock-names = "ppmu";
756                         status = "disabled";
757                 };
758
759                 ppmu_mfc: ppmu@13660000 {
760                         compatible = "samsung,exynos-ppmu";
761                         reg = <0x13660000 0x2000>;
762                         clocks = <&cmu CLK_PPMUMFC_L>;
763                         clock-names = "ppmu";
764                         status = "disabled";
765                 };
766
767                 bus_dmc: bus-dmc {
768                         compatible = "samsung,exynos-bus";
769                         clocks = <&cmu_dmc CLK_DIV_DMC>;
770                         clock-names = "bus";
771                         operating-points-v2 = <&bus_dmc_opp_table>;
772                         status = "disabled";
773                 };
774
775                 bus_dmc_opp_table: opp-table1 {
776                         compatible = "operating-points-v2";
777
778                         opp-50000000 {
779                                 opp-hz = /bits/ 64 <50000000>;
780                                 opp-microvolt = <800000>;
781                         };
782                         opp-100000000 {
783                                 opp-hz = /bits/ 64 <100000000>;
784                                 opp-microvolt = <800000>;
785                         };
786                         opp-134000000 {
787                                 opp-hz = /bits/ 64 <134000000>;
788                                 opp-microvolt = <800000>;
789                         };
790                         opp-200000000 {
791                                 opp-hz = /bits/ 64 <200000000>;
792                                 opp-microvolt = <825000>;
793                         };
794                         opp-400000000 {
795                                 opp-hz = /bits/ 64 <400000000>;
796                                 opp-microvolt = <875000>;
797                         };
798                 };
799
800                 bus_leftbus: bus-leftbus {
801                         compatible = "samsung,exynos-bus";
802                         clocks = <&cmu CLK_DIV_GDL>;
803                         clock-names = "bus";
804                         operating-points-v2 = <&bus_leftbus_opp_table>;
805                         status = "disabled";
806                 };
807
808                 bus_rightbus: bus-rightbus {
809                         compatible = "samsung,exynos-bus";
810                         clocks = <&cmu CLK_DIV_GDR>;
811                         clock-names = "bus";
812                         operating-points-v2 = <&bus_leftbus_opp_table>;
813                         status = "disabled";
814                 };
815
816                 bus_lcd0: bus-lcd0 {
817                         compatible = "samsung,exynos-bus";
818                         clocks = <&cmu CLK_DIV_ACLK_160>;
819                         clock-names = "bus";
820                         operating-points-v2 = <&bus_leftbus_opp_table>;
821                         status = "disabled";
822                 };
823
824                 bus_fsys: bus-fsys {
825                         compatible = "samsung,exynos-bus";
826                         clocks = <&cmu CLK_DIV_ACLK_200>;
827                         clock-names = "bus";
828                         operating-points-v2 = <&bus_leftbus_opp_table>;
829                         status = "disabled";
830                 };
831
832                 bus_mcuisp: bus-mcuisp {
833                         compatible = "samsung,exynos-bus";
834                         clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
835                         clock-names = "bus";
836                         operating-points-v2 = <&bus_mcuisp_opp_table>;
837                         status = "disabled";
838                 };
839
840                 bus_isp: bus-isp {
841                         compatible = "samsung,exynos-bus";
842                         clocks = <&cmu CLK_DIV_ACLK_266>;
843                         clock-names = "bus";
844                         operating-points-v2 = <&bus_isp_opp_table>;
845                         status = "disabled";
846                 };
847
848                 bus_peril: bus-peril {
849                         compatible = "samsung,exynos-bus";
850                         clocks = <&cmu CLK_DIV_ACLK_100>;
851                         clock-names = "bus";
852                         operating-points-v2 = <&bus_peril_opp_table>;
853                         status = "disabled";
854                 };
855
856                 bus_mfc: bus-mfc {
857                         compatible = "samsung,exynos-bus";
858                         clocks = <&cmu CLK_SCLK_MFC>;
859                         clock-names = "bus";
860                         operating-points-v2 = <&bus_leftbus_opp_table>;
861                         status = "disabled";
862                 };
863
864                 bus_leftbus_opp_table: opp-table2 {
865                         compatible = "operating-points-v2";
866
867                         opp-50000000 {
868                                 opp-hz = /bits/ 64 <50000000>;
869                                 opp-microvolt = <900000>;
870                         };
871                         opp-80000000 {
872                                 opp-hz = /bits/ 64 <80000000>;
873                                 opp-microvolt = <900000>;
874                         };
875                         opp-100000000 {
876                                 opp-hz = /bits/ 64 <100000000>;
877                                 opp-microvolt = <1000000>;
878                         };
879                         opp-134000000 {
880                                 opp-hz = /bits/ 64 <134000000>;
881                                 opp-microvolt = <1000000>;
882                         };
883                         opp-200000000 {
884                                 opp-hz = /bits/ 64 <200000000>;
885                                 opp-microvolt = <1000000>;
886                         };
887                 };
888
889                 bus_mcuisp_opp_table: opp-table3 {
890                         compatible = "operating-points-v2";
891
892                         opp-50000000 {
893                                 opp-hz = /bits/ 64 <50000000>;
894                         };
895                         opp-80000000 {
896                                 opp-hz = /bits/ 64 <80000000>;
897                         };
898                         opp-100000000 {
899                                 opp-hz = /bits/ 64 <100000000>;
900                         };
901                         opp-200000000 {
902                                 opp-hz = /bits/ 64 <200000000>;
903                         };
904                         opp-400000000 {
905                                 opp-hz = /bits/ 64 <400000000>;
906                         };
907                 };
908
909                 bus_isp_opp_table: opp-table4 {
910                         compatible = "operating-points-v2";
911
912                         opp-50000000 {
913                                 opp-hz = /bits/ 64 <50000000>;
914                         };
915                         opp-80000000 {
916                                 opp-hz = /bits/ 64 <80000000>;
917                         };
918                         opp-100000000 {
919                                 opp-hz = /bits/ 64 <100000000>;
920                         };
921                         opp-200000000 {
922                                 opp-hz = /bits/ 64 <200000000>;
923                         };
924                         opp-300000000 {
925                                 opp-hz = /bits/ 64 <300000000>;
926                         };
927                 };
928
929                 bus_peril_opp_table: opp-table5 {
930                         compatible = "operating-points-v2";
931
932                         opp-50000000 {
933                                 opp-hz = /bits/ 64 <50000000>;
934                         };
935                         opp-80000000 {
936                                 opp-hz = /bits/ 64 <80000000>;
937                         };
938                         opp-100000000 {
939                                 opp-hz = /bits/ 64 <100000000>;
940                         };
941                 };
942         };
943 };
944
945 #include "exynos3250-pinctrl.dtsi"
946 #include "exynos-syscon-restart.dtsi"