1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h>
8 interrupt-parent = <&gic>;
19 reg = <0x84000000 0xA00000>;
24 reg = <0x84B00000 0x100000>;
29 reg = <0x85000000 0x1A00000>;
32 npu_phyaddr@86B00000 {
34 reg = <0x86B00000 0x100000>;
39 reg = <0x86D00000 0x100000>;
44 compatible = "arm,psci-0.2";
65 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 clock-frequency = <80000000>;
69 next-level-cache = <&L2_0>;
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 clock-frequency = <80000000>;
78 next-level-cache = <&L2_0>;
86 gic: interrupt-controller@9000000 {
87 compatible = "arm,gic-v3";
89 #interrupt-cells = <3>;
92 reg = <0x09000000 0x20000>,
97 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
101 compatible = "arm,armv8-timer";
102 interrupt-parent = <&gic>;
103 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
104 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
105 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
106 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
109 uart1: serial@1fbf0000 {
110 compatible = "ns16550";
111 reg = <0x1fbf0000 0x30>;
114 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
115 clock-frequency = <1843200>;
119 gpio0: gpio@1fbf0200 {
120 compatible = "airoha,en7523-gpio";
121 reg = <0x1fbf0204 0x4>,
129 gpio1: gpio@1fbf0270 {
130 compatible = "airoha,en7523-gpio";
131 reg = <0x1fbf0270 0x4>,