arch/arm/boot/dts/dra7xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for DRA7xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_core_aon_clocks {
  11         atl_clkin0_ck: atl_clkin0_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "ti,dra7-atl-clock";
  14                 clocks = <&atl_gfclk_mux>;
  15         };
  16
  17         atl_clkin1_ck: atl_clkin1_ck {
  18                 #clock-cells = <0>;
  19                 compatible = "ti,dra7-atl-clock";
  20                 clocks = <&atl_gfclk_mux>;
  21         };
  22
  23         atl_clkin2_ck: atl_clkin2_ck {
  24                 #clock-cells = <0>;
  25                 compatible = "ti,dra7-atl-clock";
  26                 clocks = <&atl_gfclk_mux>;
  27         };
  28
  29         atl_clkin3_ck: atl_clkin3_ck {
  30                 #clock-cells = <0>;
  31                 compatible = "ti,dra7-atl-clock";
  32                 clocks = <&atl_gfclk_mux>;
  33         };
  34
  35         hdmi_clkin_ck: hdmi_clkin_ck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-clock";
  38                 clock-frequency = <0>;
  39         };
  40
  41         mlb_clkin_ck: mlb_clkin_ck {
  42                 #clock-cells = <0>;
  43                 compatible = "fixed-clock";
  44                 clock-frequency = <0>;
  45         };
  46
  47         mlbp_clkin_ck: mlbp_clkin_ck {
  48                 #clock-cells = <0>;
  49                 compatible = "fixed-clock";
  50                 clock-frequency = <0>;
  51         };
  52
  53         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-clock";
  56                 clock-frequency = <100000000>;
  57         };
  58
  59         ref_clkin0_ck: ref_clkin0_ck {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <0>;
  63         };
  64
  65         ref_clkin1_ck: ref_clkin1_ck {
  66                 #clock-cells = <0>;
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <0>;
  69         };
  70
  71         ref_clkin2_ck: ref_clkin2_ck {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-clock";
  74                 clock-frequency = <0>;
  75         };
  76
  77         ref_clkin3_ck: ref_clkin3_ck {
  78                 #clock-cells = <0>;
  79                 compatible = "fixed-clock";
  80                 clock-frequency = <0>;
  81         };
  82
  83         rmii_clk_ck: rmii_clk_ck {
  84                 #clock-cells = <0>;
  85                 compatible = "fixed-clock";
  86                 clock-frequency = <0>;
  87         };
  88
  89         sdvenc_clkin_ck: sdvenc_clkin_ck {
  90                 #clock-cells = <0>;
  91                 compatible = "fixed-clock";
  92                 clock-frequency = <0>;
  93         };
  94
  95         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  96                 #clock-cells = <0>;
  97                 compatible = "fixed-clock";
  98                 clock-frequency = <32768>;
  99         };
 100
 101         sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 102                 #clock-cells = <0>;
 103                 compatible = "fixed-clock";
 104                 clock-frequency = <32768>;
 105         };
 106
 107         sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
 108                 #clock-cells = <0>;
 109                 compatible = "fixed-factor-clock";
 110                 clocks = <&sys_clkin1>;
 111                 clock-mult = <1>;
 112                 clock-div = <610>;
 113         };
 114
 115         virt_12000000_ck: virt_12000000_ck {
 116                 #clock-cells = <0>;
 117                 compatible = "fixed-clock";
 118                 clock-frequency = <12000000>;
 119         };
 120
 121         virt_13000000_ck: virt_13000000_ck {
 122                 #clock-cells = <0>;
 123                 compatible = "fixed-clock";
 124                 clock-frequency = <13000000>;
 125         };
 126
 127         virt_16800000_ck: virt_16800000_ck {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-clock";
 130                 clock-frequency = <16800000>;
 131         };
 132
 133         virt_19200000_ck: virt_19200000_ck {
 134                 #clock-cells = <0>;
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <19200000>;
 137         };
 138
 139         virt_20000000_ck: virt_20000000_ck {
 140                 #clock-cells = <0>;
 141                 compatible = "fixed-clock";
 142                 clock-frequency = <20000000>;
 143         };
 144
 145         virt_26000000_ck: virt_26000000_ck {
 146                 #clock-cells = <0>;
 147                 compatible = "fixed-clock";
 148                 clock-frequency = <26000000>;
 149         };
 150
 151         virt_27000000_ck: virt_27000000_ck {
 152                 #clock-cells = <0>;
 153                 compatible = "fixed-clock";
 154                 clock-frequency = <27000000>;
 155         };
 156
 157         virt_38400000_ck: virt_38400000_ck {
 158                 #clock-cells = <0>;
 159                 compatible = "fixed-clock";
 160                 clock-frequency = <38400000>;
 161         };
 162
 163         sys_clkin2: sys_clkin2 {
 164                 #clock-cells = <0>;
 165                 compatible = "fixed-clock";
 166                 clock-frequency = <22579200>;
 167         };
 168
 169         usb_otg_clkin_ck: usb_otg_clkin_ck {
 170                 #clock-cells = <0>;
 171                 compatible = "fixed-clock";
 172                 clock-frequency = <0>;
 173         };
 174
 175         video1_clkin_ck: video1_clkin_ck {
 176                 #clock-cells = <0>;
 177                 compatible = "fixed-clock";
 178                 clock-frequency = <0>;
 179         };
 180
 181         video1_m2_clkin_ck: video1_m2_clkin_ck {
 182                 #clock-cells = <0>;
 183                 compatible = "fixed-clock";
 184                 clock-frequency = <0>;
 185         };
 186
 187         video2_clkin_ck: video2_clkin_ck {
 188                 #clock-cells = <0>;
 189                 compatible = "fixed-clock";
 190                 clock-frequency = <0>;
 191         };
 192
 193         video2_m2_clkin_ck: video2_m2_clkin_ck {
 194                 #clock-cells = <0>;
 195                 compatible = "fixed-clock";
 196                 clock-frequency = <0>;
 197         };
 198
 199         dpll_abe_ck: dpll_abe_ck@1e0 {
 200                 #clock-cells = <0>;
 201                 compatible = "ti,omap4-dpll-m4xen-clock";
 202                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 203                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 204         };
 205
 206         dpll_abe_x2_ck: dpll_abe_x2_ck {
 207                 #clock-cells = <0>;
 208                 compatible = "ti,omap4-dpll-x2-clock";
 209                 clocks = <&dpll_abe_ck>;
 210         };
 211
 212         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 213                 #clock-cells = <0>;
 214                 compatible = "ti,divider-clock";
 215                 clocks = <&dpll_abe_x2_ck>;
 216                 ti,max-div = <31>;
 217                 ti,autoidle-shift = <8>;
 218                 reg = <0x01f0>;
 219                 ti,index-starts-at-one;
 220                 ti,invert-autoidle-bit;
 221         };
 222
 223         abe_clk: abe_clk@108 {
 224                 #clock-cells = <0>;
 225                 compatible = "ti,divider-clock";
 226                 clocks = <&dpll_abe_m2x2_ck>;
 227                 ti,max-div = <4>;
 228                 reg = <0x0108>;
 229                 ti,index-power-of-two;
 230         };
 231
 232         dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 233                 #clock-cells = <0>;
 234                 compatible = "ti,divider-clock";
 235                 clocks = <&dpll_abe_ck>;
 236                 ti,max-div = <31>;
 237                 ti,autoidle-shift = <8>;
 238                 reg = <0x01f0>;
 239                 ti,index-starts-at-one;
 240                 ti,invert-autoidle-bit;
 241         };
 242
 243         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 244                 #clock-cells = <0>;
 245                 compatible = "ti,divider-clock";
 246                 clocks = <&dpll_abe_x2_ck>;
 247                 ti,max-div = <31>;
 248                 ti,autoidle-shift = <8>;
 249                 reg = <0x01f4>;
 250                 ti,index-starts-at-one;
 251                 ti,invert-autoidle-bit;
 252         };
 253
 254         dpll_core_byp_mux: dpll_core_byp_mux@12c {
 255                 #clock-cells = <0>;
 256                 compatible = "ti,mux-clock";
 257                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 258                 ti,bit-shift = <23>;
 259                 reg = <0x012c>;
 260         };
 261
 262         dpll_core_ck: dpll_core_ck@120 {
 263                 #clock-cells = <0>;
 264                 compatible = "ti,omap4-dpll-core-clock";
 265                 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 266                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 267         };
 268
 269         dpll_core_x2_ck: dpll_core_x2_ck {
 270                 #clock-cells = <0>;
 271                 compatible = "ti,omap4-dpll-x2-clock";
 272                 clocks = <&dpll_core_ck>;
 273         };
 274
 275         dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 276                 #clock-cells = <0>;
 277                 compatible = "ti,divider-clock";
 278                 clocks = <&dpll_core_x2_ck>;
 279                 ti,max-div = <63>;
 280                 ti,autoidle-shift = <8>;
 281                 reg = <0x013c>;
 282                 ti,index-starts-at-one;
 283                 ti,invert-autoidle-bit;
 284         };
 285
 286         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 287                 #clock-cells = <0>;
 288                 compatible = "fixed-factor-clock";
 289                 clocks = <&dpll_core_h12x2_ck>;
 290                 clock-mult = <1>;
 291                 clock-div = <1>;
 292         };
 293
 294         dpll_mpu_ck: dpll_mpu_ck@160 {
 295                 #clock-cells = <0>;
 296                 compatible = "ti,omap5-mpu-dpll-clock";
 297                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 298                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 299         };
 300
 301         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 302                 #clock-cells = <0>;
 303                 compatible = "ti,divider-clock";
 304                 clocks = <&dpll_mpu_ck>;
 305                 ti,max-div = <31>;
 306                 ti,autoidle-shift = <8>;
 307                 reg = <0x0170>;
 308                 ti,index-starts-at-one;
 309                 ti,invert-autoidle-bit;
 310         };
 311
 312         mpu_dclk_div: mpu_dclk_div {
 313                 #clock-cells = <0>;
 314                 compatible = "fixed-factor-clock";
 315                 clocks = <&dpll_mpu_m2_ck>;
 316                 clock-mult = <1>;
 317                 clock-div = <1>;
 318         };
 319
 320         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 321                 #clock-cells = <0>;
 322                 compatible = "fixed-factor-clock";
 323                 clocks = <&dpll_core_h12x2_ck>;
 324                 clock-mult = <1>;
 325                 clock-div = <1>;
 326         };
 327
 328         dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 329                 #clock-cells = <0>;
 330                 compatible = "ti,mux-clock";
 331                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 332                 ti,bit-shift = <23>;
 333                 reg = <0x0240>;
 334         };
 335
 336         dpll_dsp_ck: dpll_dsp_ck@234 {
 337                 #clock-cells = <0>;
 338                 compatible = "ti,omap4-dpll-clock";
 339                 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 340                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 341         };
 342
 343         dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 344                 #clock-cells = <0>;
 345                 compatible = "ti,divider-clock";
 346                 clocks = <&dpll_dsp_ck>;
 347                 ti,max-div = <31>;
 348                 ti,autoidle-shift = <8>;
 349                 reg = <0x0244>;
 350                 ti,index-starts-at-one;
 351                 ti,invert-autoidle-bit;
 352         };
 353
 354         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 355                 #clock-cells = <0>;
 356                 compatible = "fixed-factor-clock";
 357                 clocks = <&dpll_core_h12x2_ck>;
 358                 clock-mult = <1>;
 359                 clock-div = <1>;
 360         };
 361
 362         dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 363                 #clock-cells = <0>;
 364                 compatible = "ti,mux-clock";
 365                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 366                 ti,bit-shift = <23>;
 367                 reg = <0x01ac>;
 368         };
 369
 370         dpll_iva_ck: dpll_iva_ck@1a0 {
 371                 #clock-cells = <0>;
 372                 compatible = "ti,omap4-dpll-clock";
 373                 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 374                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 375         };
 376
 377         dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 378                 #clock-cells = <0>;
 379                 compatible = "ti,divider-clock";
 380                 clocks = <&dpll_iva_ck>;
 381                 ti,max-div = <31>;
 382                 ti,autoidle-shift = <8>;
 383                 reg = <0x01b0>;
 384                 ti,index-starts-at-one;
 385                 ti,invert-autoidle-bit;
 386         };
 387
 388         iva_dclk: iva_dclk {
 389                 #clock-cells = <0>;
 390                 compatible = "fixed-factor-clock";
 391                 clocks = <&dpll_iva_m2_ck>;
 392                 clock-mult = <1>;
 393                 clock-div = <1>;
 394         };
 395
 396         dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 397                 #clock-cells = <0>;
 398                 compatible = "ti,mux-clock";
 399                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 400                 ti,bit-shift = <23>;
 401                 reg = <0x02e4>;
 402         };
 403
 404         dpll_gpu_ck: dpll_gpu_ck@2d8 {
 405                 #clock-cells = <0>;
 406                 compatible = "ti,omap4-dpll-clock";
 407                 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 408                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 409         };
 410
 411         dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 412                 #clock-cells = <0>;
 413                 compatible = "ti,divider-clock";
 414                 clocks = <&dpll_gpu_ck>;
 415                 ti,max-div = <31>;
 416                 ti,autoidle-shift = <8>;
 417                 reg = <0x02e8>;
 418                 ti,index-starts-at-one;
 419                 ti,invert-autoidle-bit;
 420         };
 421
 422         dpll_core_m2_ck: dpll_core_m2_ck@130 {
 423                 #clock-cells = <0>;
 424                 compatible = "ti,divider-clock";
 425                 clocks = <&dpll_core_ck>;
 426                 ti,max-div = <31>;
 427                 ti,autoidle-shift = <8>;
 428                 reg = <0x0130>;
 429                 ti,index-starts-at-one;
 430                 ti,invert-autoidle-bit;
 431         };
 432
 433         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 434                 #clock-cells = <0>;
 435                 compatible = "fixed-factor-clock";
 436                 clocks = <&dpll_core_m2_ck>;
 437                 clock-mult = <1>;
 438                 clock-div = <1>;
 439         };
 440
 441         dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 442                 #clock-cells = <0>;
 443                 compatible = "ti,mux-clock";
 444                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 445                 ti,bit-shift = <23>;
 446                 reg = <0x021c>;
 447         };
 448
 449         dpll_ddr_ck: dpll_ddr_ck@210 {
 450                 #clock-cells = <0>;
 451                 compatible = "ti,omap4-dpll-clock";
 452                 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 453                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 454         };
 455
 456         dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 457                 #clock-cells = <0>;
 458                 compatible = "ti,divider-clock";
 459                 clocks = <&dpll_ddr_ck>;
 460                 ti,max-div = <31>;
 461                 ti,autoidle-shift = <8>;
 462                 reg = <0x0220>;
 463                 ti,index-starts-at-one;
 464                 ti,invert-autoidle-bit;
 465         };
 466
 467         dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 468                 #clock-cells = <0>;
 469                 compatible = "ti,mux-clock";
 470                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 471                 ti,bit-shift = <23>;
 472                 reg = <0x02b4>;
 473         };
 474
 475         dpll_gmac_ck: dpll_gmac_ck@2a8 {
 476                 #clock-cells = <0>;
 477                 compatible = "ti,omap4-dpll-clock";
 478                 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 479                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 480         };
 481
 482         dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 483                 #clock-cells = <0>;
 484                 compatible = "ti,divider-clock";
 485                 clocks = <&dpll_gmac_ck>;
 486                 ti,max-div = <31>;
 487                 ti,autoidle-shift = <8>;
 488                 reg = <0x02b8>;
 489                 ti,index-starts-at-one;
 490                 ti,invert-autoidle-bit;
 491         };
 492
 493         video2_dclk_div: video2_dclk_div {
 494                 #clock-cells = <0>;
 495                 compatible = "fixed-factor-clock";
 496                 clocks = <&video2_m2_clkin_ck>;
 497                 clock-mult = <1>;
 498                 clock-div = <1>;
 499         };
 500
 501         video1_dclk_div: video1_dclk_div {
 502                 #clock-cells = <0>;
 503                 compatible = "fixed-factor-clock";
 504                 clocks = <&video1_m2_clkin_ck>;
 505                 clock-mult = <1>;
 506                 clock-div = <1>;
 507         };
 508
 509         hdmi_dclk_div: hdmi_dclk_div {
 510                 #clock-cells = <0>;
 511                 compatible = "fixed-factor-clock";
 512                 clocks = <&hdmi_clkin_ck>;
 513                 clock-mult = <1>;
 514                 clock-div = <1>;
 515         };
 516
 517         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 518                 #clock-cells = <0>;
 519                 compatible = "fixed-factor-clock";
 520                 clocks = <&dpll_abe_m3x2_ck>;
 521                 clock-mult = <1>;
 522                 clock-div = <2>;
 523         };
 524
 525         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 526                 #clock-cells = <0>;
 527                 compatible = "fixed-factor-clock";
 528                 clocks = <&dpll_abe_m3x2_ck>;
 529                 clock-mult = <1>;
 530                 clock-div = <3>;
 531         };
 532
 533         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 534                 #clock-cells = <0>;
 535                 compatible = "fixed-factor-clock";
 536                 clocks = <&dpll_core_h12x2_ck>;
 537                 clock-mult = <1>;
 538                 clock-div = <1>;
 539         };
 540
 541         dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 542                 #clock-cells = <0>;
 543                 compatible = "ti,mux-clock";
 544                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 545                 ti,bit-shift = <23>;
 546                 reg = <0x0290>;
 547         };
 548
 549         dpll_eve_ck: dpll_eve_ck@284 {
 550                 #clock-cells = <0>;
 551                 compatible = "ti,omap4-dpll-clock";
 552                 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 553                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 554         };
 555
 556         dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 557                 #clock-cells = <0>;
 558                 compatible = "ti,divider-clock";
 559                 clocks = <&dpll_eve_ck>;
 560                 ti,max-div = <31>;
 561                 ti,autoidle-shift = <8>;
 562                 reg = <0x0294>;
 563                 ti,index-starts-at-one;
 564                 ti,invert-autoidle-bit;
 565         };
 566
 567         eve_dclk_div: eve_dclk_div {
 568                 #clock-cells = <0>;
 569                 compatible = "fixed-factor-clock";
 570                 clocks = <&dpll_eve_m2_ck>;
 571                 clock-mult = <1>;
 572                 clock-div = <1>;
 573         };
 574
 575         dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 576                 #clock-cells = <0>;
 577                 compatible = "ti,divider-clock";
 578                 clocks = <&dpll_core_x2_ck>;
 579                 ti,max-div = <63>;
 580                 ti,autoidle-shift = <8>;
 581                 reg = <0x0140>;
 582                 ti,index-starts-at-one;
 583                 ti,invert-autoidle-bit;
 584         };
 585
 586         dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 587                 #clock-cells = <0>;
 588                 compatible = "ti,divider-clock";
 589                 clocks = <&dpll_core_x2_ck>;
 590                 ti,max-div = <63>;
 591                 ti,autoidle-shift = <8>;
 592                 reg = <0x0144>;
 593                 ti,index-starts-at-one;
 594                 ti,invert-autoidle-bit;
 595         };
 596
 597         dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 598                 #clock-cells = <0>;
 599                 compatible = "ti,divider-clock";
 600                 clocks = <&dpll_core_x2_ck>;
 601                 ti,max-div = <63>;
 602                 ti,autoidle-shift = <8>;
 603                 reg = <0x0154>;
 604                 ti,index-starts-at-one;
 605                 ti,invert-autoidle-bit;
 606         };
 607
 608         dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 609                 #clock-cells = <0>;
 610                 compatible = "ti,divider-clock";
 611                 clocks = <&dpll_core_x2_ck>;
 612                 ti,max-div = <63>;
 613                 ti,autoidle-shift = <8>;
 614                 reg = <0x0158>;
 615                 ti,index-starts-at-one;
 616                 ti,invert-autoidle-bit;
 617         };
 618
 619         dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 620                 #clock-cells = <0>;
 621                 compatible = "ti,divider-clock";
 622                 clocks = <&dpll_core_x2_ck>;
 623                 ti,max-div = <63>;
 624                 ti,autoidle-shift = <8>;
 625                 reg = <0x015c>;
 626                 ti,index-starts-at-one;
 627                 ti,invert-autoidle-bit;
 628         };
 629
 630         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 631                 #clock-cells = <0>;
 632                 compatible = "ti,omap4-dpll-x2-clock";
 633                 clocks = <&dpll_ddr_ck>;
 634         };
 635
 636         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 637                 #clock-cells = <0>;
 638                 compatible = "ti,divider-clock";
 639                 clocks = <&dpll_ddr_x2_ck>;
 640                 ti,max-div = <63>;
 641                 ti,autoidle-shift = <8>;
 642                 reg = <0x0228>;
 643                 ti,index-starts-at-one;
 644                 ti,invert-autoidle-bit;
 645         };
 646
 647         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 648                 #clock-cells = <0>;
 649                 compatible = "ti,omap4-dpll-x2-clock";
 650                 clocks = <&dpll_dsp_ck>;
 651         };
 652
 653         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 654                 #clock-cells = <0>;
 655                 compatible = "ti,divider-clock";
 656                 clocks = <&dpll_dsp_x2_ck>;
 657                 ti,max-div = <31>;
 658                 ti,autoidle-shift = <8>;
 659                 reg = <0x0248>;
 660                 ti,index-starts-at-one;
 661                 ti,invert-autoidle-bit;
 662         };
 663
 664         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 665                 #clock-cells = <0>;
 666                 compatible = "ti,omap4-dpll-x2-clock";
 667                 clocks = <&dpll_gmac_ck>;
 668         };
 669
 670         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 671                 #clock-cells = <0>;
 672                 compatible = "ti,divider-clock";
 673                 clocks = <&dpll_gmac_x2_ck>;
 674                 ti,max-div = <63>;
 675                 ti,autoidle-shift = <8>;
 676                 reg = <0x02c0>;
 677                 ti,index-starts-at-one;
 678                 ti,invert-autoidle-bit;
 679         };
 680
 681         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 682                 #clock-cells = <0>;
 683                 compatible = "ti,divider-clock";
 684                 clocks = <&dpll_gmac_x2_ck>;
 685                 ti,max-div = <63>;
 686                 ti,autoidle-shift = <8>;
 687                 reg = <0x02c4>;
 688                 ti,index-starts-at-one;
 689                 ti,invert-autoidle-bit;
 690         };
 691
 692         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 693                 #clock-cells = <0>;
 694                 compatible = "ti,divider-clock";
 695                 clocks = <&dpll_gmac_x2_ck>;
 696                 ti,max-div = <63>;
 697                 ti,autoidle-shift = <8>;
 698                 reg = <0x02c8>;
 699                 ti,index-starts-at-one;
 700                 ti,invert-autoidle-bit;
 701         };
 702
 703         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 704                 #clock-cells = <0>;
 705                 compatible = "ti,divider-clock";
 706                 clocks = <&dpll_gmac_x2_ck>;
 707                 ti,max-div = <31>;
 708                 ti,autoidle-shift = <8>;
 709                 reg = <0x02bc>;
 710                 ti,index-starts-at-one;
 711                 ti,invert-autoidle-bit;
 712         };
 713
 714         gmii_m_clk_div: gmii_m_clk_div {
 715                 #clock-cells = <0>;
 716                 compatible = "fixed-factor-clock";
 717                 clocks = <&dpll_gmac_h11x2_ck>;
 718                 clock-mult = <1>;
 719                 clock-div = <2>;
 720         };
 721
 722         hdmi_clk2_div: hdmi_clk2_div {
 723                 #clock-cells = <0>;
 724                 compatible = "fixed-factor-clock";
 725                 clocks = <&hdmi_clkin_ck>;
 726                 clock-mult = <1>;
 727                 clock-div = <1>;
 728         };
 729
 730         hdmi_div_clk: hdmi_div_clk {
 731                 #clock-cells = <0>;
 732                 compatible = "fixed-factor-clock";
 733                 clocks = <&hdmi_clkin_ck>;
 734                 clock-mult = <1>;
 735                 clock-div = <1>;
 736         };
 737
 738         l3_iclk_div: l3_iclk_div@100 {
 739                 #clock-cells = <0>;
 740                 compatible = "ti,divider-clock";
 741                 ti,max-div = <2>;
 742                 ti,bit-shift = <4>;
 743                 reg = <0x0100>;
 744                 clocks = <&dpll_core_h12x2_ck>;
 745                 ti,index-power-of-two;
 746         };
 747
 748         l4_root_clk_div: l4_root_clk_div {
 749                 #clock-cells = <0>;
 750                 compatible = "fixed-factor-clock";
 751                 clocks = <&l3_iclk_div>;
 752                 clock-mult = <1>;
 753                 clock-div = <2>;
 754         };
 755
 756         video1_clk2_div: video1_clk2_div {
 757                 #clock-cells = <0>;
 758                 compatible = "fixed-factor-clock";
 759                 clocks = <&video1_clkin_ck>;
 760                 clock-mult = <1>;
 761                 clock-div = <1>;
 762         };
 763
 764         video1_div_clk: video1_div_clk {
 765                 #clock-cells = <0>;
 766                 compatible = "fixed-factor-clock";
 767                 clocks = <&video1_clkin_ck>;
 768                 clock-mult = <1>;
 769                 clock-div = <1>;
 770         };
 771
 772         video2_clk2_div: video2_clk2_div {
 773                 #clock-cells = <0>;
 774                 compatible = "fixed-factor-clock";
 775                 clocks = <&video2_clkin_ck>;
 776                 clock-mult = <1>;
 777                 clock-div = <1>;
 778         };
 779
 780         video2_div_clk: video2_div_clk {
 781                 #clock-cells = <0>;
 782                 compatible = "fixed-factor-clock";
 783                 clocks = <&video2_clkin_ck>;
 784                 clock-mult = <1>;
 785                 clock-div = <1>;
 786         };
 787
 788         ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
 789                 #clock-cells = <0>;
 790                 compatible = "ti,mux-clock";
 791                 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 792                 ti,bit-shift = <24>;
 793                 reg = <0x0520>;
 794                 assigned-clocks = <&ipu1_gfclk_mux>;
 795                 assigned-clock-parents = <&dpll_core_h22x2_ck>;
 796         };
 797
 798         mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
 799                 #clock-cells = <0>;
 800                 compatible = "ti,mux-clock";
 801                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 802                 ti,bit-shift = <28>;
 803                 reg = <0x0550>;
 804         };
 805
 806         mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
 807                 #clock-cells = <0>;
 808                 compatible = "ti,mux-clock";
 809                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 810                 ti,bit-shift = <24>;
 811                 reg = <0x0550>;
 812         };
 813
 814         mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
 815                 #clock-cells = <0>;
 816                 compatible = "ti,mux-clock";
 817                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
 818                 ti,bit-shift = <22>;
 819                 reg = <0x0550>;
 820         };
 821
 822         timer5_gfclk_mux: timer5_gfclk_mux@558 {
 823                 #clock-cells = <0>;
 824                 compatible = "ti,mux-clock";
 825                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 826                 ti,bit-shift = <24>;
 827                 reg = <0x0558>;
 828         };
 829
 830         timer6_gfclk_mux: timer6_gfclk_mux@560 {
 831                 #clock-cells = <0>;
 832                 compatible = "ti,mux-clock";
 833                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 834                 ti,bit-shift = <24>;
 835                 reg = <0x0560>;
 836         };
 837
 838         timer7_gfclk_mux: timer7_gfclk_mux@568 {
 839                 #clock-cells = <0>;
 840                 compatible = "ti,mux-clock";
 841                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 842                 ti,bit-shift = <24>;
 843                 reg = <0x0568>;
 844         };
 845
 846         timer8_gfclk_mux: timer8_gfclk_mux@570 {
 847                 #clock-cells = <0>;
 848                 compatible = "ti,mux-clock";
 849                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 850                 ti,bit-shift = <24>;
 851                 reg = <0x0570>;
 852         };
 853
 854         uart6_gfclk_mux: uart6_gfclk_mux@580 {
 855                 #clock-cells = <0>;
 856                 compatible = "ti,mux-clock";
 857                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
 858                 ti,bit-shift = <24>;
 859                 reg = <0x0580>;
 860         };
 861
 862         dummy_ck: dummy_ck {
 863                 #clock-cells = <0>;
 864                 compatible = "fixed-clock";
 865                 clock-frequency = <0>;
 866         };
 867 };
 868 &prm_clocks {
 869         sys_clkin1: sys_clkin1@110 {
 870                 #clock-cells = <0>;
 871                 compatible = "ti,mux-clock";
 872                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 873                 reg = <0x0110>;
 874                 ti,index-starts-at-one;
 875         };
 876
 877         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 878                 #clock-cells = <0>;
 879                 compatible = "ti,mux-clock";
 880                 clocks = <&sys_clkin1>, <&sys_clkin2>;
 881                 reg = <0x0118>;
 882         };
 883
 884         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 885                 #clock-cells = <0>;
 886                 compatible = "ti,mux-clock";
 887                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 888                 reg = <0x0114>;
 889         };
 890
 891         abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 892                 #clock-cells = <0>;
 893                 compatible = "ti,mux-clock";
 894                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 895                 reg = <0x010c>;
 896         };
 897
 898         abe_24m_fclk: abe_24m_fclk@11c {
 899                 #clock-cells = <0>;
 900                 compatible = "ti,divider-clock";
 901                 clocks = <&dpll_abe_m2x2_ck>;
 902                 reg = <0x011c>;
 903                 ti,dividers = <8>, <16>;
 904         };
 905
 906         aess_fclk: aess_fclk@178 {
 907                 #clock-cells = <0>;
 908                 compatible = "ti,divider-clock";
 909                 clocks = <&abe_clk>;
 910                 reg = <0x0178>;
 911                 ti,max-div = <2>;
 912         };
 913
 914         abe_giclk_div: abe_giclk_div@174 {
 915                 #clock-cells = <0>;
 916                 compatible = "ti,divider-clock";
 917                 clocks = <&aess_fclk>;
 918                 reg = <0x0174>;
 919                 ti,max-div = <2>;
 920         };
 921
 922         abe_lp_clk_div: abe_lp_clk_div@1d8 {
 923                 #clock-cells = <0>;
 924                 compatible = "ti,divider-clock";
 925                 clocks = <&dpll_abe_m2x2_ck>;
 926                 reg = <0x01d8>;
 927                 ti,dividers = <16>, <32>;
 928         };
 929
 930         abe_sys_clk_div: abe_sys_clk_div@120 {
 931                 #clock-cells = <0>;
 932                 compatible = "ti,divider-clock";
 933                 clocks = <&sys_clkin1>;
 934                 reg = <0x0120>;
 935                 ti,max-div = <2>;
 936         };
 937
 938         adc_gfclk_mux: adc_gfclk_mux@1dc {
 939                 #clock-cells = <0>;
 940                 compatible = "ti,mux-clock";
 941                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 942                 reg = <0x01dc>;
 943         };
 944
 945         sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 946                 #clock-cells = <0>;
 947                 compatible = "ti,divider-clock";
 948                 clocks = <&sys_clkin1>;
 949                 ti,max-div = <64>;
 950                 reg = <0x01c8>;
 951                 ti,index-power-of-two;
 952         };
 953
 954         sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 955                 #clock-cells = <0>;
 956                 compatible = "ti,divider-clock";
 957                 clocks = <&sys_clkin2>;
 958                 ti,max-div = <64>;
 959                 reg = <0x01cc>;
 960                 ti,index-power-of-two;
 961         };
 962
 963         per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 964                 #clock-cells = <0>;
 965                 compatible = "ti,divider-clock";
 966                 clocks = <&dpll_abe_m2_ck>;
 967                 ti,max-div = <64>;
 968                 reg = <0x01bc>;
 969                 ti,index-power-of-two;
 970         };
 971
 972         dsp_gclk_div: dsp_gclk_div@18c {
 973                 #clock-cells = <0>;
 974                 compatible = "ti,divider-clock";
 975                 clocks = <&dpll_dsp_m2_ck>;
 976                 ti,max-div = <64>;
 977                 reg = <0x018c>;
 978                 ti,index-power-of-two;
 979         };
 980
 981         gpu_dclk: gpu_dclk@1a0 {
 982                 #clock-cells = <0>;
 983                 compatible = "ti,divider-clock";
 984                 clocks = <&dpll_gpu_m2_ck>;
 985                 ti,max-div = <64>;
 986                 reg = <0x01a0>;
 987                 ti,index-power-of-two;
 988         };
 989
 990         emif_phy_dclk_div: emif_phy_dclk_div@190 {
 991                 #clock-cells = <0>;
 992                 compatible = "ti,divider-clock";
 993                 clocks = <&dpll_ddr_m2_ck>;
 994                 ti,max-div = <64>;
 995                 reg = <0x0190>;
 996                 ti,index-power-of-two;
 997         };
 998
 999         gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
1000                 #clock-cells = <0>;
1001                 compatible = "ti,divider-clock";
1002                 clocks = <&dpll_gmac_m2_ck>;
1003                 ti,max-div = <64>;
1004                 reg = <0x019c>;
1005                 ti,index-power-of-two;
1006         };
1007
1008         gmac_main_clk: gmac_main_clk {
1009                 #clock-cells = <0>;
1010                 compatible = "fixed-factor-clock";
1011                 clocks = <&gmac_250m_dclk_div>;
1012                 clock-mult = <1>;
1013                 clock-div = <2>;
1014         };
1015
1016         l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
1017                 #clock-cells = <0>;
1018                 compatible = "ti,divider-clock";
1019                 clocks = <&dpll_usb_m2_ck>;
1020                 ti,max-div = <64>;
1021                 reg = <0x01ac>;
1022                 ti,index-power-of-two;
1023         };
1024
1025         usb_otg_dclk_div: usb_otg_dclk_div@184 {
1026                 #clock-cells = <0>;
1027                 compatible = "ti,divider-clock";
1028                 clocks = <&usb_otg_clkin_ck>;
1029                 ti,max-div = <64>;
1030                 reg = <0x0184>;
1031                 ti,index-power-of-two;
1032         };
1033
1034         sata_dclk_div: sata_dclk_div@1c0 {
1035                 #clock-cells = <0>;
1036                 compatible = "ti,divider-clock";
1037                 clocks = <&sys_clkin1>;
1038                 ti,max-div = <64>;
1039                 reg = <0x01c0>;
1040                 ti,index-power-of-two;
1041         };
1042
1043         pcie2_dclk_div: pcie2_dclk_div@1b8 {
1044                 #clock-cells = <0>;
1045                 compatible = "ti,divider-clock";
1046                 clocks = <&dpll_pcie_ref_m2_ck>;
1047                 ti,max-div = <64>;
1048                 reg = <0x01b8>;
1049                 ti,index-power-of-two;
1050         };
1051
1052         pcie_dclk_div: pcie_dclk_div@1b4 {
1053                 #clock-cells = <0>;
1054                 compatible = "ti,divider-clock";
1055                 clocks = <&apll_pcie_m2_ck>;
1056                 ti,max-div = <64>;
1057                 reg = <0x01b4>;
1058                 ti,index-power-of-two;
1059         };
1060
1061         emu_dclk_div: emu_dclk_div@194 {
1062                 #clock-cells = <0>;
1063                 compatible = "ti,divider-clock";
1064                 clocks = <&sys_clkin1>;
1065                 ti,max-div = <64>;
1066                 reg = <0x0194>;
1067                 ti,index-power-of-two;
1068         };
1069
1070         secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1071                 #clock-cells = <0>;
1072                 compatible = "ti,divider-clock";
1073                 clocks = <&secure_32k_clk_src_ck>;
1074                 ti,max-div = <64>;
1075                 reg = <0x01c4>;
1076                 ti,index-power-of-two;
1077         };
1078
1079         clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1080                 #clock-cells = <0>;
1081                 compatible = "ti,mux-clock";
1082                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1083                 reg = <0x0158>;
1084         };
1085
1086         clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1087                 #clock-cells = <0>;
1088                 compatible = "ti,mux-clock";
1089                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1090                 reg = <0x015c>;
1091         };
1092
1093         clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1094                 #clock-cells = <0>;
1095                 compatible = "ti,mux-clock";
1096                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1097                 reg = <0x0160>;
1098         };
1099
1100         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1101                 #clock-cells = <0>;
1102                 compatible = "fixed-factor-clock";
1103                 clocks = <&sys_clkin1>;
1104                 clock-mult = <1>;
1105                 clock-div = <2>;
1106         };
1107
1108         eve_clk: eve_clk@180 {
1109                 #clock-cells = <0>;
1110                 compatible = "ti,mux-clock";
1111                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1112                 reg = <0x0180>;
1113         };
1114
1115         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1116                 #clock-cells = <0>;
1117                 compatible = "ti,mux-clock";
1118                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1119                 reg = <0x0164>;
1120         };
1121
1122         mlb_clk: mlb_clk@134 {
1123                 #clock-cells = <0>;
1124                 compatible = "ti,divider-clock";
1125                 clocks = <&mlb_clkin_ck>;
1126                 ti,max-div = <64>;
1127                 reg = <0x0134>;
1128                 ti,index-power-of-two;
1129         };
1130
1131         mlbp_clk: mlbp_clk@130 {
1132                 #clock-cells = <0>;
1133                 compatible = "ti,divider-clock";
1134                 clocks = <&mlbp_clkin_ck>;
1135                 ti,max-div = <64>;
1136                 reg = <0x0130>;
1137                 ti,index-power-of-two;
1138         };
1139
1140         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1141                 #clock-cells = <0>;
1142                 compatible = "ti,divider-clock";
1143                 clocks = <&dpll_abe_m2_ck>;
1144                 ti,max-div = <64>;
1145                 reg = <0x0138>;
1146                 ti,index-power-of-two;
1147         };
1148
1149         timer_sys_clk_div: timer_sys_clk_div@144 {
1150                 #clock-cells = <0>;
1151                 compatible = "ti,divider-clock";
1152                 clocks = <&sys_clkin1>;
1153                 reg = <0x0144>;
1154                 ti,max-div = <2>;
1155         };
1156
1157         video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1158                 #clock-cells = <0>;
1159                 compatible = "ti,mux-clock";
1160                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1161                 reg = <0x0168>;
1162         };
1163
1164         video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1165                 #clock-cells = <0>;
1166                 compatible = "ti,mux-clock";
1167                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1168                 reg = <0x016c>;
1169         };
1170
1171         wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1172                 #clock-cells = <0>;
1173                 compatible = "ti,mux-clock";
1174                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1175                 reg = <0x0108>;
1176         };
1177
1178         gpio1_dbclk: gpio1_dbclk@1838 {
1179                 #clock-cells = <0>;
1180                 compatible = "ti,gate-clock";
1181                 clocks = <&sys_32k_ck>;
1182                 ti,bit-shift = <8>;
1183                 reg = <0x1838>;
1184         };
1185
1186         dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
1187                 #clock-cells = <0>;
1188                 compatible = "ti,mux-clock";
1189                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1190                 ti,bit-shift = <24>;
1191                 reg = <0x1888>;
1192         };
1193
1194         timer1_gfclk_mux: timer1_gfclk_mux@1840 {
1195                 #clock-cells = <0>;
1196                 compatible = "ti,mux-clock";
1197                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1198                 ti,bit-shift = <24>;
1199                 reg = <0x1840>;
1200         };
1201
1202         uart10_gfclk_mux: uart10_gfclk_mux@1880 {
1203                 #clock-cells = <0>;
1204                 compatible = "ti,mux-clock";
1205                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1206                 ti,bit-shift = <24>;
1207                 reg = <0x1880>;
1208         };
1209 };
1210 &cm_core_clocks {
1211         dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1212                 #clock-cells = <0>;
1213                 compatible = "ti,omap4-dpll-clock";
1214                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1215                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1216         };
1217
1218         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1219                 #clock-cells = <0>;
1220                 compatible = "ti,divider-clock";
1221                 clocks = <&dpll_pcie_ref_ck>;
1222                 ti,max-div = <31>;
1223                 ti,autoidle-shift = <8>;
1224                 reg = <0x0210>;
1225                 ti,index-starts-at-one;
1226                 ti,invert-autoidle-bit;
1227         };
1228
1229         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1230                 compatible = "ti,mux-clock";
1231                 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1232                 #clock-cells = <0>;
1233                 reg = <0x021c 0x4>;
1234                 ti,bit-shift = <7>;
1235         };
1236
1237         apll_pcie_ck: apll_pcie_ck@21c {
1238                 #clock-cells = <0>;
1239                 compatible = "ti,dra7-apll-clock";
1240                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1241                 reg = <0x021c>, <0x0220>;
1242         };
1243
1244         optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1245                 compatible = "ti,gate-clock";
1246                 clocks = <&sys_32k_ck>;
1247                 #clock-cells = <0>;
1248                 reg = <0x13b0>;
1249                 ti,bit-shift = <8>;
1250         };
1251
1252         optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1253                 compatible = "ti,gate-clock";
1254                 clocks = <&sys_32k_ck>;
1255                 #clock-cells = <0>;
1256                 reg = <0x13b8>;
1257                 ti,bit-shift = <8>;
1258         };
1259
1260         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1261                 compatible = "ti,divider-clock";
1262                 clocks = <&apll_pcie_ck>;
1263                 #clock-cells = <0>;
1264                 reg = <0x021c>;
1265                 ti,dividers = <2>, <1>;
1266                 ti,bit-shift = <8>;
1267                 ti,max-div = <2>;
1268         };
1269
1270         optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1271                 compatible = "ti,gate-clock";
1272                 clocks = <&apll_pcie_ck>;
1273                 #clock-cells = <0>;
1274                 reg = <0x13b0>;
1275                 ti,bit-shift = <9>;
1276         };
1277
1278         optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1279                 compatible = "ti,gate-clock";
1280                 clocks = <&apll_pcie_ck>;
1281                 #clock-cells = <0>;
1282                 reg = <0x13b8>;
1283                 ti,bit-shift = <9>;
1284         };
1285
1286         optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1287                 compatible = "ti,gate-clock";
1288                 clocks = <&optfclk_pciephy_div>;
1289                 #clock-cells = <0>;
1290                 reg = <0x13b0>;
1291                 ti,bit-shift = <10>;
1292         };
1293
1294         optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1295                 compatible = "ti,gate-clock";
1296                 clocks = <&optfclk_pciephy_div>;
1297                 #clock-cells = <0>;
1298                 reg = <0x13b8>;
1299                 ti,bit-shift = <10>;
1300         };
1301
1302         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1303                 #clock-cells = <0>;
1304                 compatible = "fixed-factor-clock";
1305                 clocks = <&apll_pcie_ck>;
1306                 clock-mult = <1>;
1307                 clock-div = <1>;
1308         };
1309
1310         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1311                 #clock-cells = <0>;
1312                 compatible = "fixed-factor-clock";
1313                 clocks = <&apll_pcie_ck>;
1314                 clock-mult = <1>;
1315                 clock-div = <1>;
1316         };
1317
1318         apll_pcie_m2_ck: apll_pcie_m2_ck {
1319                 #clock-cells = <0>;
1320                 compatible = "fixed-factor-clock";
1321                 clocks = <&apll_pcie_ck>;
1322                 clock-mult = <1>;
1323                 clock-div = <1>;
1324         };
1325
1326         dpll_per_byp_mux: dpll_per_byp_mux@14c {
1327                 #clock-cells = <0>;
1328                 compatible = "ti,mux-clock";
1329                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1330                 ti,bit-shift = <23>;
1331                 reg = <0x014c>;
1332         };
1333
1334         dpll_per_ck: dpll_per_ck@140 {
1335                 #clock-cells = <0>;
1336                 compatible = "ti,omap4-dpll-clock";
1337                 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1338                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1339         };
1340
1341         dpll_per_m2_ck: dpll_per_m2_ck@150 {
1342                 #clock-cells = <0>;
1343                 compatible = "ti,divider-clock";
1344                 clocks = <&dpll_per_ck>;
1345                 ti,max-div = <31>;
1346                 ti,autoidle-shift = <8>;
1347                 reg = <0x0150>;
1348                 ti,index-starts-at-one;
1349                 ti,invert-autoidle-bit;
1350         };
1351
1352         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1353                 #clock-cells = <0>;
1354                 compatible = "fixed-factor-clock";
1355                 clocks = <&dpll_per_m2_ck>;
1356                 clock-mult = <1>;
1357                 clock-div = <1>;
1358         };
1359
1360         dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1361                 #clock-cells = <0>;
1362                 compatible = "ti,mux-clock";
1363                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1364                 ti,bit-shift = <23>;
1365                 reg = <0x018c>;
1366         };
1367
1368         dpll_usb_ck: dpll_usb_ck@180 {
1369                 #clock-cells = <0>;
1370                 compatible = "ti,omap4-dpll-j-type-clock";
1371                 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1372                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1373         };
1374
1375         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1376                 #clock-cells = <0>;
1377                 compatible = "ti,divider-clock";
1378                 clocks = <&dpll_usb_ck>;
1379                 ti,max-div = <127>;
1380                 ti,autoidle-shift = <8>;
1381                 reg = <0x0190>;
1382                 ti,index-starts-at-one;
1383                 ti,invert-autoidle-bit;
1384         };
1385
1386         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1387                 #clock-cells = <0>;
1388                 compatible = "ti,divider-clock";
1389                 clocks = <&dpll_pcie_ref_ck>;
1390                 ti,max-div = <127>;
1391                 ti,autoidle-shift = <8>;
1392                 reg = <0x0210>;
1393                 ti,index-starts-at-one;
1394                 ti,invert-autoidle-bit;
1395         };
1396
1397         dpll_per_x2_ck: dpll_per_x2_ck {
1398                 #clock-cells = <0>;
1399                 compatible = "ti,omap4-dpll-x2-clock";
1400                 clocks = <&dpll_per_ck>;
1401         };
1402
1403         dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1404                 #clock-cells = <0>;
1405                 compatible = "ti,divider-clock";
1406                 clocks = <&dpll_per_x2_ck>;
1407                 ti,max-div = <63>;
1408                 ti,autoidle-shift = <8>;
1409                 reg = <0x0158>;
1410                 ti,index-starts-at-one;
1411                 ti,invert-autoidle-bit;
1412         };
1413
1414         dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1415                 #clock-cells = <0>;
1416                 compatible = "ti,divider-clock";
1417                 clocks = <&dpll_per_x2_ck>;
1418                 ti,max-div = <63>;
1419                 ti,autoidle-shift = <8>;
1420                 reg = <0x015c>;
1421                 ti,index-starts-at-one;
1422                 ti,invert-autoidle-bit;
1423         };
1424
1425         dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1426                 #clock-cells = <0>;
1427                 compatible = "ti,divider-clock";
1428                 clocks = <&dpll_per_x2_ck>;
1429                 ti,max-div = <63>;
1430                 ti,autoidle-shift = <8>;
1431                 reg = <0x0160>;
1432                 ti,index-starts-at-one;
1433                 ti,invert-autoidle-bit;
1434         };
1435
1436         dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1437                 #clock-cells = <0>;
1438                 compatible = "ti,divider-clock";
1439                 clocks = <&dpll_per_x2_ck>;
1440                 ti,max-div = <63>;
1441                 ti,autoidle-shift = <8>;
1442                 reg = <0x0164>;
1443                 ti,index-starts-at-one;
1444                 ti,invert-autoidle-bit;
1445         };
1446
1447         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1448                 #clock-cells = <0>;
1449                 compatible = "ti,divider-clock";
1450                 clocks = <&dpll_per_x2_ck>;
1451                 ti,max-div = <31>;
1452                 ti,autoidle-shift = <8>;
1453                 reg = <0x0150>;
1454                 ti,index-starts-at-one;
1455                 ti,invert-autoidle-bit;
1456         };
1457
1458         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1459                 #clock-cells = <0>;
1460                 compatible = "fixed-factor-clock";
1461                 clocks = <&dpll_usb_ck>;
1462                 clock-mult = <1>;
1463                 clock-div = <1>;
1464         };
1465
1466         func_128m_clk: func_128m_clk {
1467                 #clock-cells = <0>;
1468                 compatible = "fixed-factor-clock";
1469                 clocks = <&dpll_per_h11x2_ck>;
1470                 clock-mult = <1>;
1471                 clock-div = <2>;
1472         };
1473
1474         func_12m_fclk: func_12m_fclk {
1475                 #clock-cells = <0>;
1476                 compatible = "fixed-factor-clock";
1477                 clocks = <&dpll_per_m2x2_ck>;
1478                 clock-mult = <1>;
1479                 clock-div = <16>;
1480         };
1481
1482         func_24m_clk: func_24m_clk {
1483                 #clock-cells = <0>;
1484                 compatible = "fixed-factor-clock";
1485                 clocks = <&dpll_per_m2_ck>;
1486                 clock-mult = <1>;
1487                 clock-div = <4>;
1488         };
1489
1490         func_48m_fclk: func_48m_fclk {
1491                 #clock-cells = <0>;
1492                 compatible = "fixed-factor-clock";
1493                 clocks = <&dpll_per_m2x2_ck>;
1494                 clock-mult = <1>;
1495                 clock-div = <4>;
1496         };
1497
1498         func_96m_fclk: func_96m_fclk {
1499                 #clock-cells = <0>;
1500                 compatible = "fixed-factor-clock";
1501                 clocks = <&dpll_per_m2x2_ck>;
1502                 clock-mult = <1>;
1503                 clock-div = <2>;
1504         };
1505
1506         l3init_60m_fclk: l3init_60m_fclk@104 {
1507                 #clock-cells = <0>;
1508                 compatible = "ti,divider-clock";
1509                 clocks = <&dpll_usb_m2_ck>;
1510                 reg = <0x0104>;
1511                 ti,dividers = <1>, <8>;
1512         };
1513
1514         clkout2_clk: clkout2_clk@6b0 {
1515                 #clock-cells = <0>;
1516                 compatible = "ti,gate-clock";
1517                 clocks = <&clkoutmux2_clk_mux>;
1518                 ti,bit-shift = <8>;
1519                 reg = <0x06b0>;
1520         };
1521
1522         l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1523                 #clock-cells = <0>;
1524                 compatible = "ti,gate-clock";
1525                 clocks = <&dpll_usb_clkdcoldo>;
1526                 ti,bit-shift = <8>;
1527                 reg = <0x06c0>;
1528         };
1529
1530         dss_32khz_clk: dss_32khz_clk@1120 {
1531                 #clock-cells = <0>;
1532                 compatible = "ti,gate-clock";
1533                 clocks = <&sys_32k_ck>;
1534                 ti,bit-shift = <11>;
1535                 reg = <0x1120>;
1536         };
1537
1538         dss_48mhz_clk: dss_48mhz_clk@1120 {
1539                 #clock-cells = <0>;
1540                 compatible = "ti,gate-clock";
1541                 clocks = <&func_48m_fclk>;
1542                 ti,bit-shift = <9>;
1543                 reg = <0x1120>;
1544         };
1545
1546         dss_dss_clk: dss_dss_clk@1120 {
1547                 #clock-cells = <0>;
1548                 compatible = "ti,gate-clock";
1549                 clocks = <&dpll_per_h12x2_ck>;
1550                 ti,bit-shift = <8>;
1551                 reg = <0x1120>;
1552                 ti,set-rate-parent;
1553         };
1554
1555         dss_hdmi_clk: dss_hdmi_clk@1120 {
1556                 #clock-cells = <0>;
1557                 compatible = "ti,gate-clock";
1558                 clocks = <&hdmi_dpll_clk_mux>;
1559                 ti,bit-shift = <10>;
1560                 reg = <0x1120>;
1561         };
1562
1563         dss_video1_clk: dss_video1_clk@1120 {
1564                 #clock-cells = <0>;
1565                 compatible = "ti,gate-clock";
1566                 clocks = <&video1_dpll_clk_mux>;
1567                 ti,bit-shift = <12>;
1568                 reg = <0x1120>;
1569         };
1570
1571         dss_video2_clk: dss_video2_clk@1120 {
1572                 #clock-cells = <0>;
1573                 compatible = "ti,gate-clock";
1574                 clocks = <&video2_dpll_clk_mux>;
1575                 ti,bit-shift = <13>;
1576                 reg = <0x1120>;
1577         };
1578
1579         gpio2_dbclk: gpio2_dbclk@1760 {
1580                 #clock-cells = <0>;
1581                 compatible = "ti,gate-clock";
1582                 clocks = <&sys_32k_ck>;
1583                 ti,bit-shift = <8>;
1584                 reg = <0x1760>;
1585         };
1586
1587         gpio3_dbclk: gpio3_dbclk@1768 {
1588                 #clock-cells = <0>;
1589                 compatible = "ti,gate-clock";
1590                 clocks = <&sys_32k_ck>;
1591                 ti,bit-shift = <8>;
1592                 reg = <0x1768>;
1593         };
1594
1595         gpio4_dbclk: gpio4_dbclk@1770 {
1596                 #clock-cells = <0>;
1597                 compatible = "ti,gate-clock";
1598                 clocks = <&sys_32k_ck>;
1599                 ti,bit-shift = <8>;
1600                 reg = <0x1770>;
1601         };
1602
1603         gpio5_dbclk: gpio5_dbclk@1778 {
1604                 #clock-cells = <0>;
1605                 compatible = "ti,gate-clock";
1606                 clocks = <&sys_32k_ck>;
1607                 ti,bit-shift = <8>;
1608                 reg = <0x1778>;
1609         };
1610
1611         gpio6_dbclk: gpio6_dbclk@1780 {
1612                 #clock-cells = <0>;
1613                 compatible = "ti,gate-clock";
1614                 clocks = <&sys_32k_ck>;
1615                 ti,bit-shift = <8>;
1616                 reg = <0x1780>;
1617         };
1618
1619         gpio7_dbclk: gpio7_dbclk@1810 {
1620                 #clock-cells = <0>;
1621                 compatible = "ti,gate-clock";
1622                 clocks = <&sys_32k_ck>;
1623                 ti,bit-shift = <8>;
1624                 reg = <0x1810>;
1625         };
1626
1627         gpio8_dbclk: gpio8_dbclk@1818 {
1628                 #clock-cells = <0>;
1629                 compatible = "ti,gate-clock";
1630                 clocks = <&sys_32k_ck>;
1631                 ti,bit-shift = <8>;
1632                 reg = <0x1818>;
1633         };
1634
1635         mmc1_clk32k: mmc1_clk32k@1328 {
1636                 #clock-cells = <0>;
1637                 compatible = "ti,gate-clock";
1638                 clocks = <&sys_32k_ck>;
1639                 ti,bit-shift = <8>;
1640                 reg = <0x1328>;
1641         };
1642
1643         mmc2_clk32k: mmc2_clk32k@1330 {
1644                 #clock-cells = <0>;
1645                 compatible = "ti,gate-clock";
1646                 clocks = <&sys_32k_ck>;
1647                 ti,bit-shift = <8>;
1648                 reg = <0x1330>;
1649         };
1650
1651         mmc3_clk32k: mmc3_clk32k@1820 {
1652                 #clock-cells = <0>;
1653                 compatible = "ti,gate-clock";
1654                 clocks = <&sys_32k_ck>;
1655                 ti,bit-shift = <8>;
1656                 reg = <0x1820>;
1657         };
1658
1659         mmc4_clk32k: mmc4_clk32k@1828 {
1660                 #clock-cells = <0>;
1661                 compatible = "ti,gate-clock";
1662                 clocks = <&sys_32k_ck>;
1663                 ti,bit-shift = <8>;
1664                 reg = <0x1828>;
1665         };
1666
1667         sata_ref_clk: sata_ref_clk@1388 {
1668                 #clock-cells = <0>;
1669                 compatible = "ti,gate-clock";
1670                 clocks = <&sys_clkin1>;
1671                 ti,bit-shift = <8>;
1672                 reg = <0x1388>;
1673         };
1674
1675         usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
1676                 #clock-cells = <0>;
1677                 compatible = "ti,gate-clock";
1678                 clocks = <&l3init_960m_gfclk>;
1679                 ti,bit-shift = <8>;
1680                 reg = <0x13f0>;
1681         };
1682
1683         usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
1684                 #clock-cells = <0>;
1685                 compatible = "ti,gate-clock";
1686                 clocks = <&l3init_960m_gfclk>;
1687                 ti,bit-shift = <8>;
1688                 reg = <0x1340>;
1689         };
1690
1691         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1692                 #clock-cells = <0>;
1693                 compatible = "ti,gate-clock";
1694                 clocks = <&sys_32k_ck>;
1695                 ti,bit-shift = <8>;
1696                 reg = <0x0640>;
1697         };
1698
1699         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1700                 #clock-cells = <0>;
1701                 compatible = "ti,gate-clock";
1702                 clocks = <&sys_32k_ck>;
1703                 ti,bit-shift = <8>;
1704                 reg = <0x0688>;
1705         };
1706
1707         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1708                 #clock-cells = <0>;
1709                 compatible = "ti,gate-clock";
1710                 clocks = <&sys_32k_ck>;
1711                 ti,bit-shift = <8>;
1712                 reg = <0x0698>;
1713         };
1714
1715         atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
1716                 #clock-cells = <0>;
1717                 compatible = "ti,mux-clock";
1718                 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1719                 ti,bit-shift = <24>;
1720                 reg = <0x0c00>;
1721         };
1722
1723         atl_gfclk_mux: atl_gfclk_mux@c00 {
1724                 #clock-cells = <0>;
1725                 compatible = "ti,mux-clock";
1726                 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1727                 ti,bit-shift = <26>;
1728                 reg = <0x0c00>;
1729         };
1730
1731         rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
1732                 #clock-cells = <0>;
1733                 compatible = "ti,mux-clock";
1734                 clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
1735                 ti,bit-shift = <24>;
1736                 reg = <0x13d0>;
1737         };
1738
1739         gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
1740                 #clock-cells = <0>;
1741                 compatible = "ti,mux-clock";
1742                 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1743                 ti,bit-shift = <25>;
1744                 reg = <0x13d0>;
1745         };
1746
1747         gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1748                 #clock-cells = <0>;
1749                 compatible = "ti,mux-clock";
1750                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1751                 ti,bit-shift = <24>;
1752                 reg = <0x1220>;
1753         };
1754
1755         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1756                 #clock-cells = <0>;
1757                 compatible = "ti,mux-clock";
1758                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1759                 ti,bit-shift = <26>;
1760                 reg = <0x1220>;
1761         };
1762
1763         l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1764                 #clock-cells = <0>;
1765                 compatible = "ti,divider-clock";
1766                 clocks = <&wkupaon_iclk_mux>;
1767                 ti,bit-shift = <24>;
1768                 reg = <0x0e50>;
1769                 ti,dividers = <8>, <16>, <32>;
1770         };
1771
1772         mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
1773                 #clock-cells = <0>;
1774                 compatible = "ti,mux-clock";
1775                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1776                 ti,bit-shift = <28>;
1777                 reg = <0x1860>;
1778         };
1779
1780         mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
1781                 #clock-cells = <0>;
1782                 compatible = "ti,mux-clock";
1783                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1784                 ti,bit-shift = <24>;
1785                 reg = <0x1860>;
1786         };
1787
1788         mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
1789                 #clock-cells = <0>;
1790                 compatible = "ti,mux-clock";
1791                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1792                 ti,bit-shift = <22>;
1793                 reg = <0x1860>;
1794         };
1795
1796         mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
1797                 #clock-cells = <0>;
1798                 compatible = "ti,mux-clock";
1799                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1800                 ti,bit-shift = <24>;
1801                 reg = <0x1868>;
1802         };
1803
1804         mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
1805                 #clock-cells = <0>;
1806                 compatible = "ti,mux-clock";
1807                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1808                 ti,bit-shift = <22>;
1809                 reg = <0x1868>;
1810         };
1811
1812         mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
1813                 #clock-cells = <0>;
1814                 compatible = "ti,mux-clock";
1815                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1816                 ti,bit-shift = <24>;
1817                 reg = <0x1898>;
1818         };
1819
1820         mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
1821                 #clock-cells = <0>;
1822                 compatible = "ti,mux-clock";
1823                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1824                 ti,bit-shift = <22>;
1825                 reg = <0x1898>;
1826         };
1827
1828         mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
1829                 #clock-cells = <0>;
1830                 compatible = "ti,mux-clock";
1831                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1832                 ti,bit-shift = <24>;
1833                 reg = <0x1878>;
1834         };
1835
1836         mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
1837                 #clock-cells = <0>;
1838                 compatible = "ti,mux-clock";
1839                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1840                 ti,bit-shift = <22>;
1841                 reg = <0x1878>;
1842         };
1843
1844         mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
1845                 #clock-cells = <0>;
1846                 compatible = "ti,mux-clock";
1847                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1848                 ti,bit-shift = <24>;
1849                 reg = <0x1904>;
1850         };
1851
1852         mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
1853                 #clock-cells = <0>;
1854                 compatible = "ti,mux-clock";
1855                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1856                 ti,bit-shift = <22>;
1857                 reg = <0x1904>;
1858         };
1859
1860         mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
1861                 #clock-cells = <0>;
1862                 compatible = "ti,mux-clock";
1863                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1864                 ti,bit-shift = <24>;
1865                 reg = <0x1908>;
1866         };
1867
1868         mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
1869                 #clock-cells = <0>;
1870                 compatible = "ti,mux-clock";
1871                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1872                 ti,bit-shift = <22>;
1873                 reg = <0x1908>;
1874         };
1875
1876         mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
1877                 #clock-cells = <0>;
1878                 compatible = "ti,mux-clock";
1879                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1880                 ti,bit-shift = <22>;
1881                 reg = <0x1890>;
1882         };
1883
1884         mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
1885                 #clock-cells = <0>;
1886                 compatible = "ti,mux-clock";
1887                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1888                 ti,bit-shift = <24>;
1889                 reg = <0x1890>;
1890         };
1891
1892         mmc1_fclk_mux: mmc1_fclk_mux@1328 {
1893                 #clock-cells = <0>;
1894                 compatible = "ti,mux-clock";
1895                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1896                 ti,bit-shift = <24>;
1897                 reg = <0x1328>;
1898         };
1899
1900         mmc1_fclk_div: mmc1_fclk_div@1328 {
1901                 #clock-cells = <0>;
1902                 compatible = "ti,divider-clock";
1903                 clocks = <&mmc1_fclk_mux>;
1904                 ti,bit-shift = <25>;
1905                 ti,max-div = <4>;
1906                 reg = <0x1328>;
1907                 ti,index-power-of-two;
1908         };
1909
1910         mmc2_fclk_mux: mmc2_fclk_mux@1330 {
1911                 #clock-cells = <0>;
1912                 compatible = "ti,mux-clock";
1913                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1914                 ti,bit-shift = <24>;
1915                 reg = <0x1330>;
1916         };
1917
1918         mmc2_fclk_div: mmc2_fclk_div@1330 {
1919                 #clock-cells = <0>;
1920                 compatible = "ti,divider-clock";
1921                 clocks = <&mmc2_fclk_mux>;
1922                 ti,bit-shift = <25>;
1923                 ti,max-div = <4>;
1924                 reg = <0x1330>;
1925                 ti,index-power-of-two;
1926         };
1927
1928         mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
1929                 #clock-cells = <0>;
1930                 compatible = "ti,mux-clock";
1931                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1932                 ti,bit-shift = <24>;
1933                 reg = <0x1820>;
1934         };
1935
1936         mmc3_gfclk_div: mmc3_gfclk_div@1820 {
1937                 #clock-cells = <0>;
1938                 compatible = "ti,divider-clock";
1939                 clocks = <&mmc3_gfclk_mux>;
1940                 ti,bit-shift = <25>;
1941                 ti,max-div = <4>;
1942                 reg = <0x1820>;
1943                 ti,index-power-of-two;
1944         };
1945
1946         mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
1947                 #clock-cells = <0>;
1948                 compatible = "ti,mux-clock";
1949                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1950                 ti,bit-shift = <24>;
1951                 reg = <0x1828>;
1952         };
1953
1954         mmc4_gfclk_div: mmc4_gfclk_div@1828 {
1955                 #clock-cells = <0>;
1956                 compatible = "ti,divider-clock";
1957                 clocks = <&mmc4_gfclk_mux>;
1958                 ti,bit-shift = <25>;
1959                 ti,max-div = <4>;
1960                 reg = <0x1828>;
1961                 ti,index-power-of-two;
1962         };
1963
1964         qspi_gfclk_mux: qspi_gfclk_mux@1838 {
1965                 #clock-cells = <0>;
1966                 compatible = "ti,mux-clock";
1967                 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1968                 ti,bit-shift = <24>;
1969                 reg = <0x1838>;
1970         };
1971
1972         qspi_gfclk_div: qspi_gfclk_div@1838 {
1973                 #clock-cells = <0>;
1974                 compatible = "ti,divider-clock";
1975                 clocks = <&qspi_gfclk_mux>;
1976                 ti,bit-shift = <25>;
1977                 ti,max-div = <4>;
1978                 reg = <0x1838>;
1979                 ti,index-power-of-two;
1980         };
1981
1982         timer10_gfclk_mux: timer10_gfclk_mux@1728 {
1983                 #clock-cells = <0>;
1984                 compatible = "ti,mux-clock";
1985                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1986                 ti,bit-shift = <24>;
1987                 reg = <0x1728>;
1988         };
1989
1990         timer11_gfclk_mux: timer11_gfclk_mux@1730 {
1991                 #clock-cells = <0>;
1992                 compatible = "ti,mux-clock";
1993                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1994                 ti,bit-shift = <24>;
1995                 reg = <0x1730>;
1996         };
1997
1998         timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
1999                 #clock-cells = <0>;
2000                 compatible = "ti,mux-clock";
2001                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2002                 ti,bit-shift = <24>;
2003                 reg = <0x17c8>;
2004         };
2005
2006         timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
2007                 #clock-cells = <0>;
2008                 compatible = "ti,mux-clock";
2009                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2010                 ti,bit-shift = <24>;
2011                 reg = <0x17d0>;
2012         };
2013
2014         timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
2015                 #clock-cells = <0>;
2016                 compatible = "ti,mux-clock";
2017                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2018                 ti,bit-shift = <24>;
2019                 reg = <0x17d8>;
2020         };
2021
2022         timer16_gfclk_mux: timer16_gfclk_mux@1830 {
2023                 #clock-cells = <0>;
2024                 compatible = "ti,mux-clock";
2025                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2026                 ti,bit-shift = <24>;
2027                 reg = <0x1830>;
2028         };
2029
2030         timer2_gfclk_mux: timer2_gfclk_mux@1738 {
2031                 #clock-cells = <0>;
2032                 compatible = "ti,mux-clock";
2033                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2034                 ti,bit-shift = <24>;
2035                 reg = <0x1738>;
2036         };
2037
2038         timer3_gfclk_mux: timer3_gfclk_mux@1740 {
2039                 #clock-cells = <0>;
2040                 compatible = "ti,mux-clock";
2041                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2042                 ti,bit-shift = <24>;
2043                 reg = <0x1740>;
2044         };
2045
2046         timer4_gfclk_mux: timer4_gfclk_mux@1748 {
2047                 #clock-cells = <0>;
2048                 compatible = "ti,mux-clock";
2049                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2050                 ti,bit-shift = <24>;
2051                 reg = <0x1748>;
2052         };
2053
2054         timer9_gfclk_mux: timer9_gfclk_mux@1750 {
2055                 #clock-cells = <0>;
2056                 compatible = "ti,mux-clock";
2057                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2058                 ti,bit-shift = <24>;
2059                 reg = <0x1750>;
2060         };
2061
2062         uart1_gfclk_mux: uart1_gfclk_mux@1840 {
2063                 #clock-cells = <0>;
2064                 compatible = "ti,mux-clock";
2065                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2066                 ti,bit-shift = <24>;
2067                 reg = <0x1840>;
2068         };
2069
2070         uart2_gfclk_mux: uart2_gfclk_mux@1848 {
2071                 #clock-cells = <0>;
2072                 compatible = "ti,mux-clock";
2073                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2074                 ti,bit-shift = <24>;
2075                 reg = <0x1848>;
2076         };
2077
2078         uart3_gfclk_mux: uart3_gfclk_mux@1850 {
2079                 #clock-cells = <0>;
2080                 compatible = "ti,mux-clock";
2081                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2082                 ti,bit-shift = <24>;
2083                 reg = <0x1850>;
2084         };
2085
2086         uart4_gfclk_mux: uart4_gfclk_mux@1858 {
2087                 #clock-cells = <0>;
2088                 compatible = "ti,mux-clock";
2089                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2090                 ti,bit-shift = <24>;
2091                 reg = <0x1858>;
2092         };
2093
2094         uart5_gfclk_mux: uart5_gfclk_mux@1870 {
2095                 #clock-cells = <0>;
2096                 compatible = "ti,mux-clock";
2097                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2098                 ti,bit-shift = <24>;
2099                 reg = <0x1870>;
2100         };
2101
2102         uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
2103                 #clock-cells = <0>;
2104                 compatible = "ti,mux-clock";
2105                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2106                 ti,bit-shift = <24>;
2107                 reg = <0x18d0>;
2108         };
2109
2110         uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
2111                 #clock-cells = <0>;
2112                 compatible = "ti,mux-clock";
2113                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2114                 ti,bit-shift = <24>;
2115                 reg = <0x18e0>;
2116         };
2117
2118         uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
2119                 #clock-cells = <0>;
2120                 compatible = "ti,mux-clock";
2121                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2122                 ti,bit-shift = <24>;
2123                 reg = <0x18e8>;
2124         };
2125
2126         vip1_gclk_mux: vip1_gclk_mux@1020 {
2127                 #clock-cells = <0>;
2128                 compatible = "ti,mux-clock";
2129                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2130                 ti,bit-shift = <24>;
2131                 reg = <0x1020>;
2132         };
2133
2134         vip2_gclk_mux: vip2_gclk_mux@1028 {
2135                 #clock-cells = <0>;
2136                 compatible = "ti,mux-clock";
2137                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2138                 ti,bit-shift = <24>;
2139                 reg = <0x1028>;
2140         };
2141
2142         vip3_gclk_mux: vip3_gclk_mux@1030 {
2143                 #clock-cells = <0>;
2144                 compatible = "ti,mux-clock";
2145                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2146                 ti,bit-shift = <24>;
2147                 reg = <0x1030>;
2148         };
2149 };
2150
2151 &cm_core_clockdomains {
2152         coreaon_clkdm: coreaon_clkdm {
2153                 compatible = "ti,clockdomain";
2154                 clocks = <&dpll_usb_ck>;
2155         };
2156 };
2157
2158 &scm_conf_clocks {
2159         dss_deshdcp_clk: dss_deshdcp_clk@558 {
2160                 #clock-cells = <0>;
2161                 compatible = "ti,gate-clock";
2162                 clocks = <&l3_iclk_div>;
2163                 ti,bit-shift = <0>;
2164                 reg = <0x558>;
2165         };
2166
2167        ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
2168                 #clock-cells = <0>;
2169                 compatible = "ti,gate-clock";
2170                 clocks = <&l4_root_clk_div>;
2171                 ti,bit-shift = <20>;
2172                 reg = <0x0558>;
2173         };
2174
2175         ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
2176                 #clock-cells = <0>;
2177                 compatible = "ti,gate-clock";
2178                 clocks = <&l4_root_clk_div>;
2179                 ti,bit-shift = <21>;
2180                 reg = <0x0558>;
2181         };
2182
2183         ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
2184                 #clock-cells = <0>;
2185                 compatible = "ti,gate-clock";
2186                 clocks = <&l4_root_clk_div>;
2187                 ti,bit-shift = <22>;
2188                 reg = <0x0558>;
2189         };
2190
2191         sys_32k_ck: sys_32k_ck {
2192                 #clock-cells = <0>;
2193                 compatible = "ti,mux-clock";
2194                 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
2195                 ti,bit-shift = <8>;
2196                 reg = <0x6c4>;
2197         };
2198 };