arch/arm/boot/dts/dra7xx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for DRA7xx clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &cm_core_aon_clocks {
   8         atl_clkin0_ck: atl_clkin0_ck {
   9                 #clock-cells = <0>;
  10                 compatible = "ti,dra7-atl-clock";
  11                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  12         };
  13
  14         atl_clkin1_ck: atl_clkin1_ck {
  15                 #clock-cells = <0>;
  16                 compatible = "ti,dra7-atl-clock";
  17                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  18         };
  19
  20         atl_clkin2_ck: atl_clkin2_ck {
  21                 #clock-cells = <0>;
  22                 compatible = "ti,dra7-atl-clock";
  23                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  24         };
  25
  26         atl_clkin3_ck: atl_clkin3_ck {
  27                 #clock-cells = <0>;
  28                 compatible = "ti,dra7-atl-clock";
  29                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  30         };
  31
  32         hdmi_clkin_ck: hdmi_clkin_ck {
  33                 #clock-cells = <0>;
  34                 compatible = "fixed-clock";
  35                 clock-frequency = <0>;
  36         };
  37
  38         mlb_clkin_ck: mlb_clkin_ck {
  39                 #clock-cells = <0>;
  40                 compatible = "fixed-clock";
  41                 clock-frequency = <0>;
  42         };
  43
  44         mlbp_clkin_ck: mlbp_clkin_ck {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47                 clock-frequency = <0>;
  48         };
  49
  50         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  51                 #clock-cells = <0>;
  52                 compatible = "fixed-clock";
  53                 clock-frequency = <100000000>;
  54         };
  55
  56         ref_clkin0_ck: ref_clkin0_ck {
  57                 #clock-cells = <0>;
  58                 compatible = "fixed-clock";
  59                 clock-frequency = <0>;
  60         };
  61
  62         ref_clkin1_ck: ref_clkin1_ck {
  63                 #clock-cells = <0>;
  64                 compatible = "fixed-clock";
  65                 clock-frequency = <0>;
  66         };
  67
  68         ref_clkin2_ck: ref_clkin2_ck {
  69                 #clock-cells = <0>;
  70                 compatible = "fixed-clock";
  71                 clock-frequency = <0>;
  72         };
  73
  74         ref_clkin3_ck: ref_clkin3_ck {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-clock";
  77                 clock-frequency = <0>;
  78         };
  79
  80         rmii_clk_ck: rmii_clk_ck {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-clock";
  83                 clock-frequency = <0>;
  84         };
  85
  86         sdvenc_clkin_ck: sdvenc_clkin_ck {
  87                 #clock-cells = <0>;
  88                 compatible = "fixed-clock";
  89                 clock-frequency = <0>;
  90         };
  91
  92         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  93                 #clock-cells = <0>;
  94                 compatible = "fixed-clock";
  95                 clock-frequency = <32768>;
  96         };
  97
  98         sys_clk32_crystal_ck: sys_clk32_crystal_ck {
  99                 #clock-cells = <0>;
 100                 compatible = "fixed-clock";
 101                 clock-frequency = <32768>;
 102         };
 103
 104         sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
 105                 #clock-cells = <0>;
 106                 compatible = "fixed-factor-clock";
 107                 clocks = <&sys_clkin1>;
 108                 clock-mult = <1>;
 109                 clock-div = <610>;
 110         };
 111
 112         virt_12000000_ck: virt_12000000_ck {
 113                 #clock-cells = <0>;
 114                 compatible = "fixed-clock";
 115                 clock-frequency = <12000000>;
 116         };
 117
 118         virt_13000000_ck: virt_13000000_ck {
 119                 #clock-cells = <0>;
 120                 compatible = "fixed-clock";
 121                 clock-frequency = <13000000>;
 122         };
 123
 124         virt_16800000_ck: virt_16800000_ck {
 125                 #clock-cells = <0>;
 126                 compatible = "fixed-clock";
 127                 clock-frequency = <16800000>;
 128         };
 129
 130         virt_19200000_ck: virt_19200000_ck {
 131                 #clock-cells = <0>;
 132                 compatible = "fixed-clock";
 133                 clock-frequency = <19200000>;
 134         };
 135
 136         virt_20000000_ck: virt_20000000_ck {
 137                 #clock-cells = <0>;
 138                 compatible = "fixed-clock";
 139                 clock-frequency = <20000000>;
 140         };
 141
 142         virt_26000000_ck: virt_26000000_ck {
 143                 #clock-cells = <0>;
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <26000000>;
 146         };
 147
 148         virt_27000000_ck: virt_27000000_ck {
 149                 #clock-cells = <0>;
 150                 compatible = "fixed-clock";
 151                 clock-frequency = <27000000>;
 152         };
 153
 154         virt_38400000_ck: virt_38400000_ck {
 155                 #clock-cells = <0>;
 156                 compatible = "fixed-clock";
 157                 clock-frequency = <38400000>;
 158         };
 159
 160         sys_clkin2: sys_clkin2 {
 161                 #clock-cells = <0>;
 162                 compatible = "fixed-clock";
 163                 clock-frequency = <22579200>;
 164         };
 165
 166         usb_otg_clkin_ck: usb_otg_clkin_ck {
 167                 #clock-cells = <0>;
 168                 compatible = "fixed-clock";
 169                 clock-frequency = <0>;
 170         };
 171
 172         video1_clkin_ck: video1_clkin_ck {
 173                 #clock-cells = <0>;
 174                 compatible = "fixed-clock";
 175                 clock-frequency = <0>;
 176         };
 177
 178         video1_m2_clkin_ck: video1_m2_clkin_ck {
 179                 #clock-cells = <0>;
 180                 compatible = "fixed-clock";
 181                 clock-frequency = <0>;
 182         };
 183
 184         video2_clkin_ck: video2_clkin_ck {
 185                 #clock-cells = <0>;
 186                 compatible = "fixed-clock";
 187                 clock-frequency = <0>;
 188         };
 189
 190         video2_m2_clkin_ck: video2_m2_clkin_ck {
 191                 #clock-cells = <0>;
 192                 compatible = "fixed-clock";
 193                 clock-frequency = <0>;
 194         };
 195
 196         dpll_abe_ck: dpll_abe_ck@1e0 {
 197                 #clock-cells = <0>;
 198                 compatible = "ti,omap4-dpll-m4xen-clock";
 199                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 200                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 201         };
 202
 203         dpll_abe_x2_ck: dpll_abe_x2_ck {
 204                 #clock-cells = <0>;
 205                 compatible = "ti,omap4-dpll-x2-clock";
 206                 clocks = <&dpll_abe_ck>;
 207         };
 208
 209         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 210                 #clock-cells = <0>;
 211                 compatible = "ti,divider-clock";
 212                 clocks = <&dpll_abe_x2_ck>;
 213                 ti,max-div = <31>;
 214                 ti,autoidle-shift = <8>;
 215                 reg = <0x01f0>;
 216                 ti,index-starts-at-one;
 217                 ti,invert-autoidle-bit;
 218         };
 219
 220         abe_clk: abe_clk@108 {
 221                 #clock-cells = <0>;
 222                 compatible = "ti,divider-clock";
 223                 clocks = <&dpll_abe_m2x2_ck>;
 224                 ti,max-div = <4>;
 225                 reg = <0x0108>;
 226                 ti,index-power-of-two;
 227         };
 228
 229         dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 230                 #clock-cells = <0>;
 231                 compatible = "ti,divider-clock";
 232                 clocks = <&dpll_abe_ck>;
 233                 ti,max-div = <31>;
 234                 ti,autoidle-shift = <8>;
 235                 reg = <0x01f0>;
 236                 ti,index-starts-at-one;
 237                 ti,invert-autoidle-bit;
 238         };
 239
 240         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 241                 #clock-cells = <0>;
 242                 compatible = "ti,divider-clock";
 243                 clocks = <&dpll_abe_x2_ck>;
 244                 ti,max-div = <31>;
 245                 ti,autoidle-shift = <8>;
 246                 reg = <0x01f4>;
 247                 ti,index-starts-at-one;
 248                 ti,invert-autoidle-bit;
 249         };
 250
 251         dpll_core_byp_mux: dpll_core_byp_mux@12c {
 252                 #clock-cells = <0>;
 253                 compatible = "ti,mux-clock";
 254                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 255                 ti,bit-shift = <23>;
 256                 reg = <0x012c>;
 257         };
 258
 259         dpll_core_ck: dpll_core_ck@120 {
 260                 #clock-cells = <0>;
 261                 compatible = "ti,omap4-dpll-core-clock";
 262                 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 263                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 264         };
 265
 266         dpll_core_x2_ck: dpll_core_x2_ck {
 267                 #clock-cells = <0>;
 268                 compatible = "ti,omap4-dpll-x2-clock";
 269                 clocks = <&dpll_core_ck>;
 270         };
 271
 272         dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 273                 #clock-cells = <0>;
 274                 compatible = "ti,divider-clock";
 275                 clocks = <&dpll_core_x2_ck>;
 276                 ti,max-div = <63>;
 277                 ti,autoidle-shift = <8>;
 278                 reg = <0x013c>;
 279                 ti,index-starts-at-one;
 280                 ti,invert-autoidle-bit;
 281         };
 282
 283         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 284                 #clock-cells = <0>;
 285                 compatible = "fixed-factor-clock";
 286                 clocks = <&dpll_core_h12x2_ck>;
 287                 clock-mult = <1>;
 288                 clock-div = <1>;
 289         };
 290
 291         dpll_mpu_ck: dpll_mpu_ck@160 {
 292                 #clock-cells = <0>;
 293                 compatible = "ti,omap5-mpu-dpll-clock";
 294                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 295                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 296         };
 297
 298         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 299                 #clock-cells = <0>;
 300                 compatible = "ti,divider-clock";
 301                 clocks = <&dpll_mpu_ck>;
 302                 ti,max-div = <31>;
 303                 ti,autoidle-shift = <8>;
 304                 reg = <0x0170>;
 305                 ti,index-starts-at-one;
 306                 ti,invert-autoidle-bit;
 307         };
 308
 309         mpu_dclk_div: mpu_dclk_div {
 310                 #clock-cells = <0>;
 311                 compatible = "fixed-factor-clock";
 312                 clocks = <&dpll_mpu_m2_ck>;
 313                 clock-mult = <1>;
 314                 clock-div = <1>;
 315         };
 316
 317         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 318                 #clock-cells = <0>;
 319                 compatible = "fixed-factor-clock";
 320                 clocks = <&dpll_core_h12x2_ck>;
 321                 clock-mult = <1>;
 322                 clock-div = <1>;
 323         };
 324
 325         dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 326                 #clock-cells = <0>;
 327                 compatible = "ti,mux-clock";
 328                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 329                 ti,bit-shift = <23>;
 330                 reg = <0x0240>;
 331         };
 332
 333         dpll_dsp_ck: dpll_dsp_ck@234 {
 334                 #clock-cells = <0>;
 335                 compatible = "ti,omap4-dpll-clock";
 336                 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 337                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 338                 assigned-clocks = <&dpll_dsp_ck>;
 339                 assigned-clock-rates = <600000000>;
 340         };
 341
 342         dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 343                 #clock-cells = <0>;
 344                 compatible = "ti,divider-clock";
 345                 clocks = <&dpll_dsp_ck>;
 346                 ti,max-div = <31>;
 347                 ti,autoidle-shift = <8>;
 348                 reg = <0x0244>;
 349                 ti,index-starts-at-one;
 350                 ti,invert-autoidle-bit;
 351                 assigned-clocks = <&dpll_dsp_m2_ck>;
 352                 assigned-clock-rates = <600000000>;
 353         };
 354
 355         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 356                 #clock-cells = <0>;
 357                 compatible = "fixed-factor-clock";
 358                 clocks = <&dpll_core_h12x2_ck>;
 359                 clock-mult = <1>;
 360                 clock-div = <1>;
 361         };
 362
 363         dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 364                 #clock-cells = <0>;
 365                 compatible = "ti,mux-clock";
 366                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 367                 ti,bit-shift = <23>;
 368                 reg = <0x01ac>;
 369         };
 370
 371         dpll_iva_ck: dpll_iva_ck@1a0 {
 372                 #clock-cells = <0>;
 373                 compatible = "ti,omap4-dpll-clock";
 374                 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 375                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 376                 assigned-clocks = <&dpll_iva_ck>;
 377                 assigned-clock-rates = <1165000000>;
 378         };
 379
 380         dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 381                 #clock-cells = <0>;
 382                 compatible = "ti,divider-clock";
 383                 clocks = <&dpll_iva_ck>;
 384                 ti,max-div = <31>;
 385                 ti,autoidle-shift = <8>;
 386                 reg = <0x01b0>;
 387                 ti,index-starts-at-one;
 388                 ti,invert-autoidle-bit;
 389                 assigned-clocks = <&dpll_iva_m2_ck>;
 390                 assigned-clock-rates = <388333334>;
 391         };
 392
 393         iva_dclk: iva_dclk {
 394                 #clock-cells = <0>;
 395                 compatible = "fixed-factor-clock";
 396                 clocks = <&dpll_iva_m2_ck>;
 397                 clock-mult = <1>;
 398                 clock-div = <1>;
 399         };
 400
 401         dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 402                 #clock-cells = <0>;
 403                 compatible = "ti,mux-clock";
 404                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 405                 ti,bit-shift = <23>;
 406                 reg = <0x02e4>;
 407         };
 408
 409         dpll_gpu_ck: dpll_gpu_ck@2d8 {
 410                 #clock-cells = <0>;
 411                 compatible = "ti,omap4-dpll-clock";
 412                 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 413                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 414                 assigned-clocks = <&dpll_gpu_ck>;
 415                 assigned-clock-rates = <1277000000>;
 416         };
 417
 418         dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 419                 #clock-cells = <0>;
 420                 compatible = "ti,divider-clock";
 421                 clocks = <&dpll_gpu_ck>;
 422                 ti,max-div = <31>;
 423                 ti,autoidle-shift = <8>;
 424                 reg = <0x02e8>;
 425                 ti,index-starts-at-one;
 426                 ti,invert-autoidle-bit;
 427                 assigned-clocks = <&dpll_gpu_m2_ck>;
 428                 assigned-clock-rates = <425666667>;
 429         };
 430
 431         dpll_core_m2_ck: dpll_core_m2_ck@130 {
 432                 #clock-cells = <0>;
 433                 compatible = "ti,divider-clock";
 434                 clocks = <&dpll_core_ck>;
 435                 ti,max-div = <31>;
 436                 ti,autoidle-shift = <8>;
 437                 reg = <0x0130>;
 438                 ti,index-starts-at-one;
 439                 ti,invert-autoidle-bit;
 440         };
 441
 442         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 443                 #clock-cells = <0>;
 444                 compatible = "fixed-factor-clock";
 445                 clocks = <&dpll_core_m2_ck>;
 446                 clock-mult = <1>;
 447                 clock-div = <1>;
 448         };
 449
 450         dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 451                 #clock-cells = <0>;
 452                 compatible = "ti,mux-clock";
 453                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 454                 ti,bit-shift = <23>;
 455                 reg = <0x021c>;
 456         };
 457
 458         dpll_ddr_ck: dpll_ddr_ck@210 {
 459                 #clock-cells = <0>;
 460                 compatible = "ti,omap4-dpll-clock";
 461                 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 462                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 463         };
 464
 465         dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 466                 #clock-cells = <0>;
 467                 compatible = "ti,divider-clock";
 468                 clocks = <&dpll_ddr_ck>;
 469                 ti,max-div = <31>;
 470                 ti,autoidle-shift = <8>;
 471                 reg = <0x0220>;
 472                 ti,index-starts-at-one;
 473                 ti,invert-autoidle-bit;
 474         };
 475
 476         dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 477                 #clock-cells = <0>;
 478                 compatible = "ti,mux-clock";
 479                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 480                 ti,bit-shift = <23>;
 481                 reg = <0x02b4>;
 482         };
 483
 484         dpll_gmac_ck: dpll_gmac_ck@2a8 {
 485                 #clock-cells = <0>;
 486                 compatible = "ti,omap4-dpll-clock";
 487                 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 488                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 489         };
 490
 491         dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 492                 #clock-cells = <0>;
 493                 compatible = "ti,divider-clock";
 494                 clocks = <&dpll_gmac_ck>;
 495                 ti,max-div = <31>;
 496                 ti,autoidle-shift = <8>;
 497                 reg = <0x02b8>;
 498                 ti,index-starts-at-one;
 499                 ti,invert-autoidle-bit;
 500         };
 501
 502         video2_dclk_div: video2_dclk_div {
 503                 #clock-cells = <0>;
 504                 compatible = "fixed-factor-clock";
 505                 clocks = <&video2_m2_clkin_ck>;
 506                 clock-mult = <1>;
 507                 clock-div = <1>;
 508         };
 509
 510         video1_dclk_div: video1_dclk_div {
 511                 #clock-cells = <0>;
 512                 compatible = "fixed-factor-clock";
 513                 clocks = <&video1_m2_clkin_ck>;
 514                 clock-mult = <1>;
 515                 clock-div = <1>;
 516         };
 517
 518         hdmi_dclk_div: hdmi_dclk_div {
 519                 #clock-cells = <0>;
 520                 compatible = "fixed-factor-clock";
 521                 clocks = <&hdmi_clkin_ck>;
 522                 clock-mult = <1>;
 523                 clock-div = <1>;
 524         };
 525
 526         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 527                 #clock-cells = <0>;
 528                 compatible = "fixed-factor-clock";
 529                 clocks = <&dpll_abe_m3x2_ck>;
 530                 clock-mult = <1>;
 531                 clock-div = <2>;
 532         };
 533
 534         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 535                 #clock-cells = <0>;
 536                 compatible = "fixed-factor-clock";
 537                 clocks = <&dpll_abe_m3x2_ck>;
 538                 clock-mult = <1>;
 539                 clock-div = <3>;
 540         };
 541
 542         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 543                 #clock-cells = <0>;
 544                 compatible = "fixed-factor-clock";
 545                 clocks = <&dpll_core_h12x2_ck>;
 546                 clock-mult = <1>;
 547                 clock-div = <1>;
 548         };
 549
 550         dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 551                 #clock-cells = <0>;
 552                 compatible = "ti,mux-clock";
 553                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 554                 ti,bit-shift = <23>;
 555                 reg = <0x0290>;
 556         };
 557
 558         dpll_eve_ck: dpll_eve_ck@284 {
 559                 #clock-cells = <0>;
 560                 compatible = "ti,omap4-dpll-clock";
 561                 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 562                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 563         };
 564
 565         dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 566                 #clock-cells = <0>;
 567                 compatible = "ti,divider-clock";
 568                 clocks = <&dpll_eve_ck>;
 569                 ti,max-div = <31>;
 570                 ti,autoidle-shift = <8>;
 571                 reg = <0x0294>;
 572                 ti,index-starts-at-one;
 573                 ti,invert-autoidle-bit;
 574         };
 575
 576         eve_dclk_div: eve_dclk_div {
 577                 #clock-cells = <0>;
 578                 compatible = "fixed-factor-clock";
 579                 clocks = <&dpll_eve_m2_ck>;
 580                 clock-mult = <1>;
 581                 clock-div = <1>;
 582         };
 583
 584         dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 585                 #clock-cells = <0>;
 586                 compatible = "ti,divider-clock";
 587                 clocks = <&dpll_core_x2_ck>;
 588                 ti,max-div = <63>;
 589                 ti,autoidle-shift = <8>;
 590                 reg = <0x0140>;
 591                 ti,index-starts-at-one;
 592                 ti,invert-autoidle-bit;
 593         };
 594
 595         dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 596                 #clock-cells = <0>;
 597                 compatible = "ti,divider-clock";
 598                 clocks = <&dpll_core_x2_ck>;
 599                 ti,max-div = <63>;
 600                 ti,autoidle-shift = <8>;
 601                 reg = <0x0144>;
 602                 ti,index-starts-at-one;
 603                 ti,invert-autoidle-bit;
 604         };
 605
 606         dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 607                 #clock-cells = <0>;
 608                 compatible = "ti,divider-clock";
 609                 clocks = <&dpll_core_x2_ck>;
 610                 ti,max-div = <63>;
 611                 ti,autoidle-shift = <8>;
 612                 reg = <0x0154>;
 613                 ti,index-starts-at-one;
 614                 ti,invert-autoidle-bit;
 615         };
 616
 617         dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 618                 #clock-cells = <0>;
 619                 compatible = "ti,divider-clock";
 620                 clocks = <&dpll_core_x2_ck>;
 621                 ti,max-div = <63>;
 622                 ti,autoidle-shift = <8>;
 623                 reg = <0x0158>;
 624                 ti,index-starts-at-one;
 625                 ti,invert-autoidle-bit;
 626         };
 627
 628         dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 629                 #clock-cells = <0>;
 630                 compatible = "ti,divider-clock";
 631                 clocks = <&dpll_core_x2_ck>;
 632                 ti,max-div = <63>;
 633                 ti,autoidle-shift = <8>;
 634                 reg = <0x015c>;
 635                 ti,index-starts-at-one;
 636                 ti,invert-autoidle-bit;
 637         };
 638
 639         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 640                 #clock-cells = <0>;
 641                 compatible = "ti,omap4-dpll-x2-clock";
 642                 clocks = <&dpll_ddr_ck>;
 643         };
 644
 645         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 646                 #clock-cells = <0>;
 647                 compatible = "ti,divider-clock";
 648                 clocks = <&dpll_ddr_x2_ck>;
 649                 ti,max-div = <63>;
 650                 ti,autoidle-shift = <8>;
 651                 reg = <0x0228>;
 652                 ti,index-starts-at-one;
 653                 ti,invert-autoidle-bit;
 654         };
 655
 656         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 657                 #clock-cells = <0>;
 658                 compatible = "ti,omap4-dpll-x2-clock";
 659                 clocks = <&dpll_dsp_ck>;
 660         };
 661
 662         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 663                 #clock-cells = <0>;
 664                 compatible = "ti,divider-clock";
 665                 clocks = <&dpll_dsp_x2_ck>;
 666                 ti,max-div = <31>;
 667                 ti,autoidle-shift = <8>;
 668                 reg = <0x0248>;
 669                 ti,index-starts-at-one;
 670                 ti,invert-autoidle-bit;
 671                 assigned-clocks = <&dpll_dsp_m3x2_ck>;
 672                 assigned-clock-rates = <400000000>;
 673         };
 674
 675         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 676                 #clock-cells = <0>;
 677                 compatible = "ti,omap4-dpll-x2-clock";
 678                 clocks = <&dpll_gmac_ck>;
 679         };
 680
 681         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 682                 #clock-cells = <0>;
 683                 compatible = "ti,divider-clock";
 684                 clocks = <&dpll_gmac_x2_ck>;
 685                 ti,max-div = <63>;
 686                 ti,autoidle-shift = <8>;
 687                 reg = <0x02c0>;
 688                 ti,index-starts-at-one;
 689                 ti,invert-autoidle-bit;
 690         };
 691
 692         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 693                 #clock-cells = <0>;
 694                 compatible = "ti,divider-clock";
 695                 clocks = <&dpll_gmac_x2_ck>;
 696                 ti,max-div = <63>;
 697                 ti,autoidle-shift = <8>;
 698                 reg = <0x02c4>;
 699                 ti,index-starts-at-one;
 700                 ti,invert-autoidle-bit;
 701         };
 702
 703         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 704                 #clock-cells = <0>;
 705                 compatible = "ti,divider-clock";
 706                 clocks = <&dpll_gmac_x2_ck>;
 707                 ti,max-div = <63>;
 708                 ti,autoidle-shift = <8>;
 709                 reg = <0x02c8>;
 710                 ti,index-starts-at-one;
 711                 ti,invert-autoidle-bit;
 712         };
 713
 714         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 715                 #clock-cells = <0>;
 716                 compatible = "ti,divider-clock";
 717                 clocks = <&dpll_gmac_x2_ck>;
 718                 ti,max-div = <31>;
 719                 ti,autoidle-shift = <8>;
 720                 reg = <0x02bc>;
 721                 ti,index-starts-at-one;
 722                 ti,invert-autoidle-bit;
 723         };
 724
 725         gmii_m_clk_div: gmii_m_clk_div {
 726                 #clock-cells = <0>;
 727                 compatible = "fixed-factor-clock";
 728                 clocks = <&dpll_gmac_h11x2_ck>;
 729                 clock-mult = <1>;
 730                 clock-div = <2>;
 731         };
 732
 733         hdmi_clk2_div: hdmi_clk2_div {
 734                 #clock-cells = <0>;
 735                 compatible = "fixed-factor-clock";
 736                 clocks = <&hdmi_clkin_ck>;
 737                 clock-mult = <1>;
 738                 clock-div = <1>;
 739         };
 740
 741         hdmi_div_clk: hdmi_div_clk {
 742                 #clock-cells = <0>;
 743                 compatible = "fixed-factor-clock";
 744                 clocks = <&hdmi_clkin_ck>;
 745                 clock-mult = <1>;
 746                 clock-div = <1>;
 747         };
 748
 749         l3_iclk_div: l3_iclk_div@100 {
 750                 #clock-cells = <0>;
 751                 compatible = "ti,divider-clock";
 752                 ti,max-div = <2>;
 753                 ti,bit-shift = <4>;
 754                 reg = <0x0100>;
 755                 clocks = <&dpll_core_h12x2_ck>;
 756                 ti,index-power-of-two;
 757         };
 758
 759         l4_root_clk_div: l4_root_clk_div {
 760                 #clock-cells = <0>;
 761                 compatible = "fixed-factor-clock";
 762                 clocks = <&l3_iclk_div>;
 763                 clock-mult = <1>;
 764                 clock-div = <2>;
 765         };
 766
 767         video1_clk2_div: video1_clk2_div {
 768                 #clock-cells = <0>;
 769                 compatible = "fixed-factor-clock";
 770                 clocks = <&video1_clkin_ck>;
 771                 clock-mult = <1>;
 772                 clock-div = <1>;
 773         };
 774
 775         video1_div_clk: video1_div_clk {
 776                 #clock-cells = <0>;
 777                 compatible = "fixed-factor-clock";
 778                 clocks = <&video1_clkin_ck>;
 779                 clock-mult = <1>;
 780                 clock-div = <1>;
 781         };
 782
 783         video2_clk2_div: video2_clk2_div {
 784                 #clock-cells = <0>;
 785                 compatible = "fixed-factor-clock";
 786                 clocks = <&video2_clkin_ck>;
 787                 clock-mult = <1>;
 788                 clock-div = <1>;
 789         };
 790
 791         video2_div_clk: video2_div_clk {
 792                 #clock-cells = <0>;
 793                 compatible = "fixed-factor-clock";
 794                 clocks = <&video2_clkin_ck>;
 795                 clock-mult = <1>;
 796                 clock-div = <1>;
 797         };
 798
 799         ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
 800                 #clock-cells = <0>;
 801                 compatible = "ti,mux-clock";
 802                 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 803                 ti,bit-shift = <24>;
 804                 reg = <0x0520>;
 805                 assigned-clocks = <&ipu1_gfclk_mux>;
 806                 assigned-clock-parents = <&dpll_core_h22x2_ck>;
 807         };
 808
 809         dummy_ck: dummy_ck {
 810                 #clock-cells = <0>;
 811                 compatible = "fixed-clock";
 812                 clock-frequency = <0>;
 813         };
 814 };
 815 &prm_clocks {
 816         sys_clkin1: sys_clkin1@110 {
 817                 #clock-cells = <0>;
 818                 compatible = "ti,mux-clock";
 819                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 820                 reg = <0x0110>;
 821                 ti,index-starts-at-one;
 822         };
 823
 824         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 825                 #clock-cells = <0>;
 826                 compatible = "ti,mux-clock";
 827                 clocks = <&sys_clkin1>, <&sys_clkin2>;
 828                 reg = <0x0118>;
 829         };
 830
 831         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 832                 #clock-cells = <0>;
 833                 compatible = "ti,mux-clock";
 834                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 835                 reg = <0x0114>;
 836         };
 837
 838         abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 839                 #clock-cells = <0>;
 840                 compatible = "ti,mux-clock";
 841                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 842                 reg = <0x010c>;
 843         };
 844
 845         abe_24m_fclk: abe_24m_fclk@11c {
 846                 #clock-cells = <0>;
 847                 compatible = "ti,divider-clock";
 848                 clocks = <&dpll_abe_m2x2_ck>;
 849                 reg = <0x011c>;
 850                 ti,dividers = <8>, <16>;
 851         };
 852
 853         aess_fclk: aess_fclk@178 {
 854                 #clock-cells = <0>;
 855                 compatible = "ti,divider-clock";
 856                 clocks = <&abe_clk>;
 857                 reg = <0x0178>;
 858                 ti,max-div = <2>;
 859         };
 860
 861         abe_giclk_div: abe_giclk_div@174 {
 862                 #clock-cells = <0>;
 863                 compatible = "ti,divider-clock";
 864                 clocks = <&aess_fclk>;
 865                 reg = <0x0174>;
 866                 ti,max-div = <2>;
 867         };
 868
 869         abe_lp_clk_div: abe_lp_clk_div@1d8 {
 870                 #clock-cells = <0>;
 871                 compatible = "ti,divider-clock";
 872                 clocks = <&dpll_abe_m2x2_ck>;
 873                 reg = <0x01d8>;
 874                 ti,dividers = <16>, <32>;
 875         };
 876
 877         abe_sys_clk_div: abe_sys_clk_div@120 {
 878                 #clock-cells = <0>;
 879                 compatible = "ti,divider-clock";
 880                 clocks = <&sys_clkin1>;
 881                 reg = <0x0120>;
 882                 ti,max-div = <2>;
 883         };
 884
 885         adc_gfclk_mux: adc_gfclk_mux@1dc {
 886                 #clock-cells = <0>;
 887                 compatible = "ti,mux-clock";
 888                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 889                 reg = <0x01dc>;
 890         };
 891
 892         sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 893                 #clock-cells = <0>;
 894                 compatible = "ti,divider-clock";
 895                 clocks = <&sys_clkin1>;
 896                 ti,max-div = <64>;
 897                 reg = <0x01c8>;
 898                 ti,index-power-of-two;
 899         };
 900
 901         sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 902                 #clock-cells = <0>;
 903                 compatible = "ti,divider-clock";
 904                 clocks = <&sys_clkin2>;
 905                 ti,max-div = <64>;
 906                 reg = <0x01cc>;
 907                 ti,index-power-of-two;
 908         };
 909
 910         per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 911                 #clock-cells = <0>;
 912                 compatible = "ti,divider-clock";
 913                 clocks = <&dpll_abe_m2_ck>;
 914                 ti,max-div = <64>;
 915                 reg = <0x01bc>;
 916                 ti,index-power-of-two;
 917         };
 918
 919         dsp_gclk_div: dsp_gclk_div@18c {
 920                 #clock-cells = <0>;
 921                 compatible = "ti,divider-clock";
 922                 clocks = <&dpll_dsp_m2_ck>;
 923                 ti,max-div = <64>;
 924                 reg = <0x018c>;
 925                 ti,index-power-of-two;
 926         };
 927
 928         gpu_dclk: gpu_dclk@1a0 {
 929                 #clock-cells = <0>;
 930                 compatible = "ti,divider-clock";
 931                 clocks = <&dpll_gpu_m2_ck>;
 932                 ti,max-div = <64>;
 933                 reg = <0x01a0>;
 934                 ti,index-power-of-two;
 935         };
 936
 937         emif_phy_dclk_div: emif_phy_dclk_div@190 {
 938                 #clock-cells = <0>;
 939                 compatible = "ti,divider-clock";
 940                 clocks = <&dpll_ddr_m2_ck>;
 941                 ti,max-div = <64>;
 942                 reg = <0x0190>;
 943                 ti,index-power-of-two;
 944         };
 945
 946         gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
 947                 #clock-cells = <0>;
 948                 compatible = "ti,divider-clock";
 949                 clocks = <&dpll_gmac_m2_ck>;
 950                 ti,max-div = <64>;
 951                 reg = <0x019c>;
 952                 ti,index-power-of-two;
 953         };
 954
 955         gmac_main_clk: gmac_main_clk {
 956                 #clock-cells = <0>;
 957                 compatible = "fixed-factor-clock";
 958                 clocks = <&gmac_250m_dclk_div>;
 959                 clock-mult = <1>;
 960                 clock-div = <2>;
 961         };
 962
 963         l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
 964                 #clock-cells = <0>;
 965                 compatible = "ti,divider-clock";
 966                 clocks = <&dpll_usb_m2_ck>;
 967                 ti,max-div = <64>;
 968                 reg = <0x01ac>;
 969                 ti,index-power-of-two;
 970         };
 971
 972         usb_otg_dclk_div: usb_otg_dclk_div@184 {
 973                 #clock-cells = <0>;
 974                 compatible = "ti,divider-clock";
 975                 clocks = <&usb_otg_clkin_ck>;
 976                 ti,max-div = <64>;
 977                 reg = <0x0184>;
 978                 ti,index-power-of-two;
 979         };
 980
 981         sata_dclk_div: sata_dclk_div@1c0 {
 982                 #clock-cells = <0>;
 983                 compatible = "ti,divider-clock";
 984                 clocks = <&sys_clkin1>;
 985                 ti,max-div = <64>;
 986                 reg = <0x01c0>;
 987                 ti,index-power-of-two;
 988         };
 989
 990         pcie2_dclk_div: pcie2_dclk_div@1b8 {
 991                 #clock-cells = <0>;
 992                 compatible = "ti,divider-clock";
 993                 clocks = <&dpll_pcie_ref_m2_ck>;
 994                 ti,max-div = <64>;
 995                 reg = <0x01b8>;
 996                 ti,index-power-of-two;
 997         };
 998
 999         pcie_dclk_div: pcie_dclk_div@1b4 {
1000                 #clock-cells = <0>;
1001                 compatible = "ti,divider-clock";
1002                 clocks = <&apll_pcie_m2_ck>;
1003                 ti,max-div = <64>;
1004                 reg = <0x01b4>;
1005                 ti,index-power-of-two;
1006         };
1007
1008         emu_dclk_div: emu_dclk_div@194 {
1009                 #clock-cells = <0>;
1010                 compatible = "ti,divider-clock";
1011                 clocks = <&sys_clkin1>;
1012                 ti,max-div = <64>;
1013                 reg = <0x0194>;
1014                 ti,index-power-of-two;
1015         };
1016
1017         secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1018                 #clock-cells = <0>;
1019                 compatible = "ti,divider-clock";
1020                 clocks = <&secure_32k_clk_src_ck>;
1021                 ti,max-div = <64>;
1022                 reg = <0x01c4>;
1023                 ti,index-power-of-two;
1024         };
1025
1026         clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1027                 #clock-cells = <0>;
1028                 compatible = "ti,mux-clock";
1029                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1030                 reg = <0x0158>;
1031         };
1032
1033         clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1034                 #clock-cells = <0>;
1035                 compatible = "ti,mux-clock";
1036                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1037                 reg = <0x015c>;
1038         };
1039
1040         clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1041                 #clock-cells = <0>;
1042                 compatible = "ti,mux-clock";
1043                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1044                 reg = <0x0160>;
1045         };
1046
1047         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1048                 #clock-cells = <0>;
1049                 compatible = "fixed-factor-clock";
1050                 clocks = <&sys_clkin1>;
1051                 clock-mult = <1>;
1052                 clock-div = <2>;
1053         };
1054
1055         eve_clk: eve_clk@180 {
1056                 #clock-cells = <0>;
1057                 compatible = "ti,mux-clock";
1058                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1059                 reg = <0x0180>;
1060         };
1061
1062         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1063                 #clock-cells = <0>;
1064                 compatible = "ti,mux-clock";
1065                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1066                 reg = <0x0164>;
1067         };
1068
1069         mlb_clk: mlb_clk@134 {
1070                 #clock-cells = <0>;
1071                 compatible = "ti,divider-clock";
1072                 clocks = <&mlb_clkin_ck>;
1073                 ti,max-div = <64>;
1074                 reg = <0x0134>;
1075                 ti,index-power-of-two;
1076         };
1077
1078         mlbp_clk: mlbp_clk@130 {
1079                 #clock-cells = <0>;
1080                 compatible = "ti,divider-clock";
1081                 clocks = <&mlbp_clkin_ck>;
1082                 ti,max-div = <64>;
1083                 reg = <0x0130>;
1084                 ti,index-power-of-two;
1085         };
1086
1087         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1088                 #clock-cells = <0>;
1089                 compatible = "ti,divider-clock";
1090                 clocks = <&dpll_abe_m2_ck>;
1091                 ti,max-div = <64>;
1092                 reg = <0x0138>;
1093                 ti,index-power-of-two;
1094         };
1095
1096         timer_sys_clk_div: timer_sys_clk_div@144 {
1097                 #clock-cells = <0>;
1098                 compatible = "ti,divider-clock";
1099                 clocks = <&sys_clkin1>;
1100                 reg = <0x0144>;
1101                 ti,max-div = <2>;
1102         };
1103
1104         video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1105                 #clock-cells = <0>;
1106                 compatible = "ti,mux-clock";
1107                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1108                 reg = <0x0168>;
1109         };
1110
1111         video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1112                 #clock-cells = <0>;
1113                 compatible = "ti,mux-clock";
1114                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1115                 reg = <0x016c>;
1116         };
1117
1118         wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1119                 #clock-cells = <0>;
1120                 compatible = "ti,mux-clock";
1121                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1122                 reg = <0x0108>;
1123         };
1124 };
1125
1126 &cm_core_clocks {
1127         dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1128                 #clock-cells = <0>;
1129                 compatible = "ti,omap4-dpll-clock";
1130                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1131                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1132         };
1133
1134         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1135                 #clock-cells = <0>;
1136                 compatible = "ti,divider-clock";
1137                 clocks = <&dpll_pcie_ref_ck>;
1138                 ti,max-div = <31>;
1139                 ti,autoidle-shift = <8>;
1140                 reg = <0x0210>;
1141                 ti,index-starts-at-one;
1142                 ti,invert-autoidle-bit;
1143         };
1144
1145         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1146                 compatible = "ti,mux-clock";
1147                 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1148                 #clock-cells = <0>;
1149                 reg = <0x021c 0x4>;
1150                 ti,bit-shift = <7>;
1151         };
1152
1153         apll_pcie_ck: apll_pcie_ck@21c {
1154                 #clock-cells = <0>;
1155                 compatible = "ti,dra7-apll-clock";
1156                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1157                 reg = <0x021c>, <0x0220>;
1158         };
1159
1160         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1161                 compatible = "ti,divider-clock";
1162                 clocks = <&apll_pcie_ck>;
1163                 #clock-cells = <0>;
1164                 reg = <0x021c>;
1165                 ti,dividers = <2>, <1>;
1166                 ti,bit-shift = <8>;
1167                 ti,max-div = <2>;
1168         };
1169
1170         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1171                 #clock-cells = <0>;
1172                 compatible = "fixed-factor-clock";
1173                 clocks = <&apll_pcie_ck>;
1174                 clock-mult = <1>;
1175                 clock-div = <1>;
1176         };
1177
1178         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1179                 #clock-cells = <0>;
1180                 compatible = "fixed-factor-clock";
1181                 clocks = <&apll_pcie_ck>;
1182                 clock-mult = <1>;
1183                 clock-div = <1>;
1184         };
1185
1186         apll_pcie_m2_ck: apll_pcie_m2_ck {
1187                 #clock-cells = <0>;
1188                 compatible = "fixed-factor-clock";
1189                 clocks = <&apll_pcie_ck>;
1190                 clock-mult = <1>;
1191                 clock-div = <1>;
1192         };
1193
1194         dpll_per_byp_mux: dpll_per_byp_mux@14c {
1195                 #clock-cells = <0>;
1196                 compatible = "ti,mux-clock";
1197                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1198                 ti,bit-shift = <23>;
1199                 reg = <0x014c>;
1200         };
1201
1202         dpll_per_ck: dpll_per_ck@140 {
1203                 #clock-cells = <0>;
1204                 compatible = "ti,omap4-dpll-clock";
1205                 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1206                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1207         };
1208
1209         dpll_per_m2_ck: dpll_per_m2_ck@150 {
1210                 #clock-cells = <0>;
1211                 compatible = "ti,divider-clock";
1212                 clocks = <&dpll_per_ck>;
1213                 ti,max-div = <31>;
1214                 ti,autoidle-shift = <8>;
1215                 reg = <0x0150>;
1216                 ti,index-starts-at-one;
1217                 ti,invert-autoidle-bit;
1218         };
1219
1220         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1221                 #clock-cells = <0>;
1222                 compatible = "fixed-factor-clock";
1223                 clocks = <&dpll_per_m2_ck>;
1224                 clock-mult = <1>;
1225                 clock-div = <1>;
1226         };
1227
1228         dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1229                 #clock-cells = <0>;
1230                 compatible = "ti,mux-clock";
1231                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1232                 ti,bit-shift = <23>;
1233                 reg = <0x018c>;
1234         };
1235
1236         dpll_usb_ck: dpll_usb_ck@180 {
1237                 #clock-cells = <0>;
1238                 compatible = "ti,omap4-dpll-j-type-clock";
1239                 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1240                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1241         };
1242
1243         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1244                 #clock-cells = <0>;
1245                 compatible = "ti,divider-clock";
1246                 clocks = <&dpll_usb_ck>;
1247                 ti,max-div = <127>;
1248                 ti,autoidle-shift = <8>;
1249                 reg = <0x0190>;
1250                 ti,index-starts-at-one;
1251                 ti,invert-autoidle-bit;
1252         };
1253
1254         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1255                 #clock-cells = <0>;
1256                 compatible = "ti,divider-clock";
1257                 clocks = <&dpll_pcie_ref_ck>;
1258                 ti,max-div = <127>;
1259                 ti,autoidle-shift = <8>;
1260                 reg = <0x0210>;
1261                 ti,index-starts-at-one;
1262                 ti,invert-autoidle-bit;
1263         };
1264
1265         dpll_per_x2_ck: dpll_per_x2_ck {
1266                 #clock-cells = <0>;
1267                 compatible = "ti,omap4-dpll-x2-clock";
1268                 clocks = <&dpll_per_ck>;
1269         };
1270
1271         dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1272                 #clock-cells = <0>;
1273                 compatible = "ti,divider-clock";
1274                 clocks = <&dpll_per_x2_ck>;
1275                 ti,max-div = <63>;
1276                 ti,autoidle-shift = <8>;
1277                 reg = <0x0158>;
1278                 ti,index-starts-at-one;
1279                 ti,invert-autoidle-bit;
1280         };
1281
1282         dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1283                 #clock-cells = <0>;
1284                 compatible = "ti,divider-clock";
1285                 clocks = <&dpll_per_x2_ck>;
1286                 ti,max-div = <63>;
1287                 ti,autoidle-shift = <8>;
1288                 reg = <0x015c>;
1289                 ti,index-starts-at-one;
1290                 ti,invert-autoidle-bit;
1291         };
1292
1293         dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1294                 #clock-cells = <0>;
1295                 compatible = "ti,divider-clock";
1296                 clocks = <&dpll_per_x2_ck>;
1297                 ti,max-div = <63>;
1298                 ti,autoidle-shift = <8>;
1299                 reg = <0x0160>;
1300                 ti,index-starts-at-one;
1301                 ti,invert-autoidle-bit;
1302         };
1303
1304         dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1305                 #clock-cells = <0>;
1306                 compatible = "ti,divider-clock";
1307                 clocks = <&dpll_per_x2_ck>;
1308                 ti,max-div = <63>;
1309                 ti,autoidle-shift = <8>;
1310                 reg = <0x0164>;
1311                 ti,index-starts-at-one;
1312                 ti,invert-autoidle-bit;
1313         };
1314
1315         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1316                 #clock-cells = <0>;
1317                 compatible = "ti,divider-clock";
1318                 clocks = <&dpll_per_x2_ck>;
1319                 ti,max-div = <31>;
1320                 ti,autoidle-shift = <8>;
1321                 reg = <0x0150>;
1322                 ti,index-starts-at-one;
1323                 ti,invert-autoidle-bit;
1324         };
1325
1326         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1327                 #clock-cells = <0>;
1328                 compatible = "fixed-factor-clock";
1329                 clocks = <&dpll_usb_ck>;
1330                 clock-mult = <1>;
1331                 clock-div = <1>;
1332         };
1333
1334         func_128m_clk: func_128m_clk {
1335                 #clock-cells = <0>;
1336                 compatible = "fixed-factor-clock";
1337                 clocks = <&dpll_per_h11x2_ck>;
1338                 clock-mult = <1>;
1339                 clock-div = <2>;
1340         };
1341
1342         func_12m_fclk: func_12m_fclk {
1343                 #clock-cells = <0>;
1344                 compatible = "fixed-factor-clock";
1345                 clocks = <&dpll_per_m2x2_ck>;
1346                 clock-mult = <1>;
1347                 clock-div = <16>;
1348         };
1349
1350         func_24m_clk: func_24m_clk {
1351                 #clock-cells = <0>;
1352                 compatible = "fixed-factor-clock";
1353                 clocks = <&dpll_per_m2_ck>;
1354                 clock-mult = <1>;
1355                 clock-div = <4>;
1356         };
1357
1358         func_48m_fclk: func_48m_fclk {
1359                 #clock-cells = <0>;
1360                 compatible = "fixed-factor-clock";
1361                 clocks = <&dpll_per_m2x2_ck>;
1362                 clock-mult = <1>;
1363                 clock-div = <4>;
1364         };
1365
1366         func_96m_fclk: func_96m_fclk {
1367                 #clock-cells = <0>;
1368                 compatible = "fixed-factor-clock";
1369                 clocks = <&dpll_per_m2x2_ck>;
1370                 clock-mult = <1>;
1371                 clock-div = <2>;
1372         };
1373
1374         l3init_60m_fclk: l3init_60m_fclk@104 {
1375                 #clock-cells = <0>;
1376                 compatible = "ti,divider-clock";
1377                 clocks = <&dpll_usb_m2_ck>;
1378                 reg = <0x0104>;
1379                 ti,dividers = <1>, <8>;
1380         };
1381
1382         clkout2_clk: clkout2_clk@6b0 {
1383                 #clock-cells = <0>;
1384                 compatible = "ti,gate-clock";
1385                 clocks = <&clkoutmux2_clk_mux>;
1386                 ti,bit-shift = <8>;
1387                 reg = <0x06b0>;
1388         };
1389
1390         l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1391                 #clock-cells = <0>;
1392                 compatible = "ti,gate-clock";
1393                 clocks = <&dpll_usb_clkdcoldo>;
1394                 ti,bit-shift = <8>;
1395                 reg = <0x06c0>;
1396         };
1397
1398         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1399                 #clock-cells = <0>;
1400                 compatible = "ti,gate-clock";
1401                 clocks = <&sys_32k_ck>;
1402                 ti,bit-shift = <8>;
1403                 reg = <0x0640>;
1404         };
1405
1406         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1407                 #clock-cells = <0>;
1408                 compatible = "ti,gate-clock";
1409                 clocks = <&sys_32k_ck>;
1410                 ti,bit-shift = <8>;
1411                 reg = <0x0688>;
1412         };
1413
1414         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1415                 #clock-cells = <0>;
1416                 compatible = "ti,gate-clock";
1417                 clocks = <&sys_32k_ck>;
1418                 ti,bit-shift = <8>;
1419                 reg = <0x0698>;
1420         };
1421
1422         gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1423                 #clock-cells = <0>;
1424                 compatible = "ti,mux-clock";
1425                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1426                 ti,bit-shift = <24>;
1427                 reg = <0x1220>;
1428                 assigned-clocks = <&gpu_core_gclk_mux>;
1429                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1430         };
1431
1432         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1433                 #clock-cells = <0>;
1434                 compatible = "ti,mux-clock";
1435                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1436                 ti,bit-shift = <26>;
1437                 reg = <0x1220>;
1438                 assigned-clocks = <&gpu_hyd_gclk_mux>;
1439                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1440         };
1441
1442         l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1443                 #clock-cells = <0>;
1444                 compatible = "ti,divider-clock";
1445                 clocks = <&wkupaon_iclk_mux>;
1446                 ti,bit-shift = <24>;
1447                 reg = <0x0e50>;
1448                 ti,dividers = <8>, <16>, <32>;
1449         };
1450
1451         vip1_gclk_mux: vip1_gclk_mux@1020 {
1452                 #clock-cells = <0>;
1453                 compatible = "ti,mux-clock";
1454                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1455                 ti,bit-shift = <24>;
1456                 reg = <0x1020>;
1457         };
1458
1459         vip2_gclk_mux: vip2_gclk_mux@1028 {
1460                 #clock-cells = <0>;
1461                 compatible = "ti,mux-clock";
1462                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1463                 ti,bit-shift = <24>;
1464                 reg = <0x1028>;
1465         };
1466
1467         vip3_gclk_mux: vip3_gclk_mux@1030 {
1468                 #clock-cells = <0>;
1469                 compatible = "ti,mux-clock";
1470                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1471                 ti,bit-shift = <24>;
1472                 reg = <0x1030>;
1473         };
1474 };
1475
1476 &cm_core_clockdomains {
1477         coreaon_clkdm: coreaon_clkdm {
1478                 compatible = "ti,clockdomain";
1479                 clocks = <&dpll_usb_ck>;
1480         };
1481 };
1482
1483 &scm_conf_clocks {
1484         dss_deshdcp_clk: dss_deshdcp_clk@558 {
1485                 #clock-cells = <0>;
1486                 compatible = "ti,gate-clock";
1487                 clocks = <&l3_iclk_div>;
1488                 ti,bit-shift = <0>;
1489                 reg = <0x558>;
1490         };
1491
1492        ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
1493                 #clock-cells = <0>;
1494                 compatible = "ti,gate-clock";
1495                 clocks = <&l4_root_clk_div>;
1496                 ti,bit-shift = <20>;
1497                 reg = <0x0558>;
1498         };
1499
1500         ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
1501                 #clock-cells = <0>;
1502                 compatible = "ti,gate-clock";
1503                 clocks = <&l4_root_clk_div>;
1504                 ti,bit-shift = <21>;
1505                 reg = <0x0558>;
1506         };
1507
1508         ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
1509                 #clock-cells = <0>;
1510                 compatible = "ti,gate-clock";
1511                 clocks = <&l4_root_clk_div>;
1512                 ti,bit-shift = <22>;
1513                 reg = <0x0558>;
1514         };
1515
1516         sys_32k_ck: sys_32k_ck {
1517                 #clock-cells = <0>;
1518                 compatible = "ti,mux-clock";
1519                 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
1520                 ti,bit-shift = <8>;
1521                 reg = <0x6c4>;
1522         };
1523 };
1524
1525 &cm_core_aon {
1526         mpu_cm: mpu-cm@300 {
1527                 compatible = "ti,omap4-cm";
1528                 reg = <0x300 0x100>;
1529                 #address-cells = <1>;
1530                 #size-cells = <1>;
1531                 ranges = <0 0x300 0x100>;
1532
1533                 mpu_clkctrl: mpu-clkctrl@20 {
1534                         compatible = "ti,clkctrl";
1535                         reg = <0x20 0x4>;
1536                         #clock-cells = <2>;
1537                 };
1538
1539         };
1540
1541         dsp1_cm: dsp1-cm@400 {
1542                 compatible = "ti,omap4-cm";
1543                 reg = <0x400 0x100>;
1544                 #address-cells = <1>;
1545                 #size-cells = <1>;
1546                 ranges = <0 0x400 0x100>;
1547
1548                 dsp1_clkctrl: dsp1-clkctrl@20 {
1549                         compatible = "ti,clkctrl";
1550                         reg = <0x20 0x4>;
1551                         #clock-cells = <2>;
1552                 };
1553
1554         };
1555
1556         ipu_cm: ipu-cm@500 {
1557                 compatible = "ti,omap4-cm";
1558                 reg = <0x500 0x100>;
1559                 #address-cells = <1>;
1560                 #size-cells = <1>;
1561                 ranges = <0 0x500 0x100>;
1562
1563                 ipu1_clkctrl: ipu1-clkctrl@20 {
1564                         compatible = "ti,clkctrl";
1565                         reg = <0x20 0x4>;
1566                         #clock-cells = <2>;
1567                 };
1568
1569                 ipu_clkctrl: ipu-clkctrl@50 {
1570                         compatible = "ti,clkctrl";
1571                         reg = <0x50 0x34>;
1572                         #clock-cells = <2>;
1573                 };
1574
1575         };
1576
1577         dsp2_cm: dsp2-cm@600 {
1578                 compatible = "ti,omap4-cm";
1579                 reg = <0x600 0x100>;
1580                 #address-cells = <1>;
1581                 #size-cells = <1>;
1582                 ranges = <0 0x600 0x100>;
1583
1584                 dsp2_clkctrl: dsp2-clkctrl@20 {
1585                         compatible = "ti,clkctrl";
1586                         reg = <0x20 0x4>;
1587                         #clock-cells = <2>;
1588                 };
1589
1590         };
1591
1592         rtc_cm: rtc-cm@700 {
1593                 compatible = "ti,omap4-cm";
1594                 reg = <0x700 0x60>;
1595                 #address-cells = <1>;
1596                 #size-cells = <1>;
1597                 ranges = <0 0x700 0x60>;
1598
1599                 rtc_clkctrl: rtc-clkctrl@20 {
1600                         compatible = "ti,clkctrl";
1601                         reg = <0x20 0x28>;
1602                         #clock-cells = <2>;
1603                 };
1604         };
1605
1606         vpe_cm: vpe-cm@760 {
1607                 compatible = "ti,omap4-cm";
1608                 reg = <0x760 0xc>;
1609                 #address-cells = <1>;
1610                 #size-cells = <1>;
1611                 ranges = <0 0x760 0xc>;
1612
1613                 vpe_clkctrl: vpe-clkctrl@0 {
1614                         compatible = "ti,clkctrl";
1615                         reg = <0x0 0xc>;
1616                         #clock-cells = <2>;
1617                 };
1618         };
1619
1620 };
1621
1622 &cm_core {
1623         coreaon_cm: coreaon-cm@600 {
1624                 compatible = "ti,omap4-cm";
1625                 reg = <0x600 0x100>;
1626                 #address-cells = <1>;
1627                 #size-cells = <1>;
1628                 ranges = <0 0x600 0x100>;
1629
1630                 coreaon_clkctrl: coreaon-clkctrl@20 {
1631                         compatible = "ti,clkctrl";
1632                         reg = <0x20 0x1c>;
1633                         #clock-cells = <2>;
1634                 };
1635         };
1636
1637         l3main1_cm: l3main1-cm@700 {
1638                 compatible = "ti,omap4-cm";
1639                 reg = <0x700 0x100>;
1640                 #address-cells = <1>;
1641                 #size-cells = <1>;
1642                 ranges = <0 0x700 0x100>;
1643
1644                 l3main1_clkctrl: l3main1-clkctrl@20 {
1645                         compatible = "ti,clkctrl";
1646                         reg = <0x20 0x74>;
1647                         #clock-cells = <2>;
1648                 };
1649
1650         };
1651
1652         ipu2_cm: ipu2-cm@900 {
1653                 compatible = "ti,omap4-cm";
1654                 reg = <0x900 0x100>;
1655                 #address-cells = <1>;
1656                 #size-cells = <1>;
1657                 ranges = <0 0x900 0x100>;
1658
1659                 ipu2_clkctrl: ipu2-clkctrl@20 {
1660                         compatible = "ti,clkctrl";
1661                         reg = <0x20 0x4>;
1662                         #clock-cells = <2>;
1663                 };
1664
1665         };
1666
1667         dma_cm: dma-cm@a00 {
1668                 compatible = "ti,omap4-cm";
1669                 reg = <0xa00 0x100>;
1670                 #address-cells = <1>;
1671                 #size-cells = <1>;
1672                 ranges = <0 0xa00 0x100>;
1673
1674                 dma_clkctrl: dma-clkctrl@20 {
1675                         compatible = "ti,clkctrl";
1676                         reg = <0x20 0x4>;
1677                         #clock-cells = <2>;
1678                 };
1679         };
1680
1681         emif_cm: emif-cm@b00 {
1682                 compatible = "ti,omap4-cm";
1683                 reg = <0xb00 0x100>;
1684                 #address-cells = <1>;
1685                 #size-cells = <1>;
1686                 ranges = <0 0xb00 0x100>;
1687
1688                 emif_clkctrl: emif-clkctrl@20 {
1689                         compatible = "ti,clkctrl";
1690                         reg = <0x20 0x4>;
1691                         #clock-cells = <2>;
1692                 };
1693         };
1694
1695         atl_cm: atl-cm@c00 {
1696                 compatible = "ti,omap4-cm";
1697                 reg = <0xc00 0x100>;
1698                 #address-cells = <1>;
1699                 #size-cells = <1>;
1700                 ranges = <0 0xc00 0x100>;
1701
1702                 atl_clkctrl: atl-clkctrl@0 {
1703                         compatible = "ti,clkctrl";
1704                         reg = <0x0 0x4>;
1705                         #clock-cells = <2>;
1706                 };
1707         };
1708
1709         l4cfg_cm: l4cfg-cm@d00 {
1710                 compatible = "ti,omap4-cm";
1711                 reg = <0xd00 0x100>;
1712                 #address-cells = <1>;
1713                 #size-cells = <1>;
1714                 ranges = <0 0xd00 0x100>;
1715
1716                 l4cfg_clkctrl: l4cfg-clkctrl@20 {
1717                         compatible = "ti,clkctrl";
1718                         reg = <0x20 0x84>;
1719                         #clock-cells = <2>;
1720                 };
1721         };
1722
1723         l3instr_cm: l3instr-cm@e00 {
1724                 compatible = "ti,omap4-cm";
1725                 reg = <0xe00 0x100>;
1726                 #address-cells = <1>;
1727                 #size-cells = <1>;
1728                 ranges = <0 0xe00 0x100>;
1729
1730                 l3instr_clkctrl: l3instr-clkctrl@20 {
1731                         compatible = "ti,clkctrl";
1732                         reg = <0x20 0xc>;
1733                         #clock-cells = <2>;
1734                 };
1735         };
1736
1737         cam_cm: cam-cm@1000 {
1738                 compatible = "ti,omap4-cm";
1739                 reg = <0x1000 0x100>;
1740                 #address-cells = <1>;
1741                 #size-cells = <1>;
1742                 ranges = <0 0x1000 0x100>;
1743
1744                 cam_clkctrl: cam-clkctrl@20 {
1745                         compatible = "ti,clkctrl";
1746                         reg = <0x20 0x2c>;
1747                         #clock-cells = <2>;
1748                 };
1749         };
1750
1751         dss_cm: dss-cm@1100 {
1752                 compatible = "ti,omap4-cm";
1753                 reg = <0x1100 0x100>;
1754                 #address-cells = <1>;
1755                 #size-cells = <1>;
1756                 ranges = <0 0x1100 0x100>;
1757
1758                 dss_clkctrl: dss-clkctrl@20 {
1759                         compatible = "ti,clkctrl";
1760                         reg = <0x20 0x14>;
1761                         #clock-cells = <2>;
1762                 };
1763         };
1764
1765         gpu_cm: gpu-cm@1200 {
1766                 compatible = "ti,omap4-cm";
1767                 reg = <0x1200 0x100>;
1768                 #address-cells = <1>;
1769                 #size-cells = <1>;
1770                 ranges = <0 0x1200 0x100>;
1771
1772                 gpu_clkctrl: gpu-clkctrl@20 {
1773                         compatible = "ti,clkctrl";
1774                         reg = <0x20 0x4>;
1775                         #clock-cells = <2>;
1776                 };
1777         };
1778
1779         l3init_cm: l3init-cm@1300 {
1780                 compatible = "ti,omap4-cm";
1781                 reg = <0x1300 0x100>;
1782                 #address-cells = <1>;
1783                 #size-cells = <1>;
1784                 ranges = <0 0x1300 0x100>;
1785
1786                 l3init_clkctrl: l3init-clkctrl@20 {
1787                         compatible = "ti,clkctrl";
1788                         reg = <0x20 0x6c>, <0xe0 0x14>;
1789                         #clock-cells = <2>;
1790                 };
1791
1792                 pcie_clkctrl: pcie-clkctrl@b0 {
1793                         compatible = "ti,clkctrl";
1794                         reg = <0xb0 0xc>;
1795                         #clock-cells = <2>;
1796                 };
1797
1798                 gmac_clkctrl: gmac-clkctrl@d0 {
1799                         compatible = "ti,clkctrl";
1800                         reg = <0xd0 0x4>;
1801                         #clock-cells = <2>;
1802                 };
1803
1804         };
1805
1806         l4per_cm: l4per-cm@1700 {
1807                 compatible = "ti,omap4-cm";
1808                 reg = <0x1700 0x300>;
1809                 #address-cells = <1>;
1810                 #size-cells = <1>;
1811                 ranges = <0 0x1700 0x300>;
1812
1813                 l4per_clkctrl: l4per-clkctrl@28 {
1814                         compatible = "ti,clkctrl";
1815                         reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
1816                         #clock-cells = <2>;
1817
1818                         assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
1819                         assigned-clock-parents = <&abe_24m_fclk>;
1820                 };
1821
1822                 l4sec_clkctrl: l4sec-clkctrl@1a0 {
1823                         compatible = "ti,clkctrl";
1824                         reg = <0x1a0 0x2c>;
1825                         #clock-cells = <2>;
1826                 };
1827
1828                 l4per2_clkctrl: l4per2-clkctrl@c {
1829                         compatible = "ti,clkctrl";
1830                         reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
1831                         #clock-cells = <2>;
1832                 };
1833
1834                 l4per3_clkctrl: l4per3-clkctrl@14 {
1835                         compatible = "ti,clkctrl";
1836                         reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
1837                         #clock-cells = <2>;
1838                 };
1839         };
1840
1841 };
1842
1843 &prm {
1844         wkupaon_cm: wkupaon-cm@1800 {
1845                 compatible = "ti,omap4-cm";
1846                 reg = <0x1800 0x100>;
1847                 #address-cells = <1>;
1848                 #size-cells = <1>;
1849                 ranges = <0 0x1800 0x100>;
1850
1851                 wkupaon_clkctrl: wkupaon-clkctrl@20 {
1852                         compatible = "ti,clkctrl";
1853                         reg = <0x20 0x6c>;
1854                         #clock-cells = <2>;
1855                 };
1856         };
1857 };