1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include "dra7-evm-common.dtsi"
9 #include "dra76x-mmc-iodelay.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 model = "TI DRA762 EVM";
14 compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
24 device_type = "memory";
25 reg = <0x0 0x80000000 0x0 0x80000000>;
33 ipu2_cma_pool: ipu2_cma@95800000 {
34 compatible = "shared-dma-pool";
35 reg = <0x0 0x95800000 0x0 0x3800000>;
40 dsp1_cma_pool: dsp1_cma@99000000 {
41 compatible = "shared-dma-pool";
42 reg = <0x0 0x99000000 0x0 0x4000000>;
47 ipu1_cma_pool: ipu1_cma@9d000000 {
48 compatible = "shared-dma-pool";
49 reg = <0x0 0x9d000000 0x0 0x2000000>;
54 dsp2_cma_pool: dsp2_cma@9f000000 {
55 compatible = "shared-dma-pool";
56 reg = <0x0 0x9f000000 0x0 0x800000>;
62 vsys_12v0: fixedregulator-vsys12v0 {
64 compatible = "regulator-fixed";
65 regulator-name = "vsys_12v0";
66 regulator-min-microvolt = <12000000>;
67 regulator-max-microvolt = <12000000>;
72 vsys_5v0: fixedregulator-vsys5v0 {
73 /* Output of Cntlr B of TPS43351-Q1 on dra76-evm */
74 compatible = "regulator-fixed";
75 regulator-name = "vsys_5v0";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
78 vin-supply = <&vsys_12v0>;
83 vio_3v6: fixedregulator-vio_3v6 {
84 compatible = "regulator-fixed";
85 regulator-name = "vio_3v6";
86 regulator-min-microvolt = <3600000>;
87 regulator-max-microvolt = <3600000>;
88 vin-supply = <&vsys_5v0>;
93 vsys_3v3: fixedregulator-vsys3v3 {
94 /* Output of Cntlr A of TPS43351-Q1 on dra76-evm */
95 compatible = "regulator-fixed";
96 regulator-name = "vsys_3v3";
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 vin-supply = <&vsys_12v0>;
104 vio_3v3: fixedregulator-vio_3v3 {
105 compatible = "regulator-fixed";
106 regulator-name = "vio_3v3";
107 regulator-min-microvolt = <3300000>;
108 regulator-max-microvolt = <3300000>;
109 vin-supply = <&vsys_3v3>;
114 vio_3v3_sd: fixedregulator-sd {
115 compatible = "regulator-fixed";
116 regulator-name = "vio_3v3_sd";
117 regulator-min-microvolt = <3300000>;
118 regulator-max-microvolt = <3300000>;
119 vin-supply = <&vio_3v3>;
121 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
124 vio_1v8: fixedregulator-vio_1v8 {
125 compatible = "regulator-fixed";
126 regulator-name = "vio_1v8";
127 regulator-min-microvolt = <1800000>;
128 regulator-max-microvolt = <1800000>;
129 vin-supply = <&smps5_reg>;
132 vmmcwl_fixed: fixedregulator-mmcwl {
133 compatible = "regulator-fixed";
134 regulator-name = "vmmcwl_fixed";
135 regulator-min-microvolt = <1800000>;
136 regulator-max-microvolt = <1800000>;
137 gpio = <&gpio5 8 0>; /* gpio5_8 */
138 startup-delay-us = <70000>;
142 vtt_fixed: fixedregulator-vtt {
143 compatible = "regulator-fixed";
144 regulator-name = "vtt_fixed";
145 regulator-min-microvolt = <1350000>;
146 regulator-max-microvolt = <1350000>;
147 vin-supply = <&vsys_3v3>;
152 aic_dvdd: fixedregulator-aic_dvdd {
154 compatible = "regulator-fixed";
155 regulator-name = "aic_dvdd";
156 vin-supply = <&vio_3v3>;
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <1800000>;
162 compatible = "hdmi-connector";
168 hdmi_connector_in: endpoint {
169 remote-endpoint = <&tpd12s015_out>;
175 compatible = "ti,tpd12s015";
177 gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
178 <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
179 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
182 #address-cells = <1>;
188 tpd12s015_in: endpoint {
189 remote-endpoint = <&hdmi_out>;
196 tpd12s015_out: endpoint {
197 remote-endpoint = <&hdmi_connector_in>;
206 clock-frequency = <400000>;
208 tps65917: tps65917@58 {
209 compatible = "ti,tps65917";
211 ti,system-power-controller;
212 ti,palmas-override-powerhold;
213 interrupt-controller;
214 #interrupt-cells = <2>;
217 compatible = "ti,tps65917-pmic";
219 smps12-in-supply = <&vsys_3v3>;
220 smps3-in-supply = <&vsys_3v3>;
221 smps4-in-supply = <&vsys_3v3>;
222 smps5-in-supply = <&vsys_3v3>;
223 ldo1-in-supply = <&vsys_3v3>;
224 ldo2-in-supply = <&vsys_3v3>;
225 ldo3-in-supply = <&vsys_5v0>;
226 ldo4-in-supply = <&vsys_5v0>;
227 ldo5-in-supply = <&vsys_3v3>;
229 tps65917_regulators: regulators {
232 regulator-name = "smps12";
233 regulator-min-microvolt = <850000>;
234 regulator-max-microvolt = <1250000>;
241 regulator-name = "smps3";
242 regulator-min-microvolt = <850000>;
243 regulator-max-microvolt = <1250000>;
250 regulator-name = "smps4";
251 regulator-min-microvolt = <850000>;
252 regulator-max-microvolt = <1250000>;
259 regulator-name = "smps5";
260 regulator-min-microvolt = <1800000>;
261 regulator-max-microvolt = <1800000>;
267 /* LDO1_OUT --> VDA_PHY1_1V8 */
268 regulator-name = "ldo1";
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <1800000>;
273 regulator-allow-bypass;
277 /* LDO2_OUT --> VDA_PHY2_1V8 */
278 regulator-name = "ldo2";
279 regulator-min-microvolt = <1800000>;
280 regulator-max-microvolt = <1800000>;
281 regulator-allow-bypass;
287 regulator-name = "ldo3";
288 regulator-min-microvolt = <3300000>;
289 regulator-max-microvolt = <3300000>;
296 regulator-name = "ldo5";
297 regulator-min-microvolt = <1800000>;
298 regulator-max-microvolt = <1800000>;
305 regulator-name = "ldo4";
306 regulator-min-microvolt = <1800000>;
307 regulator-max-microvolt = <3300000>;
314 tps65917_power_button {
315 compatible = "ti,palmas-pwrbutton";
316 interrupt-parent = <&tps65917>;
317 interrupts = <1 IRQ_TYPE_NONE>;
319 ti,palmas-long-press-seconds = <6>;
323 lp87565: lp87565@60 {
324 compatible = "ti,lp87565-q1";
327 buck10-in-supply =<&vsys_3v3>;
328 buck23-in-supply =<&vsys_3v3>;
330 regulators: regulators {
333 regulator-name = "buck10";
334 regulator-min-microvolt = <850000>;
335 regulator-max-microvolt = <1250000>;
342 regulator-name = "buck23";
343 regulator-min-microvolt = <850000>;
344 regulator-max-microvolt = <1250000>;
351 pcf_lcd: pcf8757@20 {
352 compatible = "nxp,pcf8575";
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 interrupt-parent = <&gpio1>;
359 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
362 pcf_gpio_21: pcf8757@21 {
363 compatible = "nxp,pcf8575";
367 interrupt-parent = <&gpio1>;
368 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
373 pcf_hdmi: pcf8575@26 {
374 compatible = "nxp,pcf8575";
379 /* vin6_sel_s0: high: VIN6, low: audio */
381 gpios = <1 GPIO_ACTIVE_HIGH>;
383 line-name = "vin6_sel_s0";
387 tlv320aic3106: tlv320aic3106@19 {
388 #sound-dai-cells = <0>;
389 compatible = "ti,tlv320aic3106";
391 adc-settle-ms = <40>;
392 ai3x-micbias-vg = <1>; /* 2.0V */
396 AVDD-supply = <&vio_3v3>;
397 IOVDD-supply = <&vio_3v3>;
398 DRVDD-supply = <&vio_3v3>;
399 DVDD-supply = <&aic_dvdd>;
404 vdd-supply = <&buck10_reg>;
409 vmmc-supply = <&vio_3v3_sd>;
410 vqmmc-supply = <&ldo4_reg>;
413 * SDCD signal is not being used here - using the fact that GPIO mode
414 * is always hardwired.
416 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
417 pinctrl-names = "default", "hs";
418 pinctrl-0 = <&mmc1_pins_default>;
419 pinctrl-1 = <&mmc1_pins_hs>;
424 vmmc-supply = <&vio_1v8>;
425 vqmmc-supply = <&vio_1v8>;
428 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
429 pinctrl-0 = <&mmc2_pins_default>;
430 pinctrl-1 = <&mmc2_pins_default>;
431 pinctrl-2 = <&mmc2_pins_default>;
432 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
437 vmmc-supply = <&vio_3v6>;
438 vqmmc-supply = <&vmmcwl_fixed>;
439 pinctrl-names = "default", "hs", "sdr12", "sdr25";
440 pinctrl-0 = <&mmc4_pins_hs &mmc4_iodelay_default_conf>;
441 pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
442 pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
443 pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
446 /* No RTC on this device */
456 phy-handle = <&dp83867_0>;
457 phy-mode = "rgmii-id";
458 ti,dual-emac-pvid = <1>;
462 phy-handle = <&dp83867_1>;
463 phy-mode = "rgmii-id";
464 ti,dual-emac-pvid = <2>;
468 dp83867_0: ethernet-phy@2 {
470 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
471 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
472 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
473 ti,min-output-impedance;
474 ti,dp83867-rxctrl-strap-quirk;
477 dp83867_1: ethernet-phy@3 {
479 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
480 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
481 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
482 ti,min-output-impedance;
483 ti,dp83867-rxctrl-strap-quirk;
488 phy-supply = <&ldo3_reg>;
492 phy-supply = <&ldo3_reg>;
497 vdda_video-supply = <&ldo5_reg>;
503 vdda-supply = <&ldo1_reg>;
507 remote-endpoint = <&tpd12s015_in>;
513 spi-max-frequency = <96000000>;
515 spi-max-frequency = <96000000>;
525 phys = <&pcie1_phy>, <&pcie2_phy>;
526 phy-names = "pcie-phy0", "pcie-phy1";
531 phys = <&pcie1_phy>, <&pcie2_phy>;
532 phy-names = "pcie-phy0", "pcie-phy1";
536 vbus-gpio = <&pcf_lcd 14 GPIO_ACTIVE_HIGH>;
540 vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>;
545 max-bitrate = <5000000>;
551 memory-region = <&ipu2_cma_pool>;
556 memory-region = <&ipu1_cma_pool>;
561 memory-region = <&dsp1_cma_pool>;
566 memory-region = <&dsp2_cma_pool>;