1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
5 * Based on "omap4.dtsi"
11 compatible = "ti,dra742", "ti,dra74", "ti,dra7";
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
20 clocks = <&dpll_mpu_ck>;
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
42 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
47 dsp2_system: dsp_system@41500000 {
48 compatible = "syscon";
49 reg = <0x41500000 0x100>;
52 omap_dwc3_4: omap_dwc3_4@48940000 {
53 compatible = "ti,dwc3";
54 ti,hwmods = "usb_otg_ss4";
55 reg = <0x48940000 0x10000>;
56 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
63 compatible = "snps,dwc3";
64 reg = <0x48950000 0x17000>;
65 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
68 interrupt-names = "peripheral",
71 maximum-speed = "high-speed";
76 target-module@41501000 {
77 compatible = "ti,sysc-omap2", "ti,sysc";
78 reg = <0x41501000 0x4>,
81 reg-names = "rev", "sysc", "syss";
82 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
85 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
86 SYSC_OMAP2_SOFTRESET |
87 SYSC_OMAP2_AUTOIDLE)>;
88 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
90 resets = <&prm_dsp2 1>;
91 reset-names = "rstctrl";
92 ranges = <0x0 0x41501000 0x1000>;
97 compatible = "ti,dra7-dsp-iommu";
99 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
101 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
105 target-module@41502000 {
106 compatible = "ti,sysc-omap2", "ti,sysc";
107 reg = <0x41502000 0x4>,
110 reg-names = "rev", "sysc", "syss";
111 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
114 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
115 SYSC_OMAP2_SOFTRESET |
116 SYSC_OMAP2_AUTOIDLE)>;
118 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
120 resets = <&prm_dsp2 1>;
121 reset-names = "rstctrl";
122 ranges = <0x0 0x41502000 0x1000>;
124 #address-cells = <1>;
127 compatible = "ti,dra7-dsp-iommu";
129 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
131 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
136 compatible = "ti,dra7-dsp";
137 reg = <0x41000000 0x48000>,
140 reg-names = "l2ram", "l1pram", "l1dram";
141 ti,bootreg = <&scm_conf 0x560 10>;
142 iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
144 resets = <&prm_dsp2 0>;
145 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
146 firmware-name = "dra7-dsp2-fw.xe66";
161 reg-names = "dss", "pll1_clkctrl", "pll1",
162 "pll2_clkctrl", "pll2";
164 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
165 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
166 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
167 clock-names = "fck", "video1_clk", "video2_clk";
171 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
172 ti,mbox-tx = <6 2 2>;
173 ti,mbox-rx = <4 2 2>;
176 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
177 ti,mbox-tx = <5 2 2>;
178 ti,mbox-rx = <1 2 2>;
184 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
185 ti,mbox-tx = <6 2 2>;
186 ti,mbox-rx = <4 2 2>;
189 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
190 ti,mbox-tx = <5 2 2>;
191 ti,mbox-rx = <1 2 2>;
197 compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
201 compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
205 compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";