1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
5 * Based on "omap4.dtsi"
11 compatible = "ti,dra742", "ti,dra74", "ti,dra7";
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
20 clocks = <&dpll_mpu_ck>;
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
42 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
47 dsp2_system: dsp_system@41500000 {
48 compatible = "syscon";
49 reg = <0x41500000 0x100>;
53 target-module@41501000 {
54 compatible = "ti,sysc-omap2", "ti,sysc";
55 reg = <0x41501000 0x4>,
58 reg-names = "rev", "sysc", "syss";
59 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
62 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
63 SYSC_OMAP2_SOFTRESET |
64 SYSC_OMAP2_AUTOIDLE)>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
67 resets = <&prm_dsp2 1>;
68 reset-names = "rstctrl";
69 ranges = <0x0 0x41501000 0x1000>;
74 compatible = "ti,dra7-dsp-iommu";
76 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
82 target-module@41502000 {
83 compatible = "ti,sysc-omap2", "ti,sysc";
84 reg = <0x41502000 0x4>,
87 reg-names = "rev", "sysc", "syss";
88 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
91 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
92 SYSC_OMAP2_SOFTRESET |
93 SYSC_OMAP2_AUTOIDLE)>;
95 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
97 resets = <&prm_dsp2 1>;
98 reset-names = "rstctrl";
99 ranges = <0x0 0x41502000 0x1000>;
101 #address-cells = <1>;
104 compatible = "ti,dra7-dsp-iommu";
106 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
108 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
113 compatible = "ti,dra7-dsp";
114 reg = <0x41000000 0x48000>,
117 reg-names = "l2ram", "l1pram", "l1dram";
118 ti,bootreg = <&scm_conf 0x560 10>;
119 iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
121 resets = <&prm_dsp2 0>;
122 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
123 firmware-name = "dra7-dsp2-fw.xe66";
138 reg-names = "dss", "pll1_clkctrl", "pll1",
139 "pll2_clkctrl", "pll2";
141 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
142 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
143 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
144 clock-names = "fck", "video1_clk", "video2_clk";
148 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
149 ti,mbox-tx = <6 2 2>;
150 ti,mbox-rx = <4 2 2>;
153 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
154 ti,mbox-tx = <5 2 2>;
155 ti,mbox-rx = <1 2 2>;
161 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
162 ti,mbox-tx = <6 2 2>;
163 ti,mbox-rx = <4 2 2>;
166 mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
167 ti,mbox-tx = <5 2 2>;
168 ti,mbox-rx = <1 2 2>;
174 compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
178 compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
182 compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
187 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
188 compatible = "ti,sysc-omap4", "ti,sysc";
189 reg = <0x140000 0x4>,
191 reg-names = "rev", "sysc";
192 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
193 ti,sysc-midle = <SYSC_IDLE_FORCE>,
196 <SYSC_IDLE_SMART_WKUP>;
197 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
200 <SYSC_IDLE_SMART_WKUP>;
201 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
202 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
204 #address-cells = <1>;
206 ranges = <0x0 0x140000 0x20000>;
208 omap_dwc3_4: omap_dwc3_4@0 {
209 compatible = "ti,dwc3";
211 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
212 #address-cells = <1>;
218 compatible = "snps,dwc3";
219 reg = <0x10000 0x17000>;
220 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "peripheral",
226 maximum-speed = "high-speed";