arch/arm/boot/dts/dra74x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on "omap4.dtsi"
   6  */
   7
   8 #include "dra7.dtsi"
   9
  10 / {
  11         compatible = "ti,dra742", "ti,dra74", "ti,dra7";
  12
  13         cpus {
  14                 cpu@1 {
  15                         device_type = "cpu";
  16                         compatible = "arm,cortex-a15";
  17                         reg = <1>;
  18                         operating-points-v2 = <&cpu0_opp_table>;
  19
  20                         clocks = <&dpll_mpu_ck>;
  21                         clock-names = "cpu";
  22
  23                         clock-latency = <300000>; /* From omap-cpufreq driver */
  24
  25                         /* cooling options */
  26                         #cooling-cells = <2>; /* min followed by max */
  27
  28                         vbb-supply = <&abb_mpu>;
  29                 };
  30         };
  31
  32         pmu {
  33                 compatible = "arm,cortex-a15-pmu";
  34                 interrupt-parent = <&wakeupgen>;
  35                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  36                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  37         };
  38
  39         ocp {
  40                 dsp2_system: dsp_system@41500000 {
  41                         compatible = "syscon";
  42                         reg = <0x41500000 0x100>;
  43                 };
  44
  45                 omap_dwc3_4: omap_dwc3_4@48940000 {
  46                         compatible = "ti,dwc3";
  47                         ti,hwmods = "usb_otg_ss4";
  48                         reg = <0x48940000 0x10000>;
  49                         interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  50                         #address-cells = <1>;
  51                         #size-cells = <1>;
  52                         utmi-mode = <2>;
  53                         ranges;
  54                         status = "disabled";
  55                         usb4: usb@48950000 {
  56                                 compatible = "snps,dwc3";
  57                                 reg = <0x48950000 0x17000>;
  58                                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  59                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  60                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
  61                                 interrupt-names = "peripheral",
  62                                                   "host",
  63                                                   "otg";
  64                                 maximum-speed = "high-speed";
  65                                 dr_mode = "otg";
  66                         };
  67                 };
  68
  69                 target-module@41501000 {
  70                         compatible = "ti,sysc-omap2", "ti,sysc";
  71                         reg = <0x41501000 0x4>,
  72                               <0x41501010 0x4>,
  73                               <0x41501014 0x4>;
  74                         reg-names = "rev", "sysc", "syss";
  75                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  76                                         <SYSC_IDLE_NO>,
  77                                         <SYSC_IDLE_SMART>;
  78                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  79                                          SYSC_OMAP2_SOFTRESET |
  80                                          SYSC_OMAP2_AUTOIDLE)>;
  81                         clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
  82                         clock-names = "fck";
  83                         resets = <&prm_dsp2 1>;
  84                         reset-names = "rstctrl";
  85                         ranges = <0x0 0x41501000 0x1000>;
  86                         #size-cells = <1>;
  87                         #address-cells = <1>;
  88
  89                         mmu0_dsp2: mmu@0 {
  90                                 compatible = "ti,dra7-dsp-iommu";
  91                                 reg = <0x0 0x100>;
  92                                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  93                                 #iommu-cells = <0>;
  94                                 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
  95                         };
  96                 };
  97
  98                 target-module@41502000 {
  99                         compatible = "ti,sysc-omap2", "ti,sysc";
 100                         reg = <0x41502000 0x4>,
 101                               <0x41502010 0x4>,
 102                               <0x41502014 0x4>;
 103                         reg-names = "rev", "sysc", "syss";
 104                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 105                                         <SYSC_IDLE_NO>,
 106                                         <SYSC_IDLE_SMART>;
 107                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 108                                          SYSC_OMAP2_SOFTRESET |
 109                                          SYSC_OMAP2_AUTOIDLE)>;
 110
 111                         clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
 112                         clock-names = "fck";
 113                         resets = <&prm_dsp2 1>;
 114                         reset-names = "rstctrl";
 115                         ranges = <0x0 0x41502000 0x1000>;
 116                         #size-cells = <1>;
 117                         #address-cells = <1>;
 118
 119                         mmu1_dsp2: mmu@0 {
 120                                 compatible = "ti,dra7-dsp-iommu";
 121                                 reg = <0x0 0x100>;
 122                                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 123                                 #iommu-cells = <0>;
 124                                 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
 125                         };
 126                 };
 127         };
 128 };
 129
 130 &cpu0_opp_table {
 131         opp-shared;
 132 };
 133
 134 &dss {
 135         reg = <0x58000000 0x80>,
 136               <0x58004054 0x4>,
 137               <0x58004300 0x20>,
 138               <0x58009054 0x4>,
 139               <0x58009300 0x20>;
 140         reg-names = "dss", "pll1_clkctrl", "pll1",
 141                     "pll2_clkctrl", "pll2";
 142
 143         clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
 144                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>,
 145                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 13>;
 146         clock-names = "fck", "video1_clk", "video2_clk";
 147 };
 148
 149 &mailbox5 {
 150         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 151                 ti,mbox-tx = <6 2 2>;
 152                 ti,mbox-rx = <4 2 2>;
 153                 status = "disabled";
 154         };
 155         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 156                 ti,mbox-tx = <5 2 2>;
 157                 ti,mbox-rx = <1 2 2>;
 158                 status = "disabled";
 159         };
 160 };
 161
 162 &mailbox6 {
 163         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 164                 ti,mbox-tx = <6 2 2>;
 165                 ti,mbox-rx = <4 2 2>;
 166                 status = "disabled";
 167         };
 168         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 169                 ti,mbox-tx = <5 2 2>;
 170                 ti,mbox-rx = <1 2 2>;
 171                 status = "disabled";
 172         };
 173 };
 174
 175 &pcie1_rc {
 176         compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
 177 };
 178
 179 &pcie1_ep {
 180         compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
 181 };
 182
 183 &pcie2_rc {
 184         compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
 185 };