arch/arm/boot/dts/dra72x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on "omap4.dtsi"
   6  */
   7
   8 #include "dra7.dtsi"
   9
  10 / {
  11         compatible = "ti,dra722", "ti,dra72", "ti,dra7";
  12
  13         pmu {
  14                 compatible = "arm,cortex-a15-pmu";
  15                 interrupt-parent = <&wakeupgen>;
  16                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
  17         };
  18 };
  19
  20 &l4_per2 {
  21         target-module@5b000 {                   /* 0x4845b000, ap 59 46.0 */
  22                 compatible = "ti,sysc-omap4", "ti,sysc";
  23                 reg = <0x5b000 0x4>,
  24                       <0x5b010 0x4>;
  25                 reg-names = "rev", "sysc";
  26                 ti,sysc-midle = <SYSC_IDLE_FORCE>,
  27                                 <SYSC_IDLE_NO>;
  28                 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
  29                                 <SYSC_IDLE_NO>;
  30                 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
  31                 clock-names = "fck";
  32                 #address-cells = <1>;
  33                 #size-cells = <1>;
  34                 ranges = <0x0 0x5b000 0x1000>;
  35
  36                 cal: cal@0 {
  37                         compatible = "ti,dra72-cal";
  38                         reg = <0x0000 0x400>,
  39                               <0x0800 0x40>,
  40                               <0x0900 0x40>;
  41                         reg-names = "cal_top",
  42                                     "cal_rx_core0",
  43                                     "cal_rx_core1";
  44                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  45                         ti,camerrx-control = <&scm_conf 0xE94>;
  46
  47                         ports {
  48                                 #address-cells = <1>;
  49                                 #size-cells = <0>;
  50
  51                                 csi2_0: port@0 {
  52                                         reg = <0>;
  53                                 };
  54                                 csi2_1: port@1 {
  55                                         reg = <1>;
  56                                 };
  57                         };
  58                 };
  59         };
  60 };
  61
  62 &dss {
  63         reg = <0 0x80>,
  64               <0x4054 0x4>,
  65               <0x4300 0x20>;
  66         reg-names = "dss", "pll1_clkctrl", "pll1";
  67
  68         clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
  69                  <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>;
  70         clock-names = "fck", "video1_clk";
  71 };
  72
  73 &mailbox5 {
  74         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
  75                 ti,mbox-tx = <6 2 2>;
  76                 ti,mbox-rx = <4 2 2>;
  77                 status = "disabled";
  78         };
  79         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
  80                 ti,mbox-tx = <5 2 2>;
  81                 ti,mbox-rx = <1 2 2>;
  82                 status = "disabled";
  83         };
  84 };
  85
  86 &mailbox6 {
  87         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
  88                 ti,mbox-tx = <6 2 2>;
  89                 ti,mbox-rx = <4 2 2>;
  90                 status = "disabled";
  91         };
  92 };
  93
  94 &pcie1_rc {
  95         compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
  96 };
  97
  98 &pcie1_ep {
  99         compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
 100 };
 101
 102 &pcie2_rc {
 103         compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
 104 };
 105
 106 &usb4_tm {
 107         status = "disabled";
 108 };