arch/arm/boot/dts/dra72-evm.dts

   1 /*
   2  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13
  14 / {
  15         model = "TI DRA722";
  16         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  17
  18         memory {
  19                 device_type = "memory";
  20                 reg = <0x80000000 0x40000000>; /* 1024 MB */
  21         };
  22
  23         aliases {
  24                 display0 = &hdmi0;
  25         };
  26
  27         evm_3v3: fixedregulator-evm_3v3 {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "evm_3v3";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32         };
  33
  34         aic_dvdd: fixedregulator-aic_dvdd {
  35                 /* TPS77018DBVT */
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "aic_dvdd";
  38                 vin-supply = <&evm_3v3>;
  39                 regulator-min-microvolt = <1800000>;
  40                 regulator-max-microvolt = <1800000>;
  41         };
  42
  43         evm_3v3_sd: fixedregulator-sd {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "evm_3v3_sd";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48                 enable-active-high;
  49                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  50         };
  51
  52         extcon_usb1: extcon_usb1 {
  53                 compatible = "linux,extcon-usb-gpio";
  54                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  55         };
  56
  57         extcon_usb2: extcon_usb2 {
  58                 compatible = "linux,extcon-usb-gpio";
  59                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  60         };
  61
  62         hdmi0: connector {
  63                 compatible = "hdmi-connector";
  64                 label = "hdmi";
  65
  66                 type = "a";
  67
  68                 port {
  69                         hdmi_connector_in: endpoint {
  70                                 remote-endpoint = <&tpd12s015_out>;
  71                         };
  72                 };
  73         };
  74
  75         tpd12s015: encoder {
  76                 compatible = "ti,tpd12s015";
  77
  78                 pinctrl-names = "default";
  79                 pinctrl-0 = <&tpd12s015_pins>;
  80
  81                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
  82                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
  83                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
  84
  85                 ports {
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88
  89                         port@0 {
  90                                 reg = <0>;
  91
  92                                 tpd12s015_in: endpoint {
  93                                         remote-endpoint = <&hdmi_out>;
  94                                 };
  95                         };
  96
  97                         port@1 {
  98                                 reg = <1>;
  99
 100                                 tpd12s015_out: endpoint {
 101                                         remote-endpoint = <&hdmi_connector_in>;
 102                                 };
 103                         };
 104                 };
 105         };
 106
 107         sound0: sound@0 {
 108                 compatible = "simple-audio-card";
 109                 simple-audio-card,name = "DRA7xx-EVM";
 110                 simple-audio-card,widgets =
 111                         "Headphone", "Headphone Jack",
 112                         "Line", "Line Out",
 113                         "Microphone", "Mic Jack",
 114                         "Line", "Line In";
 115                 simple-audio-card,routing =
 116                         "Headphone Jack",       "HPLOUT",
 117                         "Headphone Jack",       "HPROUT",
 118                         "Line Out",             "LLOUT",
 119                         "Line Out",             "RLOUT",
 120                         "MIC3L",                "Mic Jack",
 121                         "MIC3R",                "Mic Jack",
 122                         "Mic Jack",             "Mic Bias",
 123                         "LINE1L",               "Line In",
 124                         "LINE1R",               "Line In";
 125                 simple-audio-card,format = "dsp_b";
 126                 simple-audio-card,bitclock-master = <&sound0_master>;
 127                 simple-audio-card,frame-master = <&sound0_master>;
 128                 simple-audio-card,bitclock-inversion;
 129
 130                 sound0_master: simple-audio-card,cpu {
 131                         sound-dai = <&mcasp3>;
 132                         system-clock-frequency = <5644800>;
 133                 };
 134
 135                 simple-audio-card,codec {
 136                         sound-dai = <&tlv320aic3106>;
 137                         clocks = <&atl_clkin2_ck>;
 138                 };
 139         };
 140 };
 141
 142 &dra7_pmx_core {
 143         i2c1_pins: pinmux_i2c1_pins {
 144                 pinctrl-single,pins = <
 145                         DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
 146                         DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
 147                 >;
 148         };
 149
 150         i2c5_pins: pinmux_i2c5_pins {
 151                 pinctrl-single,pins = <
 152                         DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
 153                         DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
 154                 >;
 155         };
 156
 157         i2c5_pins: pinmux_i2c5_pins {
 158                 pinctrl-single,pins = <
 159                         DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
 160                         DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
 161                 >;
 162         };
 163
 164         nand_default: nand_default {
 165                 pinctrl-single,pins = <
 166                         DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT  | MUX_MODE0) /* gpmc_ad0 */
 167                         DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT  | MUX_MODE0) /* gpmc_ad1 */
 168                         DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT  | MUX_MODE0) /* gpmc_ad2 */
 169                         DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad3 */
 170                         DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT  | MUX_MODE0) /* gpmc_ad4 */
 171                         DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT  | MUX_MODE0) /* gpmc_ad5 */
 172                         DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT  | MUX_MODE0) /* gpmc_ad6 */
 173                         DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad7 */
 174                         DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT  | MUX_MODE0) /* gpmc_ad8 */
 175                         DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT  | MUX_MODE0) /* gpmc_ad9 */
 176                         DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT  | MUX_MODE0) /* gpmc_ad10 */
 177                         DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad11 */
 178                         DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT  | MUX_MODE0) /* gpmc_ad12 */
 179                         DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT  | MUX_MODE0) /* gpmc_ad13 */
 180                         DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT  | MUX_MODE0) /* gpmc_ad14 */
 181                         DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT  | MUX_MODE0) /* gpmc_ad15 */
 182                         DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
 183                         DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
 184                         DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
 185                         DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
 186                         DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
 187                         DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT  | MUX_MODE0) /* gpmc_wait0 */
 188                 >;
 189         };
 190
 191         usb1_pins: pinmux_usb1_pins {
 192                 pinctrl-single,pins = <
 193                         DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 194                 >;
 195         };
 196
 197         usb2_pins: pinmux_usb2_pins {
 198                 pinctrl-single,pins = <
 199                         DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 200                 >;
 201         };
 202
 203         tps65917_pins_default: tps65917_pins_default {
 204                 pinctrl-single,pins = <
 205                         DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
 206                 >;
 207         };
 208
 209         mmc1_pins_default: mmc1_pins_default {
 210                 pinctrl-single,pins = <
 211                         DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)       /* mmc1sdcd.gpio219 */
 212                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 213                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 214                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 215                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 216                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 217                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 218                 >;
 219         };
 220
 221         mmc2_pins_default: mmc2_pins_default {
 222                 pinctrl-single,pins = <
 223                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 224                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 225                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 226                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 227                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 228                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 229                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 230                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 231                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 232                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 233                 >;
 234         };
 235
 236         dcan1_pins_default: dcan1_pins_default {
 237                 pinctrl-single,pins = <
 238                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 239                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)  /* wakeup0.dcan1_rx */
 240                 >;
 241         };
 242
 243         dcan1_pins_sleep: dcan1_pins_sleep {
 244                 pinctrl-single,pins = <
 245                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 246                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 247                 >;
 248         };
 249
 250         qspi1_pins: pinmux_qspi1_pins {
 251                 pinctrl-single,pins = <
 252                         DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1)       /* gpmc_a13.qspi1_rtclk */
 253                         DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1)        /* gpmc_a14.qspi1_d3 */
 254                         DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1)        /* gpmc_a15.qspi1_d2 */
 255                         DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1)        /* gpmc_a16.qspi1_d1 */
 256                         DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1)        /* gpmc_a17.qspi1_d0 */
 257                         DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1)       /* qpmc_a18.qspi1_sclk */
 258                         DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1)       /* gpmc_cs2.qspi1_cs0 */
 259                 >;
 260         };
 261
 262         hdmi_pins: pinmux_hdmi_pins {
 263                 pinctrl-single,pins = <
 264                         DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
 265                         DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
 266                 >;
 267         };
 268
 269         tpd12s015_pins: pinmux_tpd12s015_pins {
 270                 pinctrl-single,pins = <
 271                         DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
 272                 >;
 273         };
 274
 275         atl_pins: pinmux_atl_pins {
 276                 pinctrl-single,pins = <
 277                         DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5)       /* xref_clk1.atl_clk1 */
 278                         DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5)       /* xref_clk2.atl_clk2 */
 279                 >;
 280         };
 281
 282         mcasp3_pins: pinmux_mcasp3_pins {
 283                 pinctrl-single,pins = <
 284                         DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_aclkx */
 285                         DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_fsx */
 286                         DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)      /* mcasp3_axr0 */
 287                         DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* mcasp3_axr1 */
 288                 >;
 289         };
 290
 291         mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
 292                 pinctrl-single,pins = <
 293                         DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
 294                         DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
 295                         DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
 296                         DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
 297                 >;
 298         };
 299 };
 300
 301 &i2c1 {
 302         status = "okay";
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&i2c1_pins>;
 305         clock-frequency = <400000>;
 306
 307         tps65917: tps65917@58 {
 308                 compatible = "ti,tps65917";
 309                 reg = <0x58>;
 310
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&tps65917_pins_default>;
 313
 314                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
 315                 interrupt-controller;
 316                 #interrupt-cells = <2>;
 317
 318                 ti,system-power-controller;
 319
 320                 tps65917_pmic {
 321                         compatible = "ti,tps65917-pmic";
 322
 323                         regulators {
 324                                 smps1_reg: smps1 {
 325                                         /* VDD_MPU */
 326                                         regulator-name = "smps1";
 327                                         regulator-min-microvolt = <850000>;
 328                                         regulator-max-microvolt = <1250000>;
 329                                         regulator-always-on;
 330                                         regulator-boot-on;
 331                                 };
 332
 333                                 smps2_reg: smps2 {
 334                                         /* VDD_CORE */
 335                                         regulator-name = "smps2";
 336                                         regulator-min-microvolt = <850000>;
 337                                         regulator-max-microvolt = <1060000>;
 338                                         regulator-boot-on;
 339                                         regulator-always-on;
 340                                 };
 341
 342                                 smps3_reg: smps3 {
 343                                         /* VDD_GPU IVA DSPEVE */
 344                                         regulator-name = "smps3";
 345                                         regulator-min-microvolt = <850000>;
 346                                         regulator-max-microvolt = <1250000>;
 347                                         regulator-boot-on;
 348                                         regulator-always-on;
 349                                 };
 350
 351                                 smps4_reg: smps4 {
 352                                         /* VDDS1V8 */
 353                                         regulator-name = "smps4";
 354                                         regulator-min-microvolt = <1800000>;
 355                                         regulator-max-microvolt = <1800000>;
 356                                         regulator-always-on;
 357                                         regulator-boot-on;
 358                                 };
 359
 360                                 smps5_reg: smps5 {
 361                                         /* VDD_DDR */
 362                                         regulator-name = "smps5";
 363                                         regulator-min-microvolt = <1350000>;
 364                                         regulator-max-microvolt = <1350000>;
 365                                         regulator-boot-on;
 366                                         regulator-always-on;
 367                                 };
 368
 369                                 ldo1_reg: ldo1 {
 370                                         /* LDO1_OUT --> SDIO  */
 371                                         regulator-name = "ldo1";
 372                                         regulator-min-microvolt = <1800000>;
 373                                         regulator-max-microvolt = <3300000>;
 374                                         regulator-always-on;
 375                                         regulator-boot-on;
 376                                 };
 377
 378                                 ldo2_reg: ldo2 {
 379                                         /* LDO2_OUT --> TP1017 (UNUSED)  */
 380                                         regulator-name = "ldo2";
 381                                         regulator-min-microvolt = <1800000>;
 382                                         regulator-max-microvolt = <3300000>;
 383                                 };
 384
 385                                 ldo3_reg: ldo3 {
 386                                         /* VDDA_1V8_PHY */
 387                                         regulator-name = "ldo3";
 388                                         regulator-min-microvolt = <1800000>;
 389                                         regulator-max-microvolt = <1800000>;
 390                                         regulator-boot-on;
 391                                         regulator-always-on;
 392                                 };
 393
 394                                 ldo5_reg: ldo5 {
 395                                         /* VDDA_1V8_PLL */
 396                                         regulator-name = "ldo5";
 397                                         regulator-min-microvolt = <1800000>;
 398                                         regulator-max-microvolt = <1800000>;
 399                                         regulator-always-on;
 400                                         regulator-boot-on;
 401                                 };
 402
 403                                 ldo4_reg: ldo4 {
 404                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 405                                         regulator-name = "ldo4";
 406                                         regulator-min-microvolt = <3300000>;
 407                                         regulator-max-microvolt = <3300000>;
 408                                         regulator-boot-on;
 409                                 };
 410                         };
 411                 };
 412
 413                 tps65917_power_button {
 414                         compatible = "ti,palmas-pwrbutton";
 415                         interrupt-parent = <&tps65917>;
 416                         interrupts = <1 IRQ_TYPE_NONE>;
 417                         wakeup-source;
 418                         ti,palmas-long-press-seconds = <6>;
 419                 };
 420         };
 421
 422         pcf_gpio_21: gpio@21 {
 423                 compatible = "ti,pcf8575";
 424                 reg = <0x21>;
 425                 lines-initial-states = <0x1408>;
 426                 gpio-controller;
 427                 #gpio-cells = <2>;
 428                 interrupt-parent = <&gpio6>;
 429                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 430                 interrupt-controller;
 431                 #interrupt-cells = <2>;
 432         };
 433
 434         tlv320aic3106: tlv320aic3106@19 {
 435                 #sound-dai-cells = <0>;
 436                 compatible = "ti,tlv320aic3106";
 437                 reg = <0x19>;
 438                 adc-settle-ms = <40>;
 439                 ai3x-micbias-vg = <1>;          /* 2.0V */
 440                 status = "okay";
 441
 442                 /* Regulators */
 443                 AVDD-supply = <&evm_3v3>;
 444                 IOVDD-supply = <&evm_3v3>;
 445                 DRVDD-supply = <&evm_3v3>;
 446                 DVDD-supply = <&aic_dvdd>;
 447         };
 448 };
 449
 450 &i2c5 {
 451         status = "okay";
 452         pinctrl-names = "default";
 453         pinctrl-0 = <&i2c5_pins>;
 454         clock-frequency = <400000>;
 455
 456         pcf_hdmi: pcf8575@26 {
 457                 compatible = "nxp,pcf8575";
 458                 reg = <0x26>;
 459                 gpio-controller;
 460                 #gpio-cells = <2>;
 461                 /*
 462                  * initial state is used here to keep the mdio interface
 463                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 464                  * VIN2_S0 driven high otherwise Ethernet stops working
 465                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 466                  */
 467                 lines-initial-states = <0x0f2b>;
 468
 469                 p1 {
 470                         /* vin6_sel_s0: high: VIN6, low: audio */
 471                         gpio-hog;
 472                         gpios = <1 GPIO_ACTIVE_HIGH>;
 473                         output-low;
 474                         line-name = "vin6_sel_s0";
 475                 };
 476         };
 477 };
 478
 479 &uart1 {
 480         status = "okay";
 481         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 482                               <&dra7_pmx_core 0x3e0>;
 483 };
 484
 485 &elm {
 486         status = "okay";
 487 };
 488
 489 &gpmc {
 490         status = "okay";
 491         pinctrl-names = "default";
 492         pinctrl-0 = <&nand_default>;
 493         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 494         nand@0,0 {
 495                 /* To use NAND, DIP switch SW5 must be set like so:
 496                  * SW5.1 (NAND_SELn) = ON (LOW)
 497                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 498                  */
 499                 reg = <0 0 4>;          /* device IO registers */
 500                 ti,nand-ecc-opt = "bch8";
 501                 ti,elm-id = <&elm>;
 502                 nand-bus-width = <16>;
 503                 gpmc,device-width = <2>;
 504                 gpmc,sync-clk-ps = <0>;
 505                 gpmc,cs-on-ns = <0>;
 506                 gpmc,cs-rd-off-ns = <80>;
 507                 gpmc,cs-wr-off-ns = <80>;
 508                 gpmc,adv-on-ns = <0>;
 509                 gpmc,adv-rd-off-ns = <60>;
 510                 gpmc,adv-wr-off-ns = <60>;
 511                 gpmc,we-on-ns = <10>;
 512                 gpmc,we-off-ns = <50>;
 513                 gpmc,oe-on-ns = <4>;
 514                 gpmc,oe-off-ns = <40>;
 515                 gpmc,access-ns = <40>;
 516                 gpmc,wr-access-ns = <80>;
 517                 gpmc,rd-cycle-ns = <80>;
 518                 gpmc,wr-cycle-ns = <80>;
 519                 gpmc,bus-turnaround-ns = <0>;
 520                 gpmc,cycle2cycle-delay-ns = <0>;
 521                 gpmc,clk-activation-ns = <0>;
 522                 gpmc,wait-monitoring-ns = <0>;
 523                 gpmc,wr-data-mux-bus-ns = <0>;
 524                 /* MTD partition table */
 525                 /* All SPL-* partitions are sized to minimal length
 526                  * which can be independently programmable. For
 527                  * NAND flash this is equal to size of erase-block */
 528                 #address-cells = <1>;
 529                 #size-cells = <1>;
 530                 partition@0 {
 531                         label = "NAND.SPL";
 532                         reg = <0x00000000 0x000020000>;
 533                 };
 534                 partition@1 {
 535                         label = "NAND.SPL.backup1";
 536                         reg = <0x00020000 0x00020000>;
 537                 };
 538                 partition@2 {
 539                         label = "NAND.SPL.backup2";
 540                         reg = <0x00040000 0x00020000>;
 541                 };
 542                 partition@3 {
 543                         label = "NAND.SPL.backup3";
 544                         reg = <0x00060000 0x00020000>;
 545                 };
 546                 partition@4 {
 547                         label = "NAND.u-boot-spl-os";
 548                         reg = <0x00080000 0x00040000>;
 549                 };
 550                 partition@5 {
 551                         label = "NAND.u-boot";
 552                         reg = <0x000c0000 0x00100000>;
 553                 };
 554                 partition@6 {
 555                         label = "NAND.u-boot-env";
 556                         reg = <0x001c0000 0x00020000>;
 557                 };
 558                 partition@7 {
 559                         label = "NAND.u-boot-env.backup1";
 560                         reg = <0x001e0000 0x00020000>;
 561                 };
 562                 partition@8 {
 563                         label = "NAND.kernel";
 564                         reg = <0x00200000 0x00800000>;
 565                 };
 566                 partition@9 {
 567                         label = "NAND.file-system";
 568                         reg = <0x00a00000 0x0f600000>;
 569                 };
 570         };
 571 };
 572
 573 &usb2_phy1 {
 574         phy-supply = <&ldo4_reg>;
 575 };
 576
 577 &usb2_phy2 {
 578         phy-supply = <&ldo4_reg>;
 579 };
 580
 581 &omap_dwc3_1 {
 582         extcon = <&extcon_usb1>;
 583 };
 584
 585 &omap_dwc3_2 {
 586         extcon = <&extcon_usb2>;
 587 };
 588
 589 &usb1 {
 590         dr_mode = "peripheral";
 591         pinctrl-names = "default";
 592         pinctrl-0 = <&usb1_pins>;
 593 };
 594
 595 &usb2 {
 596         dr_mode = "host";
 597         pinctrl-names = "default";
 598         pinctrl-0 = <&usb2_pins>;
 599 };
 600
 601 &mmc1 {
 602         status = "okay";
 603         pinctrl-names = "default";
 604         pinctrl-0 = <&mmc1_pins_default>;
 605         vmmc-supply = <&evm_3v3_sd>;
 606         vmmc_aux-supply = <&ldo1_reg>;
 607         bus-width = <4>;
 608         /*
 609          * SDCD signal is not being used here - using the fact that GPIO mode
 610          * is a viable alternative
 611          */
 612         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 613         max-frequency = <192000000>;
 614 };
 615
 616 &mmc2 {
 617         /* SW5-3 in ON position */
 618         status = "okay";
 619         pinctrl-names = "default";
 620         pinctrl-0 = <&mmc2_pins_default>;
 621
 622         vmmc-supply = <&evm_3v3>;
 623         bus-width = <8>;
 624         ti,non-removable;
 625         max-frequency = <192000000>;
 626 };
 627
 628 &dra7_pmx_core {
 629         cpsw_default: cpsw_default {
 630                 pinctrl-single,pins = <
 631                         /* Slave 2 */
 632                         DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d12.rgmii1_txc */
 633                         DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d13.rgmii1_tctl */
 634                         DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d14.rgmii1_td3 */
 635                         DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d15.rgmii1_td2 */
 636                         DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d16.rgmii1_td1 */
 637                         DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3)       /* vin2a_d17.rgmii1_td0 */
 638                         DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3)        /* vin2a_d18.rgmii1_rclk */
 639                         DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3)        /* vin2a_d19.rgmii1_rctl */
 640                         DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3)        /* vin2a_d20.rgmii1_rd3 */
 641                         DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3)        /* vin2a_d21.rgmii1_rd2 */
 642                         DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3)        /* vin2a_d22.rgmii1_rd1 */
 643                         DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3)        /* vin2a_d23.rgmii1_rd0 */
 644                 >;
 645
 646         };
 647
 648         cpsw_sleep: cpsw_sleep {
 649                 pinctrl-single,pins = <
 650                         /* Slave 2 */
 651                         DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
 652                         DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
 653                         DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
 654                         DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
 655                         DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
 656                         DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
 657                         DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
 658                         DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
 659                         DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
 660                         DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
 661                         DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
 662                         DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
 663                 >;
 664         };
 665
 666         davinci_mdio_default: davinci_mdio_default {
 667                 pinctrl-single,pins = <
 668                         /* MDIO */
 669                         DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)        /* mdio_d.mdio_d */
 670                         DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
 671                 >;
 672         };
 673
 674         davinci_mdio_sleep: davinci_mdio_sleep {
 675                 pinctrl-single,pins = <
 676                         DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
 677                         DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
 678                 >;
 679         };
 680 };
 681
 682 &mac {
 683         status = "okay";
 684         pinctrl-names = "default", "sleep";
 685         pinctrl-0 = <&cpsw_default>;
 686         pinctrl-1 = <&cpsw_sleep>;
 687         slaves = <1>;
 688         mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
 689 };
 690
 691 &cpsw_emac0 {
 692         phy_id = <&davinci_mdio>, <3>;
 693         phy-mode = "rgmii";
 694 };
 695
 696 &davinci_mdio {
 697         pinctrl-names = "default", "sleep";
 698         pinctrl-0 = <&davinci_mdio_default>;
 699         pinctrl-1 = <&davinci_mdio_sleep>;
 700 };
 701
 702 &dcan1 {
 703         status = "ok";
 704         pinctrl-names = "default", "sleep", "active";
 705         pinctrl-0 = <&dcan1_pins_sleep>;
 706         pinctrl-1 = <&dcan1_pins_sleep>;
 707         pinctrl-2 = <&dcan1_pins_default>;
 708 };
 709
 710 &qspi {
 711         status = "okay";
 712         pinctrl-names = "default";
 713         pinctrl-0 = <&qspi1_pins>;
 714
 715         spi-max-frequency = <48000000>;
 716         m25p80@0 {
 717                 compatible = "s25fl256s1";
 718                 spi-max-frequency = <48000000>;
 719                 reg = <0>;
 720                 spi-tx-bus-width = <1>;
 721                 spi-rx-bus-width = <4>;
 722                 spi-cpol;
 723                 spi-cpha;
 724                 #address-cells = <1>;
 725                 #size-cells = <1>;
 726
 727                 /* MTD partition table.
 728                  * The ROM checks the first four physical blocks
 729                  * for a valid file to boot and the flash here is
 730                  * 64KiB block size.
 731                  */
 732                 partition@0 {
 733                         label = "QSPI.SPL";
 734                         reg = <0x00000000 0x000010000>;
 735                 };
 736                 partition@1 {
 737                         label = "QSPI.SPL.backup1";
 738                         reg = <0x00010000 0x00010000>;
 739                 };
 740                 partition@2 {
 741                         label = "QSPI.SPL.backup2";
 742                         reg = <0x00020000 0x00010000>;
 743                 };
 744                 partition@3 {
 745                         label = "QSPI.SPL.backup3";
 746                         reg = <0x00030000 0x00010000>;
 747                 };
 748                 partition@4 {
 749                         label = "QSPI.u-boot";
 750                         reg = <0x00040000 0x00100000>;
 751                 };
 752                 partition@5 {
 753                         label = "QSPI.u-boot-spl-os";
 754                         reg = <0x00140000 0x00080000>;
 755                 };
 756                 partition@6 {
 757                         label = "QSPI.u-boot-env";
 758                         reg = <0x001c0000 0x00010000>;
 759                 };
 760                 partition@7 {
 761                         label = "QSPI.u-boot-env.backup1";
 762                         reg = <0x001d0000 0x0010000>;
 763                 };
 764                 partition@8 {
 765                         label = "QSPI.kernel";
 766                         reg = <0x001e0000 0x0800000>;
 767                 };
 768                 partition@9 {
 769                         label = "QSPI.file-system";
 770                         reg = <0x009e0000 0x01620000>;
 771                 };
 772         };
 773 };
 774
 775 &dss {
 776         status = "ok";
 777
 778         vdda_video-supply = <&ldo5_reg>;
 779 };
 780
 781 &hdmi {
 782         status = "ok";
 783         vdda-supply = <&ldo3_reg>;
 784
 785         pinctrl-names = "default";
 786         pinctrl-0 = <&hdmi_pins>;
 787
 788         port {
 789                 hdmi_out: endpoint {
 790                         remote-endpoint = <&tpd12s015_in>;
 791                 };
 792         };
 793 };
 794
 795 &atl {
 796         pinctrl-names = "default";
 797         pinctrl-0 = <&atl_pins>;
 798
 799         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 800                           <&atl_gfclk_mux>,
 801                           <&dpll_abe_ck>,
 802                           <&dpll_abe_m2x2_ck>,
 803                           <&atl_clkin2_ck>;
 804         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 805         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 806
 807         status = "okay";
 808
 809         atl2 {
 810                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 811                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 812         };
 813 };
 814
 815 &mcasp3 {
 816         #sound-dai-cells = <0>;
 817         pinctrl-names = "default", "sleep";
 818         pinctrl-0 = <&mcasp3_pins>;
 819         pinctrl-1 = <&mcasp3_sleep_pins>;
 820
 821         assigned-clocks = <&mcasp3_ahclkx_mux>;
 822         assigned-clock-parents = <&atl_clkin2_ck>;
 823
 824         status = "okay";
 825
 826         op-mode = <0>;          /* MCASP_IIS_MODE */
 827         tdm-slots = <2>;
 828         /* 4 serializer */
 829         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 830                 1 2 0 0
 831         >;
 832 };
 833
 834 &mailbox5 {
 835         status = "okay";
 836         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 837                 status = "okay";
 838         };
 839         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 840                 status = "okay";
 841         };
 842 };
 843
 844 &mailbox6 {
 845         status = "okay";
 846         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 847                 status = "okay";
 848         };
 849 };