1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
11 device_type = "memory";
12 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
20 ipu2_memory_region: ipu2-memory@95800000 {
21 compatible = "shared-dma-pool";
22 reg = <0x0 0x95800000 0x0 0x3800000>;
27 dsp1_memory_region: dsp1-memory@99000000 {
28 compatible = "shared-dma-pool";
29 reg = <0x0 0x99000000 0x0 0x4000000>;
34 ipu1_memory_region: ipu1-memory@9d000000 {
35 compatible = "shared-dma-pool";
36 reg = <0x0 0x9d000000 0x0 0x2000000>;
42 evm_1v8_sw: fixedregulator-evm_1v8 {
43 compatible = "regulator-fixed";
44 regulator-name = "evm_1v8";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 vin-supply = <&smps4_reg>;
54 tps65917: tps65917@58 {
57 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
61 #include "dra72-evm-tps65917.dtsi"
64 vdda-supply = <&ldo3_reg>;
68 interrupt-parent = <&gpio6>;
69 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
74 mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
78 phy-handle = <ðphy0>;
83 ethphy0: ethernet-phy@3 {
89 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
90 pinctrl-0 = <&mmc1_pins_default>;
91 pinctrl-1 = <&mmc1_pins_hs>;
92 pinctrl-2 = <&mmc1_pins_sdr12>;
93 pinctrl-3 = <&mmc1_pins_sdr25>;
94 pinctrl-4 = <&mmc1_pins_sdr50>;
95 pinctrl-5 = <&mmc1_pins_ddr50_rev10>;
96 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev10_conf>;
97 vqmmc-supply = <&ldo1_reg>;
101 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
102 pinctrl-0 = <&mmc2_pins_default>;
103 pinctrl-1 = <&mmc2_pins_hs>;
104 pinctrl-2 = <&mmc2_pins_ddr_rev10>;
105 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>;
106 vmmc-supply = <&evm_1v8_sw>;
111 memory-region = <&ipu2_memory_region>;
116 memory-region = <&ipu1_memory_region>;
121 memory-region = <&dsp1_memory_region>;