2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #define MAX_SOURCES 400
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&crossbar_mpu>;
39 ethernet0 = &cpsw_emac0;
40 ethernet1 = &cpsw_emac1;
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&gic>;
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
58 #interrupt-cells = <3>;
59 reg = <0x0 0x48211000 0x0 0x1000>,
60 <0x0 0x48212000 0x0 0x2000>,
61 <0x0 0x48214000 0x0 0x2000>,
62 <0x0 0x48216000 0x0 0x2000>;
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 interrupt-parent = <&gic>;
67 wakeupgen: interrupt-controller@48281000 {
68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 #interrupt-cells = <3>;
71 reg = <0x0 0x48281000 0x0 0x1000>;
72 interrupt-parent = <&gic>;
81 compatible = "arm,cortex-a15";
84 operating-points-v2 = <&cpu0_opp_table>;
86 clocks = <&dpll_mpu_ck>;
89 clock-latency = <300000>; /* From omap-cpufreq driver */
92 cooling-min-level = <0>;
93 cooling-max-level = <2>;
94 #cooling-cells = <2>; /* min followed by max */
98 cpu0_opp_table: opp-table {
99 compatible = "operating-points-v2-ti-cpu";
100 syscon = <&scm_wkup>;
103 opp-hz = /bits/ 64 <1000000000>;
104 opp-microvolt = <1060000 850000 1150000>;
105 opp-supported-hw = <0xFF 0x01>;
110 opp-hz = /bits/ 64 <1176000000>;
111 opp-microvolt = <1160000 885000 1160000>;
112 opp-supported-hw = <0xFF 0x02>;
117 * The soc node represents the soc top level view. It is used for IPs
118 * that are not memory mapped in the MPU view or for the MPU itself.
121 compatible = "ti,omap-infra";
123 compatible = "ti,omap5-mpu";
129 * XXX: Use a flat representation of the SOC interconnect.
130 * The real OMAP interconnect network is quite complex.
131 * Since it will not bring real advantage to represent that in DT for
132 * the moment, just use a fake OCP bus entry to represent the whole bus
136 compatible = "ti,dra7-l3-noc", "simple-bus";
137 #address-cells = <1>;
139 ranges = <0x0 0x0 0x0 0xc0000000>;
140 ti,hwmods = "l3_main_1", "l3_main_2";
141 reg = <0x0 0x44000000 0x0 0x1000000>,
142 <0x0 0x45000000 0x0 0x1000>;
143 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
144 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
146 l4_cfg: l4@4a000000 {
147 compatible = "ti,dra7-l4-cfg", "simple-bus";
148 #address-cells = <1>;
150 ranges = <0 0x4a000000 0x22c000>;
153 compatible = "ti,dra7-scm-core", "simple-bus";
154 reg = <0x2000 0x2000>;
155 #address-cells = <1>;
157 ranges = <0 0x2000 0x2000>;
159 scm_conf: scm_conf@0 {
160 compatible = "syscon", "simple-bus";
162 #address-cells = <1>;
164 ranges = <0 0x0 0x1400>;
166 pbias_regulator: pbias_regulator@e00 {
167 compatible = "ti,pbias-dra7", "ti,pbias-omap";
169 syscon = <&scm_conf>;
170 pbias_mmc_reg: pbias_mmc_omap5 {
171 regulator-name = "pbias_mmc_omap5";
172 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <3300000>;
177 scm_conf_clocks: clocks {
178 #address-cells = <1>;
183 dra7_pmx_core: pinmux@1400 {
184 compatible = "ti,dra7-padconf",
186 reg = <0x1400 0x0468>;
187 #address-cells = <1>;
189 #pinctrl-cells = <1>;
190 #interrupt-cells = <1>;
191 interrupt-controller;
192 pinctrl-single,register-width = <32>;
193 pinctrl-single,function-mask = <0x3fffffff>;
196 scm_conf1: scm_conf@1c04 {
197 compatible = "syscon";
198 reg = <0x1c04 0x0020>;
202 scm_conf_pcie: scm_conf@1c24 {
203 compatible = "syscon";
204 reg = <0x1c24 0x0024>;
207 sdma_xbar: dma-router@b78 {
208 compatible = "ti,dra7-dma-crossbar";
211 dma-requests = <205>;
212 ti,dma-safe-map = <0>;
213 dma-masters = <&sdma>;
216 edma_xbar: dma-router@c78 {
217 compatible = "ti,dra7-dma-crossbar";
220 dma-requests = <204>;
221 ti,dma-safe-map = <0>;
222 dma-masters = <&edma>;
226 cm_core_aon: cm_core_aon@5000 {
227 compatible = "ti,dra7-cm-core-aon";
228 reg = <0x5000 0x2000>;
230 cm_core_aon_clocks: clocks {
231 #address-cells = <1>;
235 cm_core_aon_clockdomains: clockdomains {
239 cm_core: cm_core@8000 {
240 compatible = "ti,dra7-cm-core";
241 reg = <0x8000 0x3000>;
243 cm_core_clocks: clocks {
244 #address-cells = <1>;
248 cm_core_clockdomains: clockdomains {
253 l4_wkup: l4@4ae00000 {
254 compatible = "ti,dra7-l4-wkup", "simple-bus";
255 #address-cells = <1>;
257 ranges = <0 0x4ae00000 0x3f000>;
259 counter32k: counter@4000 {
260 compatible = "ti,omap-counter32k";
262 ti,hwmods = "counter_32k";
266 compatible = "ti,dra7-prm";
267 reg = <0x6000 0x3000>;
268 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
271 #address-cells = <1>;
275 prm_clockdomains: clockdomains {
279 scm_wkup: scm_conf@c000 {
280 compatible = "syscon";
281 reg = <0xc000 0x1000>;
286 compatible = "simple-bus";
288 #address-cells = <1>;
289 ranges = <0x51000000 0x51000000 0x3000
290 0x0 0x20000000 0x10000000>;
292 * To enable PCI endpoint mode, disable the pcie1_rc
293 * node and enable pcie1_ep mode.
295 pcie1_rc: pcie@51000000 {
296 compatible = "ti,dra7-pcie";
297 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
298 reg-names = "rc_dbics", "ti_conf", "config";
299 interrupts = <0 232 0x4>, <0 233 0x4>;
300 #address-cells = <3>;
303 ranges = <0x81000000 0 0 0x03000 0 0x00010000
304 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
305 bus-range = <0x00 0xff>;
306 #interrupt-cells = <1>;
308 linux,pci-domain = <0>;
311 phy-names = "pcie-phy0";
312 interrupt-map-mask = <0 0 0 7>;
313 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
314 <0 0 0 2 &pcie1_intc 2>,
315 <0 0 0 3 &pcie1_intc 3>,
316 <0 0 0 4 &pcie1_intc 4>;
318 pcie1_intc: interrupt-controller {
319 interrupt-controller;
320 #address-cells = <0>;
321 #interrupt-cells = <1>;
325 pcie1_ep: pcie_ep@51000000 {
326 compatible = "ti,dra7-pcie-ep";
327 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
328 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
329 interrupts = <0 232 0x4>;
331 num-ib-windows = <4>;
332 num-ob-windows = <16>;
335 phy-names = "pcie-phy0";
336 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
342 compatible = "simple-bus";
344 #address-cells = <1>;
345 ranges = <0x51800000 0x51800000 0x3000
346 0x0 0x30000000 0x10000000>;
349 compatible = "ti,dra7-pcie";
350 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
351 reg-names = "rc_dbics", "ti_conf", "config";
352 interrupts = <0 355 0x4>, <0 356 0x4>;
353 #address-cells = <3>;
356 ranges = <0x81000000 0 0 0x03000 0 0x00010000
357 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
358 bus-range = <0x00 0xff>;
359 #interrupt-cells = <1>;
361 linux,pci-domain = <1>;
364 phy-names = "pcie-phy0";
365 interrupt-map-mask = <0 0 0 7>;
366 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
367 <0 0 0 2 &pcie2_intc 2>,
368 <0 0 0 3 &pcie2_intc 3>,
369 <0 0 0 4 &pcie2_intc 4>;
370 pcie2_intc: interrupt-controller {
371 interrupt-controller;
372 #address-cells = <0>;
373 #interrupt-cells = <1>;
378 ocmcram1: ocmcram@40300000 {
379 compatible = "mmio-sram";
380 reg = <0x40300000 0x80000>;
381 ranges = <0x0 0x40300000 0x80000>;
382 #address-cells = <1>;
385 * This is a placeholder for an optional reserved
386 * region for use by secure software. The size
387 * of this region is not known until runtime so it
388 * is set as zero to either be updated to reserve
389 * space or left unchanged to leave all SRAM for use.
390 * On HS parts that that require the reserved region
391 * either the bootloader can update the size to
392 * the required amount or the node can be overridden
393 * from the board dts file for the secure platform.
396 compatible = "ti,secure-ram";
402 * NOTE: ocmcram2 and ocmcram3 are not available on all
403 * DRA7xx and AM57xx variants. Confirm availability in
404 * the data manual for the exact part number in use
405 * before enabling these nodes in the board dts file.
407 ocmcram2: ocmcram@40400000 {
409 compatible = "mmio-sram";
410 reg = <0x40400000 0x100000>;
411 ranges = <0x0 0x40400000 0x100000>;
412 #address-cells = <1>;
416 ocmcram3: ocmcram@40500000 {
418 compatible = "mmio-sram";
419 reg = <0x40500000 0x100000>;
420 ranges = <0x0 0x40500000 0x100000>;
421 #address-cells = <1>;
425 bandgap: bandgap@4a0021e0 {
426 reg = <0x4a0021e0 0xc
432 compatible = "ti,dra752-bandgap";
433 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
434 #thermal-sensor-cells = <1>;
437 dsp1_system: dsp_system@40d00000 {
438 compatible = "syscon";
439 reg = <0x40d00000 0x100>;
442 dra7_iodelay_core: padconf@4844a000 {
443 compatible = "ti,dra7-iodelay";
444 reg = <0x4844a000 0x0d1c>;
445 #address-cells = <1>;
447 #pinctrl-cells = <2>;
450 sdma: dma-controller@4a056000 {
451 compatible = "ti,omap4430-sdma";
452 reg = <0x4a056000 0x1000>;
453 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
459 dma-requests = <127>;
460 ti,hwmods = "dma_system";
463 edma: edma@43300000 {
464 compatible = "ti,edma3-tpcc";
466 reg = <0x43300000 0x100000>;
467 reg-names = "edma3_cc";
468 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-names = "edma3_ccint", "edma3_mperr",
476 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
479 * memcpy is disabled, can be enabled with:
480 * ti,edma-memcpy-channels = <20 21>;
481 * for example. Note that these channels need to be
482 * masked in the xbar as well.
486 edma_tptc0: tptc@43400000 {
487 compatible = "ti,edma3-tptc";
489 reg = <0x43400000 0x100000>;
490 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
491 interrupt-names = "edma3_tcerrint";
494 edma_tptc1: tptc@43500000 {
495 compatible = "ti,edma3-tptc";
497 reg = <0x43500000 0x100000>;
498 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
499 interrupt-names = "edma3_tcerrint";
502 gpio1: gpio@4ae10000 {
503 compatible = "ti,omap4-gpio";
504 reg = <0x4ae10000 0x200>;
505 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
513 gpio2: gpio@48055000 {
514 compatible = "ti,omap4-gpio";
515 reg = <0x48055000 0x200>;
516 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
524 gpio3: gpio@48057000 {
525 compatible = "ti,omap4-gpio";
526 reg = <0x48057000 0x200>;
527 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
535 gpio4: gpio@48059000 {
536 compatible = "ti,omap4-gpio";
537 reg = <0x48059000 0x200>;
538 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
546 gpio5: gpio@4805b000 {
547 compatible = "ti,omap4-gpio";
548 reg = <0x4805b000 0x200>;
549 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
557 gpio6: gpio@4805d000 {
558 compatible = "ti,omap4-gpio";
559 reg = <0x4805d000 0x200>;
560 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
568 gpio7: gpio@48051000 {
569 compatible = "ti,omap4-gpio";
570 reg = <0x48051000 0x200>;
571 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
579 gpio8: gpio@48053000 {
580 compatible = "ti,omap4-gpio";
581 reg = <0x48053000 0x200>;
582 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
586 interrupt-controller;
587 #interrupt-cells = <2>;
590 uart1: serial@4806a000 {
591 compatible = "ti,dra742-uart", "ti,omap4-uart";
592 reg = <0x4806a000 0x100>;
593 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
595 clock-frequency = <48000000>;
597 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
598 dma-names = "tx", "rx";
601 uart2: serial@4806c000 {
602 compatible = "ti,dra742-uart", "ti,omap4-uart";
603 reg = <0x4806c000 0x100>;
604 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
606 clock-frequency = <48000000>;
608 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
609 dma-names = "tx", "rx";
612 uart3: serial@48020000 {
613 compatible = "ti,dra742-uart", "ti,omap4-uart";
614 reg = <0x48020000 0x100>;
615 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
617 clock-frequency = <48000000>;
619 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
620 dma-names = "tx", "rx";
623 uart4: serial@4806e000 {
624 compatible = "ti,dra742-uart", "ti,omap4-uart";
625 reg = <0x4806e000 0x100>;
626 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
628 clock-frequency = <48000000>;
630 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
631 dma-names = "tx", "rx";
634 uart5: serial@48066000 {
635 compatible = "ti,dra742-uart", "ti,omap4-uart";
636 reg = <0x48066000 0x100>;
637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
639 clock-frequency = <48000000>;
641 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
642 dma-names = "tx", "rx";
645 uart6: serial@48068000 {
646 compatible = "ti,dra742-uart", "ti,omap4-uart";
647 reg = <0x48068000 0x100>;
648 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
650 clock-frequency = <48000000>;
652 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
653 dma-names = "tx", "rx";
656 uart7: serial@48420000 {
657 compatible = "ti,dra742-uart", "ti,omap4-uart";
658 reg = <0x48420000 0x100>;
659 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
661 clock-frequency = <48000000>;
665 uart8: serial@48422000 {
666 compatible = "ti,dra742-uart", "ti,omap4-uart";
667 reg = <0x48422000 0x100>;
668 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
670 clock-frequency = <48000000>;
674 uart9: serial@48424000 {
675 compatible = "ti,dra742-uart", "ti,omap4-uart";
676 reg = <0x48424000 0x100>;
677 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
679 clock-frequency = <48000000>;
683 uart10: serial@4ae2b000 {
684 compatible = "ti,dra742-uart", "ti,omap4-uart";
685 reg = <0x4ae2b000 0x100>;
686 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
687 ti,hwmods = "uart10";
688 clock-frequency = <48000000>;
692 mailbox1: mailbox@4a0f4000 {
693 compatible = "ti,omap4-mailbox";
694 reg = <0x4a0f4000 0x200>;
695 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
698 ti,hwmods = "mailbox1";
700 ti,mbox-num-users = <3>;
701 ti,mbox-num-fifos = <8>;
705 mailbox2: mailbox@4883a000 {
706 compatible = "ti,omap4-mailbox";
707 reg = <0x4883a000 0x200>;
708 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
712 ti,hwmods = "mailbox2";
714 ti,mbox-num-users = <4>;
715 ti,mbox-num-fifos = <12>;
719 mailbox3: mailbox@4883c000 {
720 compatible = "ti,omap4-mailbox";
721 reg = <0x4883c000 0x200>;
722 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
726 ti,hwmods = "mailbox3";
728 ti,mbox-num-users = <4>;
729 ti,mbox-num-fifos = <12>;
733 mailbox4: mailbox@4883e000 {
734 compatible = "ti,omap4-mailbox";
735 reg = <0x4883e000 0x200>;
736 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
740 ti,hwmods = "mailbox4";
742 ti,mbox-num-users = <4>;
743 ti,mbox-num-fifos = <12>;
747 mailbox5: mailbox@48840000 {
748 compatible = "ti,omap4-mailbox";
749 reg = <0x48840000 0x200>;
750 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
754 ti,hwmods = "mailbox5";
756 ti,mbox-num-users = <4>;
757 ti,mbox-num-fifos = <12>;
761 mailbox6: mailbox@48842000 {
762 compatible = "ti,omap4-mailbox";
763 reg = <0x48842000 0x200>;
764 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
768 ti,hwmods = "mailbox6";
770 ti,mbox-num-users = <4>;
771 ti,mbox-num-fifos = <12>;
775 mailbox7: mailbox@48844000 {
776 compatible = "ti,omap4-mailbox";
777 reg = <0x48844000 0x200>;
778 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
782 ti,hwmods = "mailbox7";
784 ti,mbox-num-users = <4>;
785 ti,mbox-num-fifos = <12>;
789 mailbox8: mailbox@48846000 {
790 compatible = "ti,omap4-mailbox";
791 reg = <0x48846000 0x200>;
792 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
794 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
796 ti,hwmods = "mailbox8";
798 ti,mbox-num-users = <4>;
799 ti,mbox-num-fifos = <12>;
803 mailbox9: mailbox@4885e000 {
804 compatible = "ti,omap4-mailbox";
805 reg = <0x4885e000 0x200>;
806 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
810 ti,hwmods = "mailbox9";
812 ti,mbox-num-users = <4>;
813 ti,mbox-num-fifos = <12>;
817 mailbox10: mailbox@48860000 {
818 compatible = "ti,omap4-mailbox";
819 reg = <0x48860000 0x200>;
820 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
824 ti,hwmods = "mailbox10";
826 ti,mbox-num-users = <4>;
827 ti,mbox-num-fifos = <12>;
831 mailbox11: mailbox@48862000 {
832 compatible = "ti,omap4-mailbox";
833 reg = <0x48862000 0x200>;
834 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
838 ti,hwmods = "mailbox11";
840 ti,mbox-num-users = <4>;
841 ti,mbox-num-fifos = <12>;
845 mailbox12: mailbox@48864000 {
846 compatible = "ti,omap4-mailbox";
847 reg = <0x48864000 0x200>;
848 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
852 ti,hwmods = "mailbox12";
854 ti,mbox-num-users = <4>;
855 ti,mbox-num-fifos = <12>;
859 mailbox13: mailbox@48802000 {
860 compatible = "ti,omap4-mailbox";
861 reg = <0x48802000 0x200>;
862 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
865 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
866 ti,hwmods = "mailbox13";
868 ti,mbox-num-users = <4>;
869 ti,mbox-num-fifos = <12>;
873 timer1: timer@4ae18000 {
874 compatible = "ti,omap5430-timer";
875 reg = <0x4ae18000 0x80>;
876 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
877 ti,hwmods = "timer1";
881 timer2: timer@48032000 {
882 compatible = "ti,omap5430-timer";
883 reg = <0x48032000 0x80>;
884 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
885 ti,hwmods = "timer2";
888 timer3: timer@48034000 {
889 compatible = "ti,omap5430-timer";
890 reg = <0x48034000 0x80>;
891 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
892 ti,hwmods = "timer3";
895 timer4: timer@48036000 {
896 compatible = "ti,omap5430-timer";
897 reg = <0x48036000 0x80>;
898 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
899 ti,hwmods = "timer4";
902 timer5: timer@48820000 {
903 compatible = "ti,omap5430-timer";
904 reg = <0x48820000 0x80>;
905 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
906 ti,hwmods = "timer5";
909 timer6: timer@48822000 {
910 compatible = "ti,omap5430-timer";
911 reg = <0x48822000 0x80>;
912 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
913 ti,hwmods = "timer6";
916 timer7: timer@48824000 {
917 compatible = "ti,omap5430-timer";
918 reg = <0x48824000 0x80>;
919 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
920 ti,hwmods = "timer7";
923 timer8: timer@48826000 {
924 compatible = "ti,omap5430-timer";
925 reg = <0x48826000 0x80>;
926 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
927 ti,hwmods = "timer8";
930 timer9: timer@4803e000 {
931 compatible = "ti,omap5430-timer";
932 reg = <0x4803e000 0x80>;
933 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
934 ti,hwmods = "timer9";
937 timer10: timer@48086000 {
938 compatible = "ti,omap5430-timer";
939 reg = <0x48086000 0x80>;
940 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
941 ti,hwmods = "timer10";
944 timer11: timer@48088000 {
945 compatible = "ti,omap5430-timer";
946 reg = <0x48088000 0x80>;
947 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
948 ti,hwmods = "timer11";
951 timer12: timer@4ae20000 {
952 compatible = "ti,omap5430-timer";
953 reg = <0x4ae20000 0x80>;
954 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
955 ti,hwmods = "timer12";
960 timer13: timer@48828000 {
961 compatible = "ti,omap5430-timer";
962 reg = <0x48828000 0x80>;
963 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
964 ti,hwmods = "timer13";
967 timer14: timer@4882a000 {
968 compatible = "ti,omap5430-timer";
969 reg = <0x4882a000 0x80>;
970 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
971 ti,hwmods = "timer14";
974 timer15: timer@4882c000 {
975 compatible = "ti,omap5430-timer";
976 reg = <0x4882c000 0x80>;
977 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
978 ti,hwmods = "timer15";
981 timer16: timer@4882e000 {
982 compatible = "ti,omap5430-timer";
983 reg = <0x4882e000 0x80>;
984 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
985 ti,hwmods = "timer16";
989 compatible = "ti,omap3-wdt";
990 reg = <0x4ae14000 0x80>;
991 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
992 ti,hwmods = "wd_timer2";
995 hwspinlock: spinlock@4a0f6000 {
996 compatible = "ti,omap4-hwspinlock";
997 reg = <0x4a0f6000 0x1000>;
998 ti,hwmods = "spinlock";
1003 compatible = "ti,omap5-dmm";
1004 reg = <0x4e000000 0x800>;
1005 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1009 i2c1: i2c@48070000 {
1010 compatible = "ti,omap4-i2c";
1011 reg = <0x48070000 0x100>;
1012 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1013 #address-cells = <1>;
1016 status = "disabled";
1019 i2c2: i2c@48072000 {
1020 compatible = "ti,omap4-i2c";
1021 reg = <0x48072000 0x100>;
1022 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1023 #address-cells = <1>;
1026 status = "disabled";
1029 i2c3: i2c@48060000 {
1030 compatible = "ti,omap4-i2c";
1031 reg = <0x48060000 0x100>;
1032 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1033 #address-cells = <1>;
1036 status = "disabled";
1039 i2c4: i2c@4807a000 {
1040 compatible = "ti,omap4-i2c";
1041 reg = <0x4807a000 0x100>;
1042 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1043 #address-cells = <1>;
1046 status = "disabled";
1049 i2c5: i2c@4807c000 {
1050 compatible = "ti,omap4-i2c";
1051 reg = <0x4807c000 0x100>;
1052 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1053 #address-cells = <1>;
1056 status = "disabled";
1059 mmc1: mmc@4809c000 {
1060 compatible = "ti,omap4-hsmmc";
1061 reg = <0x4809c000 0x400>;
1062 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1065 ti,needs-special-reset;
1066 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1067 dma-names = "tx", "rx";
1068 status = "disabled";
1069 pbias-supply = <&pbias_mmc_reg>;
1070 max-frequency = <192000000>;
1073 hdqw1w: 1w@480b2000 {
1074 compatible = "ti,omap3-1w";
1075 reg = <0x480b2000 0x1000>;
1076 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1077 ti,hwmods = "hdq1w";
1080 mmc2: mmc@480b4000 {
1081 compatible = "ti,omap4-hsmmc";
1082 reg = <0x480b4000 0x400>;
1083 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1085 ti,needs-special-reset;
1086 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1087 dma-names = "tx", "rx";
1088 status = "disabled";
1089 max-frequency = <192000000>;
1092 mmc3: mmc@480ad000 {
1093 compatible = "ti,omap4-hsmmc";
1094 reg = <0x480ad000 0x400>;
1095 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1097 ti,needs-special-reset;
1098 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1099 dma-names = "tx", "rx";
1100 status = "disabled";
1101 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1102 max-frequency = <64000000>;
1105 mmc4: mmc@480d1000 {
1106 compatible = "ti,omap4-hsmmc";
1107 reg = <0x480d1000 0x400>;
1108 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1110 ti,needs-special-reset;
1111 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1112 dma-names = "tx", "rx";
1113 status = "disabled";
1114 max-frequency = <192000000>;
1117 mmu0_dsp1: mmu@40d01000 {
1118 compatible = "ti,dra7-dsp-iommu";
1119 reg = <0x40d01000 0x100>;
1120 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1121 ti,hwmods = "mmu0_dsp1";
1123 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1124 status = "disabled";
1127 mmu1_dsp1: mmu@40d02000 {
1128 compatible = "ti,dra7-dsp-iommu";
1129 reg = <0x40d02000 0x100>;
1130 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1131 ti,hwmods = "mmu1_dsp1";
1133 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1134 status = "disabled";
1137 mmu_ipu1: mmu@58882000 {
1138 compatible = "ti,dra7-iommu";
1139 reg = <0x58882000 0x100>;
1140 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1141 ti,hwmods = "mmu_ipu1";
1143 ti,iommu-bus-err-back;
1144 status = "disabled";
1147 mmu_ipu2: mmu@55082000 {
1148 compatible = "ti,dra7-iommu";
1149 reg = <0x55082000 0x100>;
1150 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1151 ti,hwmods = "mmu_ipu2";
1153 ti,iommu-bus-err-back;
1154 status = "disabled";
1157 abb_mpu: regulator-abb-mpu {
1158 compatible = "ti,abb-v3";
1159 regulator-name = "abb_mpu";
1160 #address-cells = <0>;
1162 clocks = <&sys_clkin1>;
1163 ti,settling-time = <50>;
1164 ti,clock-cycles = <16>;
1166 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1167 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1169 reg-names = "setup-address", "control-address",
1170 "int-address", "efuse-address",
1172 ti,tranxdone-status-mask = <0x80>;
1173 /* LDOVBBMPU_FBB_MUX_CTRL */
1174 ti,ldovbb-override-mask = <0x400>;
1175 /* LDOVBBMPU_FBB_VSET_OUT */
1176 ti,ldovbb-vset-mask = <0x1F>;
1179 * NOTE: only FBB mode used but actual vset will
1180 * determine final biasing
1183 /*uV ABB efuse rbb_m fbb_m vset_m*/
1184 1060000 0 0x0 0 0x02000000 0x01F00000
1185 1160000 0 0x4 0 0x02000000 0x01F00000
1186 1210000 0 0x8 0 0x02000000 0x01F00000
1190 abb_ivahd: regulator-abb-ivahd {
1191 compatible = "ti,abb-v3";
1192 regulator-name = "abb_ivahd";
1193 #address-cells = <0>;
1195 clocks = <&sys_clkin1>;
1196 ti,settling-time = <50>;
1197 ti,clock-cycles = <16>;
1199 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1200 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1202 reg-names = "setup-address", "control-address",
1203 "int-address", "efuse-address",
1205 ti,tranxdone-status-mask = <0x40000000>;
1206 /* LDOVBBIVA_FBB_MUX_CTRL */
1207 ti,ldovbb-override-mask = <0x400>;
1208 /* LDOVBBIVA_FBB_VSET_OUT */
1209 ti,ldovbb-vset-mask = <0x1F>;
1212 * NOTE: only FBB mode used but actual vset will
1213 * determine final biasing
1216 /*uV ABB efuse rbb_m fbb_m vset_m*/
1217 1055000 0 0x0 0 0x02000000 0x01F00000
1218 1150000 0 0x4 0 0x02000000 0x01F00000
1219 1250000 0 0x8 0 0x02000000 0x01F00000
1223 abb_dspeve: regulator-abb-dspeve {
1224 compatible = "ti,abb-v3";
1225 regulator-name = "abb_dspeve";
1226 #address-cells = <0>;
1228 clocks = <&sys_clkin1>;
1229 ti,settling-time = <50>;
1230 ti,clock-cycles = <16>;
1232 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1233 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1235 reg-names = "setup-address", "control-address",
1236 "int-address", "efuse-address",
1238 ti,tranxdone-status-mask = <0x20000000>;
1239 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1240 ti,ldovbb-override-mask = <0x400>;
1241 /* LDOVBBDSPEVE_FBB_VSET_OUT */
1242 ti,ldovbb-vset-mask = <0x1F>;
1245 * NOTE: only FBB mode used but actual vset will
1246 * determine final biasing
1249 /*uV ABB efuse rbb_m fbb_m vset_m*/
1250 1055000 0 0x0 0 0x02000000 0x01F00000
1251 1150000 0 0x4 0 0x02000000 0x01F00000
1252 1250000 0 0x8 0 0x02000000 0x01F00000
1256 abb_gpu: regulator-abb-gpu {
1257 compatible = "ti,abb-v3";
1258 regulator-name = "abb_gpu";
1259 #address-cells = <0>;
1261 clocks = <&sys_clkin1>;
1262 ti,settling-time = <50>;
1263 ti,clock-cycles = <16>;
1265 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1266 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1268 reg-names = "setup-address", "control-address",
1269 "int-address", "efuse-address",
1271 ti,tranxdone-status-mask = <0x10000000>;
1272 /* LDOVBBGPU_FBB_MUX_CTRL */
1273 ti,ldovbb-override-mask = <0x400>;
1274 /* LDOVBBGPU_FBB_VSET_OUT */
1275 ti,ldovbb-vset-mask = <0x1F>;
1278 * NOTE: only FBB mode used but actual vset will
1279 * determine final biasing
1282 /*uV ABB efuse rbb_m fbb_m vset_m*/
1283 1090000 0 0x0 0 0x02000000 0x01F00000
1284 1210000 0 0x4 0 0x02000000 0x01F00000
1285 1280000 0 0x8 0 0x02000000 0x01F00000
1289 mcspi1: spi@48098000 {
1290 compatible = "ti,omap4-mcspi";
1291 reg = <0x48098000 0x200>;
1292 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1293 #address-cells = <1>;
1295 ti,hwmods = "mcspi1";
1296 ti,spi-num-cs = <4>;
1297 dmas = <&sdma_xbar 35>,
1305 dma-names = "tx0", "rx0", "tx1", "rx1",
1306 "tx2", "rx2", "tx3", "rx3";
1307 status = "disabled";
1310 mcspi2: spi@4809a000 {
1311 compatible = "ti,omap4-mcspi";
1312 reg = <0x4809a000 0x200>;
1313 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1314 #address-cells = <1>;
1316 ti,hwmods = "mcspi2";
1317 ti,spi-num-cs = <2>;
1318 dmas = <&sdma_xbar 43>,
1322 dma-names = "tx0", "rx0", "tx1", "rx1";
1323 status = "disabled";
1326 mcspi3: spi@480b8000 {
1327 compatible = "ti,omap4-mcspi";
1328 reg = <0x480b8000 0x200>;
1329 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1330 #address-cells = <1>;
1332 ti,hwmods = "mcspi3";
1333 ti,spi-num-cs = <2>;
1334 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1335 dma-names = "tx0", "rx0";
1336 status = "disabled";
1339 mcspi4: spi@480ba000 {
1340 compatible = "ti,omap4-mcspi";
1341 reg = <0x480ba000 0x200>;
1342 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cells = <1>;
1345 ti,hwmods = "mcspi4";
1346 ti,spi-num-cs = <1>;
1347 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1348 dma-names = "tx0", "rx0";
1349 status = "disabled";
1352 qspi: qspi@4b300000 {
1353 compatible = "ti,dra7xxx-qspi";
1354 reg = <0x4b300000 0x100>,
1355 <0x5c000000 0x4000000>;
1356 reg-names = "qspi_base", "qspi_mmap";
1357 syscon-chipselects = <&scm_conf 0x558>;
1358 #address-cells = <1>;
1361 clocks = <&qspi_gfclk_div>;
1362 clock-names = "fck";
1364 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1365 status = "disabled";
1370 compatible = "ti,omap-ocp2scp";
1371 #address-cells = <1>;
1374 reg = <0x4a090000 0x20>;
1375 ti,hwmods = "ocp2scp3";
1376 sata_phy: phy@4A096000 {
1377 compatible = "ti,phy-pipe3-sata";
1378 reg = <0x4A096000 0x80>, /* phy_rx */
1379 <0x4A096400 0x64>, /* phy_tx */
1380 <0x4A096800 0x40>; /* pll_ctrl */
1381 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1382 syscon-phy-power = <&scm_conf 0x374>;
1383 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1384 clock-names = "sysclk", "refclk";
1385 syscon-pllreset = <&scm_conf 0x3fc>;
1389 pcie1_phy: pciephy@4a094000 {
1390 compatible = "ti,phy-pipe3-pcie";
1391 reg = <0x4a094000 0x80>, /* phy_rx */
1392 <0x4a094400 0x64>; /* phy_tx */
1393 reg-names = "phy_rx", "phy_tx";
1394 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1395 syscon-pcs = <&scm_conf_pcie 0x10>;
1396 clocks = <&dpll_pcie_ref_ck>,
1397 <&dpll_pcie_ref_m2ldo_ck>,
1398 <&optfclk_pciephy1_32khz>,
1399 <&optfclk_pciephy1_clk>,
1400 <&optfclk_pciephy1_div_clk>,
1401 <&optfclk_pciephy_div>,
1403 clock-names = "dpll_ref", "dpll_ref_m2",
1404 "wkupclk", "refclk",
1405 "div-clk", "phy-div", "sysclk";
1409 pcie2_phy: pciephy@4a095000 {
1410 compatible = "ti,phy-pipe3-pcie";
1411 reg = <0x4a095000 0x80>, /* phy_rx */
1412 <0x4a095400 0x64>; /* phy_tx */
1413 reg-names = "phy_rx", "phy_tx";
1414 syscon-phy-power = <&scm_conf_pcie 0x20>;
1415 syscon-pcs = <&scm_conf_pcie 0x10>;
1416 clocks = <&dpll_pcie_ref_ck>,
1417 <&dpll_pcie_ref_m2ldo_ck>,
1418 <&optfclk_pciephy2_32khz>,
1419 <&optfclk_pciephy2_clk>,
1420 <&optfclk_pciephy2_div_clk>,
1421 <&optfclk_pciephy_div>,
1423 clock-names = "dpll_ref", "dpll_ref_m2",
1424 "wkupclk", "refclk",
1425 "div-clk", "phy-div", "sysclk";
1427 status = "disabled";
1431 sata: sata@4a141100 {
1432 compatible = "snps,dwc-ahci";
1433 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1434 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1436 phy-names = "sata-phy";
1437 clocks = <&sata_ref_clk>;
1439 ports-implemented = <0x1>;
1443 compatible = "ti,am3352-rtc";
1444 reg = <0x48838000 0x100>;
1445 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1447 ti,hwmods = "rtcss";
1448 clocks = <&sys_32k_ck>;
1453 compatible = "ti,omap-ocp2scp";
1454 #address-cells = <1>;
1457 reg = <0x4a080000 0x20>;
1458 ti,hwmods = "ocp2scp1";
1460 usb2_phy1: phy@4a084000 {
1461 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1462 reg = <0x4a084000 0x400>;
1463 syscon-phy-power = <&scm_conf 0x300>;
1464 clocks = <&usb_phy1_always_on_clk32k>,
1465 <&usb_otg_ss1_refclk960m>;
1466 clock-names = "wkupclk",
1471 usb2_phy2: phy@4a085000 {
1472 compatible = "ti,dra7x-usb2-phy2",
1474 reg = <0x4a085000 0x400>;
1475 syscon-phy-power = <&scm_conf 0xe74>;
1476 clocks = <&usb_phy2_always_on_clk32k>,
1477 <&usb_otg_ss2_refclk960m>;
1478 clock-names = "wkupclk",
1483 usb3_phy1: phy@4a084400 {
1484 compatible = "ti,omap-usb3";
1485 reg = <0x4a084400 0x80>,
1488 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1489 syscon-phy-power = <&scm_conf 0x370>;
1490 clocks = <&usb_phy3_always_on_clk32k>,
1492 <&usb_otg_ss1_refclk960m>;
1493 clock-names = "wkupclk",
1500 target-module@4a0dd000 {
1501 compatible = "ti,sysc-omap4-sr";
1502 ti,hwmods = "smartreflex_core";
1503 reg = <0x4a0dd000 0x4>,
1505 reg-names = "rev", "sysc";
1506 #address-cells = <1>;
1508 ranges = <0 0x4a0dd000 0x001000>;
1510 /* SmartReflex child device marked reserved in TRM */
1513 target-module@4a0d9000 {
1514 compatible = "ti,sysc-omap4-sr";
1515 ti,hwmods = "smartreflex_mpu";
1516 reg = <0x4a0d9000 0x4>,
1518 reg-names = "rev", "sysc";
1519 #address-cells = <1>;
1521 ranges = <0 0x4a0d9000 0x001000>;
1523 /* SmartReflex child device marked reserved in TRM */
1526 omap_dwc3_1: omap_dwc3_1@48880000 {
1527 compatible = "ti,dwc3";
1528 ti,hwmods = "usb_otg_ss1";
1529 reg = <0x48880000 0x10000>;
1530 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1531 #address-cells = <1>;
1535 usb1: usb@48890000 {
1536 compatible = "snps,dwc3";
1537 reg = <0x48890000 0x17000>;
1538 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1541 interrupt-names = "peripheral",
1544 phys = <&usb2_phy1>, <&usb3_phy1>;
1545 phy-names = "usb2-phy", "usb3-phy";
1546 maximum-speed = "super-speed";
1548 snps,dis_u3_susphy_quirk;
1549 snps,dis_u2_susphy_quirk;
1553 omap_dwc3_2: omap_dwc3_2@488c0000 {
1554 compatible = "ti,dwc3";
1555 ti,hwmods = "usb_otg_ss2";
1556 reg = <0x488c0000 0x10000>;
1557 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1558 #address-cells = <1>;
1562 usb2: usb@488d0000 {
1563 compatible = "snps,dwc3";
1564 reg = <0x488d0000 0x17000>;
1565 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1566 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1567 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1568 interrupt-names = "peripheral",
1571 phys = <&usb2_phy2>;
1572 phy-names = "usb2-phy";
1573 maximum-speed = "high-speed";
1575 snps,dis_u3_susphy_quirk;
1576 snps,dis_u2_susphy_quirk;
1580 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1581 omap_dwc3_3: omap_dwc3_3@48900000 {
1582 compatible = "ti,dwc3";
1583 ti,hwmods = "usb_otg_ss3";
1584 reg = <0x48900000 0x10000>;
1585 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1586 #address-cells = <1>;
1590 status = "disabled";
1591 usb3: usb@48910000 {
1592 compatible = "snps,dwc3";
1593 reg = <0x48910000 0x17000>;
1594 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1595 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1596 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1597 interrupt-names = "peripheral",
1600 maximum-speed = "high-speed";
1602 snps,dis_u3_susphy_quirk;
1603 snps,dis_u2_susphy_quirk;
1608 compatible = "ti,am3352-elm";
1609 reg = <0x48078000 0xfc0>; /* device IO registers */
1610 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1612 status = "disabled";
1615 gpmc: gpmc@50000000 {
1616 compatible = "ti,am3352-gpmc";
1618 reg = <0x50000000 0x37c>; /* device IO registers */
1619 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1620 dmas = <&edma_xbar 4 0>;
1623 gpmc,num-waitpins = <2>;
1624 #address-cells = <2>;
1626 interrupt-controller;
1627 #interrupt-cells = <2>;
1630 status = "disabled";
1634 compatible = "ti,dra7-atl";
1635 reg = <0x4843c000 0x3ff>;
1637 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1638 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1639 clocks = <&atl_gfclk_mux>;
1640 clock-names = "fck";
1641 status = "disabled";
1644 mcasp1: mcasp@48460000 {
1645 compatible = "ti,dra7-mcasp-audio";
1646 ti,hwmods = "mcasp1";
1647 reg = <0x48460000 0x2000>,
1648 <0x45800000 0x1000>;
1649 reg-names = "mpu","dat";
1650 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1652 interrupt-names = "tx", "rx";
1653 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1654 dma-names = "tx", "rx";
1655 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1656 <&mcasp1_ahclkr_mux>;
1657 clock-names = "fck", "ahclkx", "ahclkr";
1658 status = "disabled";
1661 mcasp2: mcasp@48464000 {
1662 compatible = "ti,dra7-mcasp-audio";
1663 ti,hwmods = "mcasp2";
1664 reg = <0x48464000 0x2000>,
1665 <0x45c00000 0x1000>;
1666 reg-names = "mpu","dat";
1667 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1668 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1669 interrupt-names = "tx", "rx";
1670 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1671 dma-names = "tx", "rx";
1672 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1673 <&mcasp2_ahclkr_mux>;
1674 clock-names = "fck", "ahclkx", "ahclkr";
1675 status = "disabled";
1678 mcasp3: mcasp@48468000 {
1679 compatible = "ti,dra7-mcasp-audio";
1680 ti,hwmods = "mcasp3";
1681 reg = <0x48468000 0x2000>,
1682 <0x46000000 0x1000>;
1683 reg-names = "mpu","dat";
1684 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1685 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1686 interrupt-names = "tx", "rx";
1687 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1688 dma-names = "tx", "rx";
1689 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1690 clock-names = "fck", "ahclkx";
1691 status = "disabled";
1694 mcasp4: mcasp@4846c000 {
1695 compatible = "ti,dra7-mcasp-audio";
1696 ti,hwmods = "mcasp4";
1697 reg = <0x4846c000 0x2000>,
1698 <0x48436000 0x1000>;
1699 reg-names = "mpu","dat";
1700 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1702 interrupt-names = "tx", "rx";
1703 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1704 dma-names = "tx", "rx";
1705 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1706 clock-names = "fck", "ahclkx";
1707 status = "disabled";
1710 mcasp5: mcasp@48470000 {
1711 compatible = "ti,dra7-mcasp-audio";
1712 ti,hwmods = "mcasp5";
1713 reg = <0x48470000 0x2000>,
1714 <0x4843a000 0x1000>;
1715 reg-names = "mpu","dat";
1716 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1717 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1718 interrupt-names = "tx", "rx";
1719 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1720 dma-names = "tx", "rx";
1721 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1722 clock-names = "fck", "ahclkx";
1723 status = "disabled";
1726 mcasp6: mcasp@48474000 {
1727 compatible = "ti,dra7-mcasp-audio";
1728 ti,hwmods = "mcasp6";
1729 reg = <0x48474000 0x2000>,
1730 <0x4844c000 0x1000>;
1731 reg-names = "mpu","dat";
1732 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1734 interrupt-names = "tx", "rx";
1735 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1736 dma-names = "tx", "rx";
1737 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1738 clock-names = "fck", "ahclkx";
1739 status = "disabled";
1742 mcasp7: mcasp@48478000 {
1743 compatible = "ti,dra7-mcasp-audio";
1744 ti,hwmods = "mcasp7";
1745 reg = <0x48478000 0x2000>,
1746 <0x48450000 0x1000>;
1747 reg-names = "mpu","dat";
1748 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1749 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1750 interrupt-names = "tx", "rx";
1751 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1752 dma-names = "tx", "rx";
1753 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1754 clock-names = "fck", "ahclkx";
1755 status = "disabled";
1758 mcasp8: mcasp@4847c000 {
1759 compatible = "ti,dra7-mcasp-audio";
1760 ti,hwmods = "mcasp8";
1761 reg = <0x4847c000 0x2000>,
1762 <0x48454000 0x1000>;
1763 reg-names = "mpu","dat";
1764 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1766 interrupt-names = "tx", "rx";
1767 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1768 dma-names = "tx", "rx";
1769 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1770 clock-names = "fck", "ahclkx";
1771 status = "disabled";
1774 crossbar_mpu: crossbar@4a002a48 {
1775 compatible = "ti,irq-crossbar";
1776 reg = <0x4a002a48 0x130>;
1777 interrupt-controller;
1778 interrupt-parent = <&wakeupgen>;
1779 #interrupt-cells = <3>;
1780 ti,max-irqs = <160>;
1781 ti,max-crossbar-sources = <MAX_SOURCES>;
1783 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1784 ti,irqs-skip = <10 133 139 140>;
1785 ti,irqs-safe-map = <0>;
1788 mac: ethernet@48484000 {
1789 compatible = "ti,dra7-cpsw","ti,cpsw";
1791 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1792 clock-names = "fck", "cpts";
1793 cpdma_channels = <8>;
1794 ale_entries = <1024>;
1795 bd_ram_size = <0x2000>;
1796 mac_control = <0x20>;
1799 cpts_clock_mult = <0x784CFE14>;
1800 cpts_clock_shift = <29>;
1801 reg = <0x48484000 0x1000
1803 #address-cells = <1>;
1807 * Do not allow gating of cpsw clock as workaround
1808 * for errata i877. Keeping internal clock disabled
1809 * causes the device switching characteristics
1810 * to degrade over time and eventually fail to meet
1811 * the data manual delay time/skew specs.
1821 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1826 syscon = <&scm_conf>;
1827 status = "disabled";
1829 davinci_mdio: mdio@48485000 {
1830 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1831 #address-cells = <1>;
1833 ti,hwmods = "davinci_mdio";
1834 bus_freq = <1000000>;
1835 reg = <0x48485000 0x100>;
1838 cpsw_emac0: slave@48480200 {
1839 /* Filled in by U-Boot */
1840 mac-address = [ 00 00 00 00 00 00 ];
1843 cpsw_emac1: slave@48480300 {
1844 /* Filled in by U-Boot */
1845 mac-address = [ 00 00 00 00 00 00 ];
1848 phy_sel: cpsw-phy-sel@4a002554 {
1849 compatible = "ti,dra7xx-cpsw-phy-sel";
1850 reg= <0x4a002554 0x4>;
1851 reg-names = "gmii-sel";
1855 dcan1: can@481cc000 {
1856 compatible = "ti,dra7-d_can";
1857 ti,hwmods = "dcan1";
1858 reg = <0x4ae3c000 0x2000>;
1859 syscon-raminit = <&scm_conf 0x558 0>;
1860 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1861 clocks = <&dcan1_sys_clk_mux>;
1862 status = "disabled";
1865 dcan2: can@481d0000 {
1866 compatible = "ti,dra7-d_can";
1867 ti,hwmods = "dcan2";
1868 reg = <0x48480000 0x2000>;
1869 syscon-raminit = <&scm_conf 0x558 1>;
1870 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1871 clocks = <&sys_clkin1>;
1872 status = "disabled";
1876 compatible = "ti,dra7-dss";
1877 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1878 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1879 status = "disabled";
1880 ti,hwmods = "dss_core";
1881 /* CTRL_CORE_DSS_PLL_CONTROL */
1882 syscon-pll-ctrl = <&scm_conf 0x538>;
1883 #address-cells = <1>;
1888 compatible = "ti,dra7-dispc";
1889 reg = <0x58001000 0x1000>;
1890 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1891 ti,hwmods = "dss_dispc";
1892 clocks = <&dss_dss_clk>;
1893 clock-names = "fck";
1894 /* CTRL_CORE_SMA_SW_1 */
1895 syscon-pol = <&scm_conf 0x534>;
1898 hdmi: encoder@58060000 {
1899 compatible = "ti,dra7-hdmi";
1900 reg = <0x58040000 0x200>,
1903 <0x58060000 0x19000>;
1904 reg-names = "wp", "pll", "phy", "core";
1905 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1906 status = "disabled";
1907 ti,hwmods = "dss_hdmi";
1908 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1909 clock-names = "fck", "sys_clk";
1913 epwmss0: epwmss@4843e000 {
1914 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1915 reg = <0x4843e000 0x30>;
1916 ti,hwmods = "epwmss0";
1917 #address-cells = <1>;
1919 status = "disabled";
1922 ehrpwm0: pwm@4843e200 {
1923 compatible = "ti,dra746-ehrpwm",
1926 reg = <0x4843e200 0x80>;
1927 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1928 clock-names = "tbclk", "fck";
1929 status = "disabled";
1932 ecap0: ecap@4843e100 {
1933 compatible = "ti,dra746-ecap",
1936 reg = <0x4843e100 0x80>;
1937 clocks = <&l4_root_clk_div>;
1938 clock-names = "fck";
1939 status = "disabled";
1943 epwmss1: epwmss@48440000 {
1944 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1945 reg = <0x48440000 0x30>;
1946 ti,hwmods = "epwmss1";
1947 #address-cells = <1>;
1949 status = "disabled";
1952 ehrpwm1: pwm@48440200 {
1953 compatible = "ti,dra746-ehrpwm",
1956 reg = <0x48440200 0x80>;
1957 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1958 clock-names = "tbclk", "fck";
1959 status = "disabled";
1962 ecap1: ecap@48440100 {
1963 compatible = "ti,dra746-ecap",
1966 reg = <0x48440100 0x80>;
1967 clocks = <&l4_root_clk_div>;
1968 clock-names = "fck";
1969 status = "disabled";
1973 epwmss2: epwmss@48442000 {
1974 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1975 reg = <0x48442000 0x30>;
1976 ti,hwmods = "epwmss2";
1977 #address-cells = <1>;
1979 status = "disabled";
1982 ehrpwm2: pwm@48442200 {
1983 compatible = "ti,dra746-ehrpwm",
1986 reg = <0x48442200 0x80>;
1987 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1988 clock-names = "tbclk", "fck";
1989 status = "disabled";
1992 ecap2: ecap@48442100 {
1993 compatible = "ti,dra746-ecap",
1996 reg = <0x48442100 0x80>;
1997 clocks = <&l4_root_clk_div>;
1998 clock-names = "fck";
1999 status = "disabled";
2003 aes1: aes@4b500000 {
2004 compatible = "ti,omap4-aes";
2006 reg = <0x4b500000 0xa0>;
2007 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2008 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
2009 dma-names = "tx", "rx";
2010 clocks = <&l3_iclk_div>;
2011 clock-names = "fck";
2014 aes2: aes@4b700000 {
2015 compatible = "ti,omap4-aes";
2017 reg = <0x4b700000 0xa0>;
2018 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2019 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
2020 dma-names = "tx", "rx";
2021 clocks = <&l3_iclk_div>;
2022 clock-names = "fck";
2026 compatible = "ti,omap4-des";
2028 reg = <0x480a5000 0xa0>;
2029 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2030 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2031 dma-names = "tx", "rx";
2032 clocks = <&l3_iclk_div>;
2033 clock-names = "fck";
2036 sham: sham@53100000 {
2037 compatible = "ti,omap5-sham";
2039 reg = <0x4b101000 0x300>;
2040 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2041 dmas = <&edma_xbar 119 0>;
2043 clocks = <&l3_iclk_div>;
2044 clock-names = "fck";
2048 compatible = "ti,omap4-rng";
2050 reg = <0x48090000 0x2000>;
2051 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2052 clocks = <&l3_iclk_div>;
2053 clock-names = "fck";
2057 thermal_zones: thermal-zones {
2058 #include "omap4-cpu-thermal.dtsi"
2059 #include "omap5-gpu-thermal.dtsi"
2060 #include "omap5-core-thermal.dtsi"
2061 #include "dra7-dspeve-thermal.dtsi"
2062 #include "dra7-iva-thermal.dtsi"
2068 polling-delay = <500>; /* milliseconds */
2069 coefficients = <0 2000>;
2073 coefficients = <0 2000>;
2077 coefficients = <0 2000>;
2081 coefficients = <0 2000>;
2085 coefficients = <0 2000>;
2089 temperature = <120000>; /* milli Celsius */
2092 /include/ "dra7xx-clocks.dtsi"