arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #define MAX_SOURCES 400
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         compatible = "ti,dra7xx";
  20         interrupt-parent = <&crossbar_mpu>;
  21         chosen { };
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35                 serial6 = &uart7;
  36                 serial7 = &uart8;
  37                 serial8 = &uart9;
  38                 serial9 = &uart10;
  39                 ethernet0 = &cpsw_emac0;
  40                 ethernet1 = &cpsw_emac1;
  41                 d_can0 = &dcan1;
  42                 d_can1 = &dcan2;
  43                 spi0 = &qspi;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&gic>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x0 0x48211000 0x0 0x1000>,
  60                       <0x0 0x48212000 0x0 0x2000>,
  61                       <0x0 0x48214000 0x0 0x2000>,
  62                       <0x0 0x48216000 0x0 0x2000>;
  63                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 interrupt-parent = <&gic>;
  65         };
  66
  67         wakeupgen: interrupt-controller@48281000 {
  68                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  69                 interrupt-controller;
  70                 #interrupt-cells = <3>;
  71                 reg = <0x0 0x48281000 0x0 0x1000>;
  72                 interrupt-parent = <&gic>;
  73         };
  74
  75         cpus {
  76                 #address-cells = <1>;
  77                 #size-cells = <0>;
  78
  79                 cpu0: cpu@0 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a15";
  82                         reg = <0>;
  83
  84                         operating-points-v2 = <&cpu0_opp_table>;
  85
  86                         clocks = <&dpll_mpu_ck>;
  87                         clock-names = "cpu";
  88
  89                         clock-latency = <300000>; /* From omap-cpufreq driver */
  90
  91                         /* cooling options */
  92                         cooling-min-level = <0>;
  93                         cooling-max-level = <2>;
  94                         #cooling-cells = <2>; /* min followed by max */
  95                 };
  96         };
  97
  98         cpu0_opp_table: opp-table {
  99                 compatible = "operating-points-v2-ti-cpu";
 100                 syscon = <&scm_wkup>;
 101
 102                 opp_nom-1000000000 {
 103                         opp-hz = /bits/ 64 <1000000000>;
 104                         opp-microvolt = <1060000 850000 1150000>;
 105                         opp-supported-hw = <0xFF 0x01>;
 106                         opp-suspend;
 107                 };
 108
 109                 opp_od-1176000000 {
 110                         opp-hz = /bits/ 64 <1176000000>;
 111                         opp-microvolt = <1160000 885000 1160000>;
 112                         opp-supported-hw = <0xFF 0x02>;
 113                 };
 114         };
 115
 116         /*
 117          * The soc node represents the soc top level view. It is used for IPs
 118          * that are not memory mapped in the MPU view or for the MPU itself.
 119          */
 120         soc {
 121                 compatible = "ti,omap-infra";
 122                 mpu {
 123                         compatible = "ti,omap5-mpu";
 124                         ti,hwmods = "mpu";
 125                 };
 126         };
 127
 128         /*
 129          * XXX: Use a flat representation of the SOC interconnect.
 130          * The real OMAP interconnect network is quite complex.
 131          * Since it will not bring real advantage to represent that in DT for
 132          * the moment, just use a fake OCP bus entry to represent the whole bus
 133          * hierarchy.
 134          */
 135         ocp {
 136                 compatible = "ti,dra7-l3-noc", "simple-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges = <0x0 0x0 0x0 0xc0000000>;
 140                 ti,hwmods = "l3_main_1", "l3_main_2";
 141                 reg = <0x0 0x44000000 0x0 0x1000000>,
 142                       <0x0 0x45000000 0x0 0x1000>;
 143                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 144                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 145
 146                 l4_cfg: l4@4a000000 {
 147                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 148                         #address-cells = <1>;
 149                         #size-cells = <1>;
 150                         ranges = <0 0x4a000000 0x22c000>;
 151
 152                         scm: scm@2000 {
 153                                 compatible = "ti,dra7-scm-core", "simple-bus";
 154                                 reg = <0x2000 0x2000>;
 155                                 #address-cells = <1>;
 156                                 #size-cells = <1>;
 157                                 ranges = <0 0x2000 0x2000>;
 158
 159                                 scm_conf: scm_conf@0 {
 160                                         compatible = "syscon", "simple-bus";
 161                                         reg = <0x0 0x1400>;
 162                                         #address-cells = <1>;
 163                                         #size-cells = <1>;
 164                                         ranges = <0 0x0 0x1400>;
 165
 166                                         pbias_regulator: pbias_regulator@e00 {
 167                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
 168                                                 reg = <0xe00 0x4>;
 169                                                 syscon = <&scm_conf>;
 170                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 171                                                         regulator-name = "pbias_mmc_omap5";
 172                                                         regulator-min-microvolt = <1800000>;
 173                                                         regulator-max-microvolt = <3000000>;
 174                                                 };
 175                                         };
 176
 177                                         scm_conf_clocks: clocks {
 178                                                 #address-cells = <1>;
 179                                                 #size-cells = <0>;
 180                                         };
 181                                 };
 182
 183                                 dra7_pmx_core: pinmux@1400 {
 184                                         compatible = "ti,dra7-padconf",
 185                                                      "pinctrl-single";
 186                                         reg = <0x1400 0x0468>;
 187                                         #address-cells = <1>;
 188                                         #size-cells = <0>;
 189                                         #pinctrl-cells = <1>;
 190                                         #interrupt-cells = <1>;
 191                                         interrupt-controller;
 192                                         pinctrl-single,register-width = <32>;
 193                                         pinctrl-single,function-mask = <0x3fffffff>;
 194                                 };
 195
 196                                 scm_conf1: scm_conf@1c04 {
 197                                         compatible = "syscon";
 198                                         reg = <0x1c04 0x0020>;
 199                                 };
 200
 201                                 scm_conf_pcie: scm_conf@1c24 {
 202                                         compatible = "syscon";
 203                                         reg = <0x1c24 0x0024>;
 204                                 };
 205
 206                                 sdma_xbar: dma-router@b78 {
 207                                         compatible = "ti,dra7-dma-crossbar";
 208                                         reg = <0xb78 0xfc>;
 209                                         #dma-cells = <1>;
 210                                         dma-requests = <205>;
 211                                         ti,dma-safe-map = <0>;
 212                                         dma-masters = <&sdma>;
 213                                 };
 214
 215                                 edma_xbar: dma-router@c78 {
 216                                         compatible = "ti,dra7-dma-crossbar";
 217                                         reg = <0xc78 0x7c>;
 218                                         #dma-cells = <2>;
 219                                         dma-requests = <204>;
 220                                         ti,dma-safe-map = <0>;
 221                                         dma-masters = <&edma>;
 222                                 };
 223                         };
 224
 225                         cm_core_aon: cm_core_aon@5000 {
 226                                 compatible = "ti,dra7-cm-core-aon";
 227                                 reg = <0x5000 0x2000>;
 228
 229                                 cm_core_aon_clocks: clocks {
 230                                         #address-cells = <1>;
 231                                         #size-cells = <0>;
 232                                 };
 233
 234                                 cm_core_aon_clockdomains: clockdomains {
 235                                 };
 236                         };
 237
 238                         cm_core: cm_core@8000 {
 239                                 compatible = "ti,dra7-cm-core";
 240                                 reg = <0x8000 0x3000>;
 241
 242                                 cm_core_clocks: clocks {
 243                                         #address-cells = <1>;
 244                                         #size-cells = <0>;
 245                                 };
 246
 247                                 cm_core_clockdomains: clockdomains {
 248                                 };
 249                         };
 250                 };
 251
 252                 l4_wkup: l4@4ae00000 {
 253                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 254                         #address-cells = <1>;
 255                         #size-cells = <1>;
 256                         ranges = <0 0x4ae00000 0x3f000>;
 257
 258                         counter32k: counter@4000 {
 259                                 compatible = "ti,omap-counter32k";
 260                                 reg = <0x4000 0x40>;
 261                                 ti,hwmods = "counter_32k";
 262                         };
 263
 264                         prm: prm@6000 {
 265                                 compatible = "ti,dra7-prm";
 266                                 reg = <0x6000 0x3000>;
 267                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 268
 269                                 prm_clocks: clocks {
 270                                         #address-cells = <1>;
 271                                         #size-cells = <0>;
 272                                 };
 273
 274                                 prm_clockdomains: clockdomains {
 275                                 };
 276                         };
 277
 278                         scm_wkup: scm_conf@c000 {
 279                                 compatible = "syscon";
 280                                 reg = <0xc000 0x1000>;
 281                         };
 282                 };
 283
 284                 axi@0 {
 285                         compatible = "simple-bus";
 286                         #size-cells = <1>;
 287                         #address-cells = <1>;
 288                         ranges = <0x51000000 0x51000000 0x3000
 289                                   0x0        0x20000000 0x10000000>;
 290                         pcie1: pcie@51000000 {
 291                                 compatible = "ti,dra7-pcie";
 292                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 293                                 reg-names = "rc_dbics", "ti_conf", "config";
 294                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 295                                 #address-cells = <3>;
 296                                 #size-cells = <2>;
 297                                 device_type = "pci";
 298                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 299                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 300                                 bus-range = <0x00 0xff>;
 301                                 #interrupt-cells = <1>;
 302                                 num-lanes = <1>;
 303                                 linux,pci-domain = <0>;
 304                                 ti,hwmods = "pcie1";
 305                                 phys = <&pcie1_phy>;
 306                                 phy-names = "pcie-phy0";
 307                                 interrupt-map-mask = <0 0 0 7>;
 308                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 309                                                 <0 0 0 2 &pcie1_intc 2>,
 310                                                 <0 0 0 3 &pcie1_intc 3>,
 311                                                 <0 0 0 4 &pcie1_intc 4>;
 312                                 pcie1_intc: interrupt-controller {
 313                                         interrupt-controller;
 314                                         #address-cells = <0>;
 315                                         #interrupt-cells = <1>;
 316                                 };
 317                         };
 318                 };
 319
 320                 axi@1 {
 321                         compatible = "simple-bus";
 322                         #size-cells = <1>;
 323                         #address-cells = <1>;
 324                         ranges = <0x51800000 0x51800000 0x3000
 325                                   0x0        0x30000000 0x10000000>;
 326                         status = "disabled";
 327                         pcie@51800000 {
 328                                 compatible = "ti,dra7-pcie";
 329                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 330                                 reg-names = "rc_dbics", "ti_conf", "config";
 331                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 332                                 #address-cells = <3>;
 333                                 #size-cells = <2>;
 334                                 device_type = "pci";
 335                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 336                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 337                                 bus-range = <0x00 0xff>;
 338                                 #interrupt-cells = <1>;
 339                                 num-lanes = <1>;
 340                                 linux,pci-domain = <1>;
 341                                 ti,hwmods = "pcie2";
 342                                 phys = <&pcie2_phy>;
 343                                 phy-names = "pcie-phy0";
 344                                 interrupt-map-mask = <0 0 0 7>;
 345                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 346                                                 <0 0 0 2 &pcie2_intc 2>,
 347                                                 <0 0 0 3 &pcie2_intc 3>,
 348                                                 <0 0 0 4 &pcie2_intc 4>;
 349                                 pcie2_intc: interrupt-controller {
 350                                         interrupt-controller;
 351                                         #address-cells = <0>;
 352                                         #interrupt-cells = <1>;
 353                                 };
 354                         };
 355                 };
 356
 357                 ocmcram1: ocmcram@40300000 {
 358                         compatible = "mmio-sram";
 359                         reg = <0x40300000 0x80000>;
 360                         ranges = <0x0 0x40300000 0x80000>;
 361                         #address-cells = <1>;
 362                         #size-cells = <1>;
 363                         /*
 364                          * This is a placeholder for an optional reserved
 365                          * region for use by secure software. The size
 366                          * of this region is not known until runtime so it
 367                          * is set as zero to either be updated to reserve
 368                          * space or left unchanged to leave all SRAM for use.
 369                          * On HS parts that that require the reserved region
 370                          * either the bootloader can update the size to
 371                          * the required amount or the node can be overridden
 372                          * from the board dts file for the secure platform.
 373                          */
 374                         sram-hs@0 {
 375                                 compatible = "ti,secure-ram";
 376                                 reg = <0x0 0x0>;
 377                         };
 378                 };
 379
 380                 /*
 381                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 382                  * DRA7xx and AM57xx variants. Confirm availability in
 383                  * the data manual for the exact part number in use
 384                  * before enabling these nodes in the board dts file.
 385                  */
 386                 ocmcram2: ocmcram@40400000 {
 387                         status = "disabled";
 388                         compatible = "mmio-sram";
 389                         reg = <0x40400000 0x100000>;
 390                         ranges = <0x0 0x40400000 0x100000>;
 391                         #address-cells = <1>;
 392                         #size-cells = <1>;
 393                 };
 394
 395                 ocmcram3: ocmcram@40500000 {
 396                         status = "disabled";
 397                         compatible = "mmio-sram";
 398                         reg = <0x40500000 0x100000>;
 399                         ranges = <0x0 0x40500000 0x100000>;
 400                         #address-cells = <1>;
 401                         #size-cells = <1>;
 402                 };
 403
 404                 bandgap: bandgap@4a0021e0 {
 405                         reg = <0x4a0021e0 0xc
 406                                 0x4a00232c 0xc
 407                                 0x4a002380 0x2c
 408                                 0x4a0023C0 0x3c
 409                                 0x4a002564 0x8
 410                                 0x4a002574 0x50>;
 411                                 compatible = "ti,dra752-bandgap";
 412                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 413                                 #thermal-sensor-cells = <1>;
 414                 };
 415
 416                 dsp1_system: dsp_system@40d00000 {
 417                         compatible = "syscon";
 418                         reg = <0x40d00000 0x100>;
 419                 };
 420
 421                 sdma: dma-controller@4a056000 {
 422                         compatible = "ti,omap4430-sdma";
 423                         reg = <0x4a056000 0x1000>;
 424                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 425                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 426                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 427                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 428                         #dma-cells = <1>;
 429                         dma-channels = <32>;
 430                         dma-requests = <127>;
 431                 };
 432
 433                 edma: edma@43300000 {
 434                         compatible = "ti,edma3-tpcc";
 435                         ti,hwmods = "tpcc";
 436                         reg = <0x43300000 0x100000>;
 437                         reg-names = "edma3_cc";
 438                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 439                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 440                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 441                         interrupt-names = "edma3_ccint", "edma3_mperr",
 442                                           "edma3_ccerrint";
 443                         dma-requests = <64>;
 444                         #dma-cells = <2>;
 445
 446                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 447
 448                         /*
 449                          * memcpy is disabled, can be enabled with:
 450                          * ti,edma-memcpy-channels = <20 21>;
 451                          * for example. Note that these channels need to be
 452                          * masked in the xbar as well.
 453                          */
 454                 };
 455
 456                 edma_tptc0: tptc@43400000 {
 457                         compatible = "ti,edma3-tptc";
 458                         ti,hwmods = "tptc0";
 459                         reg =   <0x43400000 0x100000>;
 460                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 461                         interrupt-names = "edma3_tcerrint";
 462                 };
 463
 464                 edma_tptc1: tptc@43500000 {
 465                         compatible = "ti,edma3-tptc";
 466                         ti,hwmods = "tptc1";
 467                         reg =   <0x43500000 0x100000>;
 468                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 469                         interrupt-names = "edma3_tcerrint";
 470                 };
 471
 472                 gpio1: gpio@4ae10000 {
 473                         compatible = "ti,omap4-gpio";
 474                         reg = <0x4ae10000 0x200>;
 475                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 476                         ti,hwmods = "gpio1";
 477                         gpio-controller;
 478                         #gpio-cells = <2>;
 479                         interrupt-controller;
 480                         #interrupt-cells = <2>;
 481                 };
 482
 483                 gpio2: gpio@48055000 {
 484                         compatible = "ti,omap4-gpio";
 485                         reg = <0x48055000 0x200>;
 486                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 487                         ti,hwmods = "gpio2";
 488                         gpio-controller;
 489                         #gpio-cells = <2>;
 490                         interrupt-controller;
 491                         #interrupt-cells = <2>;
 492                 };
 493
 494                 gpio3: gpio@48057000 {
 495                         compatible = "ti,omap4-gpio";
 496                         reg = <0x48057000 0x200>;
 497                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 498                         ti,hwmods = "gpio3";
 499                         gpio-controller;
 500                         #gpio-cells = <2>;
 501                         interrupt-controller;
 502                         #interrupt-cells = <2>;
 503                 };
 504
 505                 gpio4: gpio@48059000 {
 506                         compatible = "ti,omap4-gpio";
 507                         reg = <0x48059000 0x200>;
 508                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 509                         ti,hwmods = "gpio4";
 510                         gpio-controller;
 511                         #gpio-cells = <2>;
 512                         interrupt-controller;
 513                         #interrupt-cells = <2>;
 514                 };
 515
 516                 gpio5: gpio@4805b000 {
 517                         compatible = "ti,omap4-gpio";
 518                         reg = <0x4805b000 0x200>;
 519                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "gpio5";
 521                         gpio-controller;
 522                         #gpio-cells = <2>;
 523                         interrupt-controller;
 524                         #interrupt-cells = <2>;
 525                 };
 526
 527                 gpio6: gpio@4805d000 {
 528                         compatible = "ti,omap4-gpio";
 529                         reg = <0x4805d000 0x200>;
 530                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 531                         ti,hwmods = "gpio6";
 532                         gpio-controller;
 533                         #gpio-cells = <2>;
 534                         interrupt-controller;
 535                         #interrupt-cells = <2>;
 536                 };
 537
 538                 gpio7: gpio@48051000 {
 539                         compatible = "ti,omap4-gpio";
 540                         reg = <0x48051000 0x200>;
 541                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 542                         ti,hwmods = "gpio7";
 543                         gpio-controller;
 544                         #gpio-cells = <2>;
 545                         interrupt-controller;
 546                         #interrupt-cells = <2>;
 547                 };
 548
 549                 gpio8: gpio@48053000 {
 550                         compatible = "ti,omap4-gpio";
 551                         reg = <0x48053000 0x200>;
 552                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 553                         ti,hwmods = "gpio8";
 554                         gpio-controller;
 555                         #gpio-cells = <2>;
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                 };
 559
 560                 uart1: serial@4806a000 {
 561                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 562                         reg = <0x4806a000 0x100>;
 563                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 564                         ti,hwmods = "uart1";
 565                         clock-frequency = <48000000>;
 566                         status = "disabled";
 567                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 568                         dma-names = "tx", "rx";
 569                 };
 570
 571                 uart2: serial@4806c000 {
 572                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 573                         reg = <0x4806c000 0x100>;
 574                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 575                         ti,hwmods = "uart2";
 576                         clock-frequency = <48000000>;
 577                         status = "disabled";
 578                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 579                         dma-names = "tx", "rx";
 580                 };
 581
 582                 uart3: serial@48020000 {
 583                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 584                         reg = <0x48020000 0x100>;
 585                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 586                         ti,hwmods = "uart3";
 587                         clock-frequency = <48000000>;
 588                         status = "disabled";
 589                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 590                         dma-names = "tx", "rx";
 591                 };
 592
 593                 uart4: serial@4806e000 {
 594                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 595                         reg = <0x4806e000 0x100>;
 596                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 597                         ti,hwmods = "uart4";
 598                         clock-frequency = <48000000>;
 599                         status = "disabled";
 600                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 601                         dma-names = "tx", "rx";
 602                 };
 603
 604                 uart5: serial@48066000 {
 605                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 606                         reg = <0x48066000 0x100>;
 607                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 608                         ti,hwmods = "uart5";
 609                         clock-frequency = <48000000>;
 610                         status = "disabled";
 611                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 612                         dma-names = "tx", "rx";
 613                 };
 614
 615                 uart6: serial@48068000 {
 616                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 617                         reg = <0x48068000 0x100>;
 618                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 619                         ti,hwmods = "uart6";
 620                         clock-frequency = <48000000>;
 621                         status = "disabled";
 622                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 623                         dma-names = "tx", "rx";
 624                 };
 625
 626                 uart7: serial@48420000 {
 627                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 628                         reg = <0x48420000 0x100>;
 629                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 630                         ti,hwmods = "uart7";
 631                         clock-frequency = <48000000>;
 632                         status = "disabled";
 633                 };
 634
 635                 uart8: serial@48422000 {
 636                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 637                         reg = <0x48422000 0x100>;
 638                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 639                         ti,hwmods = "uart8";
 640                         clock-frequency = <48000000>;
 641                         status = "disabled";
 642                 };
 643
 644                 uart9: serial@48424000 {
 645                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 646                         reg = <0x48424000 0x100>;
 647                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 648                         ti,hwmods = "uart9";
 649                         clock-frequency = <48000000>;
 650                         status = "disabled";
 651                 };
 652
 653                 uart10: serial@4ae2b000 {
 654                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 655                         reg = <0x4ae2b000 0x100>;
 656                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 657                         ti,hwmods = "uart10";
 658                         clock-frequency = <48000000>;
 659                         status = "disabled";
 660                 };
 661
 662                 mailbox1: mailbox@4a0f4000 {
 663                         compatible = "ti,omap4-mailbox";
 664                         reg = <0x4a0f4000 0x200>;
 665                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 666                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 667                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 668                         ti,hwmods = "mailbox1";
 669                         #mbox-cells = <1>;
 670                         ti,mbox-num-users = <3>;
 671                         ti,mbox-num-fifos = <8>;
 672                         status = "disabled";
 673                 };
 674
 675                 mailbox2: mailbox@4883a000 {
 676                         compatible = "ti,omap4-mailbox";
 677                         reg = <0x4883a000 0x200>;
 678                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 682                         ti,hwmods = "mailbox2";
 683                         #mbox-cells = <1>;
 684                         ti,mbox-num-users = <4>;
 685                         ti,mbox-num-fifos = <12>;
 686                         status = "disabled";
 687                 };
 688
 689                 mailbox3: mailbox@4883c000 {
 690                         compatible = "ti,omap4-mailbox";
 691                         reg = <0x4883c000 0x200>;
 692                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 696                         ti,hwmods = "mailbox3";
 697                         #mbox-cells = <1>;
 698                         ti,mbox-num-users = <4>;
 699                         ti,mbox-num-fifos = <12>;
 700                         status = "disabled";
 701                 };
 702
 703                 mailbox4: mailbox@4883e000 {
 704                         compatible = "ti,omap4-mailbox";
 705                         reg = <0x4883e000 0x200>;
 706                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 710                         ti,hwmods = "mailbox4";
 711                         #mbox-cells = <1>;
 712                         ti,mbox-num-users = <4>;
 713                         ti,mbox-num-fifos = <12>;
 714                         status = "disabled";
 715                 };
 716
 717                 mailbox5: mailbox@48840000 {
 718                         compatible = "ti,omap4-mailbox";
 719                         reg = <0x48840000 0x200>;
 720                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 721                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 722                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 723                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 724                         ti,hwmods = "mailbox5";
 725                         #mbox-cells = <1>;
 726                         ti,mbox-num-users = <4>;
 727                         ti,mbox-num-fifos = <12>;
 728                         status = "disabled";
 729                 };
 730
 731                 mailbox6: mailbox@48842000 {
 732                         compatible = "ti,omap4-mailbox";
 733                         reg = <0x48842000 0x200>;
 734                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 738                         ti,hwmods = "mailbox6";
 739                         #mbox-cells = <1>;
 740                         ti,mbox-num-users = <4>;
 741                         ti,mbox-num-fifos = <12>;
 742                         status = "disabled";
 743                 };
 744
 745                 mailbox7: mailbox@48844000 {
 746                         compatible = "ti,omap4-mailbox";
 747                         reg = <0x48844000 0x200>;
 748                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 752                         ti,hwmods = "mailbox7";
 753                         #mbox-cells = <1>;
 754                         ti,mbox-num-users = <4>;
 755                         ti,mbox-num-fifos = <12>;
 756                         status = "disabled";
 757                 };
 758
 759                 mailbox8: mailbox@48846000 {
 760                         compatible = "ti,omap4-mailbox";
 761                         reg = <0x48846000 0x200>;
 762                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 763                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 764                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 765                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 766                         ti,hwmods = "mailbox8";
 767                         #mbox-cells = <1>;
 768                         ti,mbox-num-users = <4>;
 769                         ti,mbox-num-fifos = <12>;
 770                         status = "disabled";
 771                 };
 772
 773                 mailbox9: mailbox@4885e000 {
 774                         compatible = "ti,omap4-mailbox";
 775                         reg = <0x4885e000 0x200>;
 776                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 777                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 778                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 779                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 780                         ti,hwmods = "mailbox9";
 781                         #mbox-cells = <1>;
 782                         ti,mbox-num-users = <4>;
 783                         ti,mbox-num-fifos = <12>;
 784                         status = "disabled";
 785                 };
 786
 787                 mailbox10: mailbox@48860000 {
 788                         compatible = "ti,omap4-mailbox";
 789                         reg = <0x48860000 0x200>;
 790                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 791                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 792                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 793                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 794                         ti,hwmods = "mailbox10";
 795                         #mbox-cells = <1>;
 796                         ti,mbox-num-users = <4>;
 797                         ti,mbox-num-fifos = <12>;
 798                         status = "disabled";
 799                 };
 800
 801                 mailbox11: mailbox@48862000 {
 802                         compatible = "ti,omap4-mailbox";
 803                         reg = <0x48862000 0x200>;
 804                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 805                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 806                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 807                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 808                         ti,hwmods = "mailbox11";
 809                         #mbox-cells = <1>;
 810                         ti,mbox-num-users = <4>;
 811                         ti,mbox-num-fifos = <12>;
 812                         status = "disabled";
 813                 };
 814
 815                 mailbox12: mailbox@48864000 {
 816                         compatible = "ti,omap4-mailbox";
 817                         reg = <0x48864000 0x200>;
 818                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 819                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 820                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 821                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 822                         ti,hwmods = "mailbox12";
 823                         #mbox-cells = <1>;
 824                         ti,mbox-num-users = <4>;
 825                         ti,mbox-num-fifos = <12>;
 826                         status = "disabled";
 827                 };
 828
 829                 mailbox13: mailbox@48802000 {
 830                         compatible = "ti,omap4-mailbox";
 831                         reg = <0x48802000 0x200>;
 832                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 833                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 834                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 835                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 836                         ti,hwmods = "mailbox13";
 837                         #mbox-cells = <1>;
 838                         ti,mbox-num-users = <4>;
 839                         ti,mbox-num-fifos = <12>;
 840                         status = "disabled";
 841                 };
 842
 843                 timer1: timer@4ae18000 {
 844                         compatible = "ti,omap5430-timer";
 845                         reg = <0x4ae18000 0x80>;
 846                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 847                         ti,hwmods = "timer1";
 848                         ti,timer-alwon;
 849                 };
 850
 851                 timer2: timer@48032000 {
 852                         compatible = "ti,omap5430-timer";
 853                         reg = <0x48032000 0x80>;
 854                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 855                         ti,hwmods = "timer2";
 856                 };
 857
 858                 timer3: timer@48034000 {
 859                         compatible = "ti,omap5430-timer";
 860                         reg = <0x48034000 0x80>;
 861                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 862                         ti,hwmods = "timer3";
 863                 };
 864
 865                 timer4: timer@48036000 {
 866                         compatible = "ti,omap5430-timer";
 867                         reg = <0x48036000 0x80>;
 868                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 869                         ti,hwmods = "timer4";
 870                 };
 871
 872                 timer5: timer@48820000 {
 873                         compatible = "ti,omap5430-timer";
 874                         reg = <0x48820000 0x80>;
 875                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 876                         ti,hwmods = "timer5";
 877                 };
 878
 879                 timer6: timer@48822000 {
 880                         compatible = "ti,omap5430-timer";
 881                         reg = <0x48822000 0x80>;
 882                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 883                         ti,hwmods = "timer6";
 884                 };
 885
 886                 timer7: timer@48824000 {
 887                         compatible = "ti,omap5430-timer";
 888                         reg = <0x48824000 0x80>;
 889                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 890                         ti,hwmods = "timer7";
 891                 };
 892
 893                 timer8: timer@48826000 {
 894                         compatible = "ti,omap5430-timer";
 895                         reg = <0x48826000 0x80>;
 896                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 897                         ti,hwmods = "timer8";
 898                 };
 899
 900                 timer9: timer@4803e000 {
 901                         compatible = "ti,omap5430-timer";
 902                         reg = <0x4803e000 0x80>;
 903                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 904                         ti,hwmods = "timer9";
 905                 };
 906
 907                 timer10: timer@48086000 {
 908                         compatible = "ti,omap5430-timer";
 909                         reg = <0x48086000 0x80>;
 910                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 911                         ti,hwmods = "timer10";
 912                 };
 913
 914                 timer11: timer@48088000 {
 915                         compatible = "ti,omap5430-timer";
 916                         reg = <0x48088000 0x80>;
 917                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 918                         ti,hwmods = "timer11";
 919                 };
 920
 921                 timer12: timer@4ae20000 {
 922                         compatible = "ti,omap5430-timer";
 923                         reg = <0x4ae20000 0x80>;
 924                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 925                         ti,hwmods = "timer12";
 926                         ti,timer-alwon;
 927                         ti,timer-secure;
 928                 };
 929
 930                 timer13: timer@48828000 {
 931                         compatible = "ti,omap5430-timer";
 932                         reg = <0x48828000 0x80>;
 933                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 934                         ti,hwmods = "timer13";
 935                 };
 936
 937                 timer14: timer@4882a000 {
 938                         compatible = "ti,omap5430-timer";
 939                         reg = <0x4882a000 0x80>;
 940                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 941                         ti,hwmods = "timer14";
 942                 };
 943
 944                 timer15: timer@4882c000 {
 945                         compatible = "ti,omap5430-timer";
 946                         reg = <0x4882c000 0x80>;
 947                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 948                         ti,hwmods = "timer15";
 949                 };
 950
 951                 timer16: timer@4882e000 {
 952                         compatible = "ti,omap5430-timer";
 953                         reg = <0x4882e000 0x80>;
 954                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 955                         ti,hwmods = "timer16";
 956                 };
 957
 958                 wdt2: wdt@4ae14000 {
 959                         compatible = "ti,omap3-wdt";
 960                         reg = <0x4ae14000 0x80>;
 961                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 962                         ti,hwmods = "wd_timer2";
 963                 };
 964
 965                 hwspinlock: spinlock@4a0f6000 {
 966                         compatible = "ti,omap4-hwspinlock";
 967                         reg = <0x4a0f6000 0x1000>;
 968                         ti,hwmods = "spinlock";
 969                         #hwlock-cells = <1>;
 970                 };
 971
 972                 dmm@4e000000 {
 973                         compatible = "ti,omap5-dmm";
 974                         reg = <0x4e000000 0x800>;
 975                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 976                         ti,hwmods = "dmm";
 977                 };
 978
 979                 i2c1: i2c@48070000 {
 980                         compatible = "ti,omap4-i2c";
 981                         reg = <0x48070000 0x100>;
 982                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 983                         #address-cells = <1>;
 984                         #size-cells = <0>;
 985                         ti,hwmods = "i2c1";
 986                         status = "disabled";
 987                 };
 988
 989                 i2c2: i2c@48072000 {
 990                         compatible = "ti,omap4-i2c";
 991                         reg = <0x48072000 0x100>;
 992                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 993                         #address-cells = <1>;
 994                         #size-cells = <0>;
 995                         ti,hwmods = "i2c2";
 996                         status = "disabled";
 997                 };
 998
 999                 i2c3: i2c@48060000 {
1000                         compatible = "ti,omap4-i2c";
1001                         reg = <0x48060000 0x100>;
1002                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1003                         #address-cells = <1>;
1004                         #size-cells = <0>;
1005                         ti,hwmods = "i2c3";
1006                         status = "disabled";
1007                 };
1008
1009                 i2c4: i2c@4807a000 {
1010                         compatible = "ti,omap4-i2c";
1011                         reg = <0x4807a000 0x100>;
1012                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1013                         #address-cells = <1>;
1014                         #size-cells = <0>;
1015                         ti,hwmods = "i2c4";
1016                         status = "disabled";
1017                 };
1018
1019                 i2c5: i2c@4807c000 {
1020                         compatible = "ti,omap4-i2c";
1021                         reg = <0x4807c000 0x100>;
1022                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1023                         #address-cells = <1>;
1024                         #size-cells = <0>;
1025                         ti,hwmods = "i2c5";
1026                         status = "disabled";
1027                 };
1028
1029                 mmc1: mmc@4809c000 {
1030                         compatible = "ti,omap4-hsmmc";
1031                         reg = <0x4809c000 0x400>;
1032                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1033                         ti,hwmods = "mmc1";
1034                         ti,dual-volt;
1035                         ti,needs-special-reset;
1036                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1037                         dma-names = "tx", "rx";
1038                         status = "disabled";
1039                         pbias-supply = <&pbias_mmc_reg>;
1040                         max-frequency = <192000000>;
1041                 };
1042
1043                 mmc2: mmc@480b4000 {
1044                         compatible = "ti,omap4-hsmmc";
1045                         reg = <0x480b4000 0x400>;
1046                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1047                         ti,hwmods = "mmc2";
1048                         ti,needs-special-reset;
1049                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1050                         dma-names = "tx", "rx";
1051                         status = "disabled";
1052                         max-frequency = <192000000>;
1053                 };
1054
1055                 mmc3: mmc@480ad000 {
1056                         compatible = "ti,omap4-hsmmc";
1057                         reg = <0x480ad000 0x400>;
1058                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1059                         ti,hwmods = "mmc3";
1060                         ti,needs-special-reset;
1061                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1062                         dma-names = "tx", "rx";
1063                         status = "disabled";
1064                         /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1065                         max-frequency = <64000000>;
1066                 };
1067
1068                 mmc4: mmc@480d1000 {
1069                         compatible = "ti,omap4-hsmmc";
1070                         reg = <0x480d1000 0x400>;
1071                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1072                         ti,hwmods = "mmc4";
1073                         ti,needs-special-reset;
1074                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1075                         dma-names = "tx", "rx";
1076                         status = "disabled";
1077                         max-frequency = <192000000>;
1078                 };
1079
1080                 mmu0_dsp1: mmu@40d01000 {
1081                         compatible = "ti,dra7-dsp-iommu";
1082                         reg = <0x40d01000 0x100>;
1083                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1084                         ti,hwmods = "mmu0_dsp1";
1085                         #iommu-cells = <0>;
1086                         ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1087                         status = "disabled";
1088                 };
1089
1090                 mmu1_dsp1: mmu@40d02000 {
1091                         compatible = "ti,dra7-dsp-iommu";
1092                         reg = <0x40d02000 0x100>;
1093                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1094                         ti,hwmods = "mmu1_dsp1";
1095                         #iommu-cells = <0>;
1096                         ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1097                         status = "disabled";
1098                 };
1099
1100                 mmu_ipu1: mmu@58882000 {
1101                         compatible = "ti,dra7-iommu";
1102                         reg = <0x58882000 0x100>;
1103                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1104                         ti,hwmods = "mmu_ipu1";
1105                         #iommu-cells = <0>;
1106                         ti,iommu-bus-err-back;
1107                         status = "disabled";
1108                 };
1109
1110                 mmu_ipu2: mmu@55082000 {
1111                         compatible = "ti,dra7-iommu";
1112                         reg = <0x55082000 0x100>;
1113                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1114                         ti,hwmods = "mmu_ipu2";
1115                         #iommu-cells = <0>;
1116                         ti,iommu-bus-err-back;
1117                         status = "disabled";
1118                 };
1119
1120                 abb_mpu: regulator-abb-mpu {
1121                         compatible = "ti,abb-v3";
1122                         regulator-name = "abb_mpu";
1123                         #address-cells = <0>;
1124                         #size-cells = <0>;
1125                         clocks = <&sys_clkin1>;
1126                         ti,settling-time = <50>;
1127                         ti,clock-cycles = <16>;
1128
1129                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1130                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1131                               <0x4ae0c158 0x4>;
1132                         reg-names = "setup-address", "control-address",
1133                                     "int-address", "efuse-address",
1134                                     "ldo-address";
1135                         ti,tranxdone-status-mask = <0x80>;
1136                         /* LDOVBBMPU_FBB_MUX_CTRL */
1137                         ti,ldovbb-override-mask = <0x400>;
1138                         /* LDOVBBMPU_FBB_VSET_OUT */
1139                         ti,ldovbb-vset-mask = <0x1F>;
1140
1141                         /*
1142                          * NOTE: only FBB mode used but actual vset will
1143                          * determine final biasing
1144                          */
1145                         ti,abb_info = <
1146                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1147                         1060000         0       0x0     0 0x02000000 0x01F00000
1148                         1160000         0       0x4     0 0x02000000 0x01F00000
1149                         1210000         0       0x8     0 0x02000000 0x01F00000
1150                         >;
1151                 };
1152
1153                 abb_ivahd: regulator-abb-ivahd {
1154                         compatible = "ti,abb-v3";
1155                         regulator-name = "abb_ivahd";
1156                         #address-cells = <0>;
1157                         #size-cells = <0>;
1158                         clocks = <&sys_clkin1>;
1159                         ti,settling-time = <50>;
1160                         ti,clock-cycles = <16>;
1161
1162                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1163                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1164                               <0x4a002470 0x4>;
1165                         reg-names = "setup-address", "control-address",
1166                                     "int-address", "efuse-address",
1167                                     "ldo-address";
1168                         ti,tranxdone-status-mask = <0x40000000>;
1169                         /* LDOVBBIVA_FBB_MUX_CTRL */
1170                         ti,ldovbb-override-mask = <0x400>;
1171                         /* LDOVBBIVA_FBB_VSET_OUT */
1172                         ti,ldovbb-vset-mask = <0x1F>;
1173
1174                         /*
1175                          * NOTE: only FBB mode used but actual vset will
1176                          * determine final biasing
1177                          */
1178                         ti,abb_info = <
1179                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1180                         1055000         0       0x0     0 0x02000000 0x01F00000
1181                         1150000         0       0x4     0 0x02000000 0x01F00000
1182                         1250000         0       0x8     0 0x02000000 0x01F00000
1183                         >;
1184                 };
1185
1186                 abb_dspeve: regulator-abb-dspeve {
1187                         compatible = "ti,abb-v3";
1188                         regulator-name = "abb_dspeve";
1189                         #address-cells = <0>;
1190                         #size-cells = <0>;
1191                         clocks = <&sys_clkin1>;
1192                         ti,settling-time = <50>;
1193                         ti,clock-cycles = <16>;
1194
1195                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1196                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1197                               <0x4a00246c 0x4>;
1198                         reg-names = "setup-address", "control-address",
1199                                     "int-address", "efuse-address",
1200                                     "ldo-address";
1201                         ti,tranxdone-status-mask = <0x20000000>;
1202                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1203                         ti,ldovbb-override-mask = <0x400>;
1204                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1205                         ti,ldovbb-vset-mask = <0x1F>;
1206
1207                         /*
1208                          * NOTE: only FBB mode used but actual vset will
1209                          * determine final biasing
1210                          */
1211                         ti,abb_info = <
1212                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1213                         1055000         0       0x0     0 0x02000000 0x01F00000
1214                         1150000         0       0x4     0 0x02000000 0x01F00000
1215                         1250000         0       0x8     0 0x02000000 0x01F00000
1216                         >;
1217                 };
1218
1219                 abb_gpu: regulator-abb-gpu {
1220                         compatible = "ti,abb-v3";
1221                         regulator-name = "abb_gpu";
1222                         #address-cells = <0>;
1223                         #size-cells = <0>;
1224                         clocks = <&sys_clkin1>;
1225                         ti,settling-time = <50>;
1226                         ti,clock-cycles = <16>;
1227
1228                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1229                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1230                               <0x4ae0c154 0x4>;
1231                         reg-names = "setup-address", "control-address",
1232                                     "int-address", "efuse-address",
1233                                     "ldo-address";
1234                         ti,tranxdone-status-mask = <0x10000000>;
1235                         /* LDOVBBGPU_FBB_MUX_CTRL */
1236                         ti,ldovbb-override-mask = <0x400>;
1237                         /* LDOVBBGPU_FBB_VSET_OUT */
1238                         ti,ldovbb-vset-mask = <0x1F>;
1239
1240                         /*
1241                          * NOTE: only FBB mode used but actual vset will
1242                          * determine final biasing
1243                          */
1244                         ti,abb_info = <
1245                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1246                         1090000         0       0x0     0 0x02000000 0x01F00000
1247                         1210000         0       0x4     0 0x02000000 0x01F00000
1248                         1280000         0       0x8     0 0x02000000 0x01F00000
1249                         >;
1250                 };
1251
1252                 mcspi1: spi@48098000 {
1253                         compatible = "ti,omap4-mcspi";
1254                         reg = <0x48098000 0x200>;
1255                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1256                         #address-cells = <1>;
1257                         #size-cells = <0>;
1258                         ti,hwmods = "mcspi1";
1259                         ti,spi-num-cs = <4>;
1260                         dmas = <&sdma_xbar 35>,
1261                                <&sdma_xbar 36>,
1262                                <&sdma_xbar 37>,
1263                                <&sdma_xbar 38>,
1264                                <&sdma_xbar 39>,
1265                                <&sdma_xbar 40>,
1266                                <&sdma_xbar 41>,
1267                                <&sdma_xbar 42>;
1268                         dma-names = "tx0", "rx0", "tx1", "rx1",
1269                                     "tx2", "rx2", "tx3", "rx3";
1270                         status = "disabled";
1271                 };
1272
1273                 mcspi2: spi@4809a000 {
1274                         compatible = "ti,omap4-mcspi";
1275                         reg = <0x4809a000 0x200>;
1276                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1277                         #address-cells = <1>;
1278                         #size-cells = <0>;
1279                         ti,hwmods = "mcspi2";
1280                         ti,spi-num-cs = <2>;
1281                         dmas = <&sdma_xbar 43>,
1282                                <&sdma_xbar 44>,
1283                                <&sdma_xbar 45>,
1284                                <&sdma_xbar 46>;
1285                         dma-names = "tx0", "rx0", "tx1", "rx1";
1286                         status = "disabled";
1287                 };
1288
1289                 mcspi3: spi@480b8000 {
1290                         compatible = "ti,omap4-mcspi";
1291                         reg = <0x480b8000 0x200>;
1292                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1293                         #address-cells = <1>;
1294                         #size-cells = <0>;
1295                         ti,hwmods = "mcspi3";
1296                         ti,spi-num-cs = <2>;
1297                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1298                         dma-names = "tx0", "rx0";
1299                         status = "disabled";
1300                 };
1301
1302                 mcspi4: spi@480ba000 {
1303                         compatible = "ti,omap4-mcspi";
1304                         reg = <0x480ba000 0x200>;
1305                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1306                         #address-cells = <1>;
1307                         #size-cells = <0>;
1308                         ti,hwmods = "mcspi4";
1309                         ti,spi-num-cs = <1>;
1310                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1311                         dma-names = "tx0", "rx0";
1312                         status = "disabled";
1313                 };
1314
1315                 qspi: qspi@4b300000 {
1316                         compatible = "ti,dra7xxx-qspi";
1317                         reg = <0x4b300000 0x100>,
1318                               <0x5c000000 0x4000000>;
1319                         reg-names = "qspi_base", "qspi_mmap";
1320                         syscon-chipselects = <&scm_conf 0x558>;
1321                         #address-cells = <1>;
1322                         #size-cells = <0>;
1323                         ti,hwmods = "qspi";
1324                         clocks = <&qspi_gfclk_div>;
1325                         clock-names = "fck";
1326                         num-cs = <4>;
1327                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1328                         status = "disabled";
1329                 };
1330
1331                 /* OCP2SCP3 */
1332                 ocp2scp@4a090000 {
1333                         compatible = "ti,omap-ocp2scp";
1334                         #address-cells = <1>;
1335                         #size-cells = <1>;
1336                         ranges;
1337                         reg = <0x4a090000 0x20>;
1338                         ti,hwmods = "ocp2scp3";
1339                         sata_phy: phy@4A096000 {
1340                                 compatible = "ti,phy-pipe3-sata";
1341                                 reg = <0x4A096000 0x80>, /* phy_rx */
1342                                       <0x4A096400 0x64>, /* phy_tx */
1343                                       <0x4A096800 0x40>; /* pll_ctrl */
1344                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1345                                 syscon-phy-power = <&scm_conf 0x374>;
1346                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1347                                 clock-names = "sysclk", "refclk";
1348                                 syscon-pllreset = <&scm_conf 0x3fc>;
1349                                 #phy-cells = <0>;
1350                         };
1351
1352                         pcie1_phy: pciephy@4a094000 {
1353                                 compatible = "ti,phy-pipe3-pcie";
1354                                 reg = <0x4a094000 0x80>, /* phy_rx */
1355                                       <0x4a094400 0x64>; /* phy_tx */
1356                                 reg-names = "phy_rx", "phy_tx";
1357                                 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1358                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1359                                 clocks = <&dpll_pcie_ref_ck>,
1360                                          <&dpll_pcie_ref_m2ldo_ck>,
1361                                          <&optfclk_pciephy1_32khz>,
1362                                          <&optfclk_pciephy1_clk>,
1363                                          <&optfclk_pciephy1_div_clk>,
1364                                          <&optfclk_pciephy_div>,
1365                                          <&sys_clkin1>;
1366                                 clock-names = "dpll_ref", "dpll_ref_m2",
1367                                               "wkupclk", "refclk",
1368                                               "div-clk", "phy-div", "sysclk";
1369                                 #phy-cells = <0>;
1370                         };
1371
1372                         pcie2_phy: pciephy@4a095000 {
1373                                 compatible = "ti,phy-pipe3-pcie";
1374                                 reg = <0x4a095000 0x80>, /* phy_rx */
1375                                       <0x4a095400 0x64>; /* phy_tx */
1376                                 reg-names = "phy_rx", "phy_tx";
1377                                 syscon-phy-power = <&scm_conf_pcie 0x20>;
1378                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1379                                 clocks = <&dpll_pcie_ref_ck>,
1380                                          <&dpll_pcie_ref_m2ldo_ck>,
1381                                          <&optfclk_pciephy2_32khz>,
1382                                          <&optfclk_pciephy2_clk>,
1383                                          <&optfclk_pciephy2_div_clk>,
1384                                          <&optfclk_pciephy_div>,
1385                                          <&sys_clkin1>;
1386                                 clock-names = "dpll_ref", "dpll_ref_m2",
1387                                               "wkupclk", "refclk",
1388                                               "div-clk", "phy-div", "sysclk";
1389                                 #phy-cells = <0>;
1390                                 status = "disabled";
1391                         };
1392                 };
1393
1394                 sata: sata@4a141100 {
1395                         compatible = "snps,dwc-ahci";
1396                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1397                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1398                         phys = <&sata_phy>;
1399                         phy-names = "sata-phy";
1400                         clocks = <&sata_ref_clk>;
1401                         ti,hwmods = "sata";
1402                         ports-implemented = <0x1>;
1403                 };
1404
1405                 rtc: rtc@48838000 {
1406                         compatible = "ti,am3352-rtc";
1407                         reg = <0x48838000 0x100>;
1408                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1409                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1410                         ti,hwmods = "rtcss";
1411                         clocks = <&sys_32k_ck>;
1412                 };
1413
1414                 /* OCP2SCP1 */
1415                 ocp2scp@4a080000 {
1416                         compatible = "ti,omap-ocp2scp";
1417                         #address-cells = <1>;
1418                         #size-cells = <1>;
1419                         ranges;
1420                         reg = <0x4a080000 0x20>;
1421                         ti,hwmods = "ocp2scp1";
1422
1423                         usb2_phy1: phy@4a084000 {
1424                                 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1425                                 reg = <0x4a084000 0x400>;
1426                                 syscon-phy-power = <&scm_conf 0x300>;
1427                                 clocks = <&usb_phy1_always_on_clk32k>,
1428                                          <&usb_otg_ss1_refclk960m>;
1429                                 clock-names =   "wkupclk",
1430                                                 "refclk";
1431                                 #phy-cells = <0>;
1432                         };
1433
1434                         usb2_phy2: phy@4a085000 {
1435                                 compatible = "ti,dra7x-usb2-phy2",
1436                                              "ti,omap-usb2";
1437                                 reg = <0x4a085000 0x400>;
1438                                 syscon-phy-power = <&scm_conf 0xe74>;
1439                                 clocks = <&usb_phy2_always_on_clk32k>,
1440                                          <&usb_otg_ss2_refclk960m>;
1441                                 clock-names =   "wkupclk",
1442                                                 "refclk";
1443                                 #phy-cells = <0>;
1444                         };
1445
1446                         usb3_phy1: phy@4a084400 {
1447                                 compatible = "ti,omap-usb3";
1448                                 reg = <0x4a084400 0x80>,
1449                                       <0x4a084800 0x64>,
1450                                       <0x4a084c00 0x40>;
1451                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1452                                 syscon-phy-power = <&scm_conf 0x370>;
1453                                 clocks = <&usb_phy3_always_on_clk32k>,
1454                                          <&sys_clkin1>,
1455                                          <&usb_otg_ss1_refclk960m>;
1456                                 clock-names =   "wkupclk",
1457                                                 "sysclk",
1458                                                 "refclk";
1459                                 #phy-cells = <0>;
1460                         };
1461                 };
1462
1463                 omap_dwc3_1: omap_dwc3_1@48880000 {
1464                         compatible = "ti,dwc3";
1465                         ti,hwmods = "usb_otg_ss1";
1466                         reg = <0x48880000 0x10000>;
1467                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1468                         #address-cells = <1>;
1469                         #size-cells = <1>;
1470                         utmi-mode = <2>;
1471                         ranges;
1472                         usb1: usb@48890000 {
1473                                 compatible = "snps,dwc3";
1474                                 reg = <0x48890000 0x17000>;
1475                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1476                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1477                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1478                                 interrupt-names = "peripheral",
1479                                                   "host",
1480                                                   "otg";
1481                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1482                                 phy-names = "usb2-phy", "usb3-phy";
1483                                 maximum-speed = "super-speed";
1484                                 dr_mode = "otg";
1485                                 snps,dis_u3_susphy_quirk;
1486                                 snps,dis_u2_susphy_quirk;
1487                         };
1488                 };
1489
1490                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1491                         compatible = "ti,dwc3";
1492                         ti,hwmods = "usb_otg_ss2";
1493                         reg = <0x488c0000 0x10000>;
1494                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1495                         #address-cells = <1>;
1496                         #size-cells = <1>;
1497                         utmi-mode = <2>;
1498                         ranges;
1499                         usb2: usb@488d0000 {
1500                                 compatible = "snps,dwc3";
1501                                 reg = <0x488d0000 0x17000>;
1502                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1503                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1504                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1505                                 interrupt-names = "peripheral",
1506                                                   "host",
1507                                                   "otg";
1508                                 phys = <&usb2_phy2>;
1509                                 phy-names = "usb2-phy";
1510                                 maximum-speed = "high-speed";
1511                                 dr_mode = "otg";
1512                                 snps,dis_u3_susphy_quirk;
1513                                 snps,dis_u2_susphy_quirk;
1514                         };
1515                 };
1516
1517                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1518                 omap_dwc3_3: omap_dwc3_3@48900000 {
1519                         compatible = "ti,dwc3";
1520                         ti,hwmods = "usb_otg_ss3";
1521                         reg = <0x48900000 0x10000>;
1522                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1523                         #address-cells = <1>;
1524                         #size-cells = <1>;
1525                         utmi-mode = <2>;
1526                         ranges;
1527                         status = "disabled";
1528                         usb3: usb@48910000 {
1529                                 compatible = "snps,dwc3";
1530                                 reg = <0x48910000 0x17000>;
1531                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1532                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1533                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1534                                 interrupt-names = "peripheral",
1535                                                   "host",
1536                                                   "otg";
1537                                 maximum-speed = "high-speed";
1538                                 dr_mode = "otg";
1539                                 snps,dis_u3_susphy_quirk;
1540                                 snps,dis_u2_susphy_quirk;
1541                         };
1542                 };
1543
1544                 elm: elm@48078000 {
1545                         compatible = "ti,am3352-elm";
1546                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1547                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1548                         ti,hwmods = "elm";
1549                         status = "disabled";
1550                 };
1551
1552                 gpmc: gpmc@50000000 {
1553                         compatible = "ti,am3352-gpmc";
1554                         ti,hwmods = "gpmc";
1555                         reg = <0x50000000 0x37c>;      /* device IO registers */
1556                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1557                         dmas = <&edma_xbar 4 0>;
1558                         dma-names = "rxtx";
1559                         gpmc,num-cs = <8>;
1560                         gpmc,num-waitpins = <2>;
1561                         #address-cells = <2>;
1562                         #size-cells = <1>;
1563                         interrupt-controller;
1564                         #interrupt-cells = <2>;
1565                         gpio-controller;
1566                         #gpio-cells = <2>;
1567                         status = "disabled";
1568                 };
1569
1570                 atl: atl@4843c000 {
1571                         compatible = "ti,dra7-atl";
1572                         reg = <0x4843c000 0x3ff>;
1573                         ti,hwmods = "atl";
1574                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1575                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1576                         clocks = <&atl_gfclk_mux>;
1577                         clock-names = "fck";
1578                         status = "disabled";
1579                 };
1580
1581                 mcasp1: mcasp@48460000 {
1582                         compatible = "ti,dra7-mcasp-audio";
1583                         ti,hwmods = "mcasp1";
1584                         reg = <0x48460000 0x2000>,
1585                               <0x45800000 0x1000>;
1586                         reg-names = "mpu","dat";
1587                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1588                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1589                         interrupt-names = "tx", "rx";
1590                         dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1591                         dma-names = "tx", "rx";
1592                         clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1593                                  <&mcasp1_ahclkr_mux>;
1594                         clock-names = "fck", "ahclkx", "ahclkr";
1595                         status = "disabled";
1596                 };
1597
1598                 mcasp2: mcasp@48464000 {
1599                         compatible = "ti,dra7-mcasp-audio";
1600                         ti,hwmods = "mcasp2";
1601                         reg = <0x48464000 0x2000>,
1602                               <0x45c00000 0x1000>;
1603                         reg-names = "mpu","dat";
1604                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1605                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1606                         interrupt-names = "tx", "rx";
1607                         dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1608                         dma-names = "tx", "rx";
1609                         clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1610                                  <&mcasp2_ahclkr_mux>;
1611                         clock-names = "fck", "ahclkx", "ahclkr";
1612                         status = "disabled";
1613                 };
1614
1615                 mcasp3: mcasp@48468000 {
1616                         compatible = "ti,dra7-mcasp-audio";
1617                         ti,hwmods = "mcasp3";
1618                         reg = <0x48468000 0x2000>,
1619                               <0x46000000 0x1000>;
1620                         reg-names = "mpu","dat";
1621                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1622                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1623                         interrupt-names = "tx", "rx";
1624                         dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1625                         dma-names = "tx", "rx";
1626                         clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1627                         clock-names = "fck", "ahclkx";
1628                         status = "disabled";
1629                 };
1630
1631                 mcasp4: mcasp@4846c000 {
1632                         compatible = "ti,dra7-mcasp-audio";
1633                         ti,hwmods = "mcasp4";
1634                         reg = <0x4846c000 0x2000>,
1635                               <0x48436000 0x1000>;
1636                         reg-names = "mpu","dat";
1637                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1638                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1639                         interrupt-names = "tx", "rx";
1640                         dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1641                         dma-names = "tx", "rx";
1642                         clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1643                         clock-names = "fck", "ahclkx";
1644                         status = "disabled";
1645                 };
1646
1647                 mcasp5: mcasp@48470000 {
1648                         compatible = "ti,dra7-mcasp-audio";
1649                         ti,hwmods = "mcasp5";
1650                         reg = <0x48470000 0x2000>,
1651                               <0x4843a000 0x1000>;
1652                         reg-names = "mpu","dat";
1653                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1654                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1655                         interrupt-names = "tx", "rx";
1656                         dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1657                         dma-names = "tx", "rx";
1658                         clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1659                         clock-names = "fck", "ahclkx";
1660                         status = "disabled";
1661                 };
1662
1663                 mcasp6: mcasp@48474000 {
1664                         compatible = "ti,dra7-mcasp-audio";
1665                         ti,hwmods = "mcasp6";
1666                         reg = <0x48474000 0x2000>,
1667                               <0x4844c000 0x1000>;
1668                         reg-names = "mpu","dat";
1669                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1670                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1671                         interrupt-names = "tx", "rx";
1672                         dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1673                         dma-names = "tx", "rx";
1674                         clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1675                         clock-names = "fck", "ahclkx";
1676                         status = "disabled";
1677                 };
1678
1679                 mcasp7: mcasp@48478000 {
1680                         compatible = "ti,dra7-mcasp-audio";
1681                         ti,hwmods = "mcasp7";
1682                         reg = <0x48478000 0x2000>,
1683                               <0x48450000 0x1000>;
1684                         reg-names = "mpu","dat";
1685                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1686                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1687                         interrupt-names = "tx", "rx";
1688                         dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1689                         dma-names = "tx", "rx";
1690                         clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1691                         clock-names = "fck", "ahclkx";
1692                         status = "disabled";
1693                 };
1694
1695                 mcasp8: mcasp@4847c000 {
1696                         compatible = "ti,dra7-mcasp-audio";
1697                         ti,hwmods = "mcasp8";
1698                         reg = <0x4847c000 0x2000>,
1699                               <0x48454000 0x1000>;
1700                         reg-names = "mpu","dat";
1701                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1702                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1703                         interrupt-names = "tx", "rx";
1704                         dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1705                         dma-names = "tx", "rx";
1706                         clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1707                         clock-names = "fck", "ahclkx";
1708                         status = "disabled";
1709                 };
1710
1711                 crossbar_mpu: crossbar@4a002a48 {
1712                         compatible = "ti,irq-crossbar";
1713                         reg = <0x4a002a48 0x130>;
1714                         interrupt-controller;
1715                         interrupt-parent = <&wakeupgen>;
1716                         #interrupt-cells = <3>;
1717                         ti,max-irqs = <160>;
1718                         ti,max-crossbar-sources = <MAX_SOURCES>;
1719                         ti,reg-size = <2>;
1720                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1721                         ti,irqs-skip = <10 133 139 140>;
1722                         ti,irqs-safe-map = <0>;
1723                 };
1724
1725                 mac: ethernet@48484000 {
1726                         compatible = "ti,dra7-cpsw","ti,cpsw";
1727                         ti,hwmods = "gmac";
1728                         clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1729                         clock-names = "fck", "cpts";
1730                         cpdma_channels = <8>;
1731                         ale_entries = <1024>;
1732                         bd_ram_size = <0x2000>;
1733                         mac_control = <0x20>;
1734                         slaves = <2>;
1735                         active_slave = <0>;
1736                         cpts_clock_mult = <0x784CFE14>;
1737                         cpts_clock_shift = <29>;
1738                         reg = <0x48484000 0x1000
1739                                0x48485200 0x2E00>;
1740                         #address-cells = <1>;
1741                         #size-cells = <1>;
1742
1743                         /*
1744                          * Do not allow gating of cpsw clock as workaround
1745                          * for errata i877. Keeping internal clock disabled
1746                          * causes the device switching characteristics
1747                          * to degrade over time and eventually fail to meet
1748                          * the data manual delay time/skew specs.
1749                          */
1750                         ti,no-idle;
1751
1752                         /*
1753                          * rx_thresh_pend
1754                          * rx_pend
1755                          * tx_pend
1756                          * misc_pend
1757                          */
1758                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1759                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1760                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1761                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1762                         ranges;
1763                         syscon = <&scm_conf>;
1764                         status = "disabled";
1765
1766                         davinci_mdio: mdio@48485000 {
1767                                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1768                                 #address-cells = <1>;
1769                                 #size-cells = <0>;
1770                                 ti,hwmods = "davinci_mdio";
1771                                 bus_freq = <1000000>;
1772                                 reg = <0x48485000 0x100>;
1773                         };
1774
1775                         cpsw_emac0: slave@48480200 {
1776                                 /* Filled in by U-Boot */
1777                                 mac-address = [ 00 00 00 00 00 00 ];
1778                         };
1779
1780                         cpsw_emac1: slave@48480300 {
1781                                 /* Filled in by U-Boot */
1782                                 mac-address = [ 00 00 00 00 00 00 ];
1783                         };
1784
1785                         phy_sel: cpsw-phy-sel@4a002554 {
1786                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1787                                 reg= <0x4a002554 0x4>;
1788                                 reg-names = "gmii-sel";
1789                         };
1790                 };
1791
1792                 dcan1: can@481cc000 {
1793                         compatible = "ti,dra7-d_can";
1794                         ti,hwmods = "dcan1";
1795                         reg = <0x4ae3c000 0x2000>;
1796                         syscon-raminit = <&scm_conf 0x558 0>;
1797                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1798                         clocks = <&dcan1_sys_clk_mux>;
1799                         status = "disabled";
1800                 };
1801
1802                 dcan2: can@481d0000 {
1803                         compatible = "ti,dra7-d_can";
1804                         ti,hwmods = "dcan2";
1805                         reg = <0x48480000 0x2000>;
1806                         syscon-raminit = <&scm_conf 0x558 1>;
1807                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1808                         clocks = <&sys_clkin1>;
1809                         status = "disabled";
1810                 };
1811
1812                 dss: dss@58000000 {
1813                         compatible = "ti,dra7-dss";
1814                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1815                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1816                         status = "disabled";
1817                         ti,hwmods = "dss_core";
1818                         /* CTRL_CORE_DSS_PLL_CONTROL */
1819                         syscon-pll-ctrl = <&scm_conf 0x538>;
1820                         #address-cells = <1>;
1821                         #size-cells = <1>;
1822                         ranges;
1823
1824                         dispc@58001000 {
1825                                 compatible = "ti,dra7-dispc";
1826                                 reg = <0x58001000 0x1000>;
1827                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1828                                 ti,hwmods = "dss_dispc";
1829                                 clocks = <&dss_dss_clk>;
1830                                 clock-names = "fck";
1831                                 /* CTRL_CORE_SMA_SW_1 */
1832                                 syscon-pol = <&scm_conf 0x534>;
1833                         };
1834
1835                         hdmi: encoder@58060000 {
1836                                 compatible = "ti,dra7-hdmi";
1837                                 reg = <0x58040000 0x200>,
1838                                       <0x58040200 0x80>,
1839                                       <0x58040300 0x80>,
1840                                       <0x58060000 0x19000>;
1841                                 reg-names = "wp", "pll", "phy", "core";
1842                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1843                                 status = "disabled";
1844                                 ti,hwmods = "dss_hdmi";
1845                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1846                                 clock-names = "fck", "sys_clk";
1847                         };
1848                 };
1849
1850                 epwmss0: epwmss@4843e000 {
1851                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1852                         reg = <0x4843e000 0x30>;
1853                         ti,hwmods = "epwmss0";
1854                         #address-cells = <1>;
1855                         #size-cells = <1>;
1856                         status = "disabled";
1857                         ranges;
1858
1859                         ehrpwm0: pwm@4843e200 {
1860                                 compatible = "ti,dra746-ehrpwm",
1861                                              "ti,am3352-ehrpwm";
1862                                 #pwm-cells = <3>;
1863                                 reg = <0x4843e200 0x80>;
1864                                 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1865                                 clock-names = "tbclk", "fck";
1866                                 status = "disabled";
1867                         };
1868
1869                         ecap0: ecap@4843e100 {
1870                                 compatible = "ti,dra746-ecap",
1871                                              "ti,am3352-ecap";
1872                                 #pwm-cells = <3>;
1873                                 reg = <0x4843e100 0x80>;
1874                                 clocks = <&l4_root_clk_div>;
1875                                 clock-names = "fck";
1876                                 status = "disabled";
1877                         };
1878                 };
1879
1880                 epwmss1: epwmss@48440000 {
1881                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1882                         reg = <0x48440000 0x30>;
1883                         ti,hwmods = "epwmss1";
1884                         #address-cells = <1>;
1885                         #size-cells = <1>;
1886                         status = "disabled";
1887                         ranges;
1888
1889                         ehrpwm1: pwm@48440200 {
1890                                 compatible = "ti,dra746-ehrpwm",
1891                                              "ti,am3352-ehrpwm";
1892                                 #pwm-cells = <3>;
1893                                 reg = <0x48440200 0x80>;
1894                                 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1895                                 clock-names = "tbclk", "fck";
1896                                 status = "disabled";
1897                         };
1898
1899                         ecap1: ecap@48440100 {
1900                                 compatible = "ti,dra746-ecap",
1901                                              "ti,am3352-ecap";
1902                                 #pwm-cells = <3>;
1903                                 reg = <0x48440100 0x80>;
1904                                 clocks = <&l4_root_clk_div>;
1905                                 clock-names = "fck";
1906                                 status = "disabled";
1907                         };
1908                 };
1909
1910                 epwmss2: epwmss@48442000 {
1911                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1912                         reg = <0x48442000 0x30>;
1913                         ti,hwmods = "epwmss2";
1914                         #address-cells = <1>;
1915                         #size-cells = <1>;
1916                         status = "disabled";
1917                         ranges;
1918
1919                         ehrpwm2: pwm@48442200 {
1920                                 compatible = "ti,dra746-ehrpwm",
1921                                              "ti,am3352-ehrpwm";
1922                                 #pwm-cells = <3>;
1923                                 reg = <0x48442200 0x80>;
1924                                 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1925                                 clock-names = "tbclk", "fck";
1926                                 status = "disabled";
1927                         };
1928
1929                         ecap2: ecap@48442100 {
1930                                 compatible = "ti,dra746-ecap",
1931                                              "ti,am3352-ecap";
1932                                 #pwm-cells = <3>;
1933                                 reg = <0x48442100 0x80>;
1934                                 clocks = <&l4_root_clk_div>;
1935                                 clock-names = "fck";
1936                                 status = "disabled";
1937                         };
1938                 };
1939
1940                 aes1: aes@4b500000 {
1941                         compatible = "ti,omap4-aes";
1942                         ti,hwmods = "aes1";
1943                         reg = <0x4b500000 0xa0>;
1944                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1945                         dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1946                         dma-names = "tx", "rx";
1947                         clocks = <&l3_iclk_div>;
1948                         clock-names = "fck";
1949                 };
1950
1951                 aes2: aes@4b700000 {
1952                         compatible = "ti,omap4-aes";
1953                         ti,hwmods = "aes2";
1954                         reg = <0x4b700000 0xa0>;
1955                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1956                         dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1957                         dma-names = "tx", "rx";
1958                         clocks = <&l3_iclk_div>;
1959                         clock-names = "fck";
1960                 };
1961
1962                 des: des@480a5000 {
1963                         compatible = "ti,omap4-des";
1964                         ti,hwmods = "des";
1965                         reg = <0x480a5000 0xa0>;
1966                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1967                         dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1968                         dma-names = "tx", "rx";
1969                         clocks = <&l3_iclk_div>;
1970                         clock-names = "fck";
1971                 };
1972
1973                 sham: sham@53100000 {
1974                         compatible = "ti,omap5-sham";
1975                         ti,hwmods = "sham";
1976                         reg = <0x4b101000 0x300>;
1977                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1978                         dmas = <&edma_xbar 119 0>;
1979                         dma-names = "rx";
1980                         clocks = <&l3_iclk_div>;
1981                         clock-names = "fck";
1982                 };
1983
1984                 rng: rng@48090000 {
1985                         compatible = "ti,omap4-rng";
1986                         ti,hwmods = "rng";
1987                         reg = <0x48090000 0x2000>;
1988                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1989                         clocks = <&l3_iclk_div>;
1990                         clock-names = "fck";
1991                 };
1992         };
1993
1994         thermal_zones: thermal-zones {
1995                 #include "omap4-cpu-thermal.dtsi"
1996                 #include "omap5-gpu-thermal.dtsi"
1997                 #include "omap5-core-thermal.dtsi"
1998                 #include "dra7-dspeve-thermal.dtsi"
1999                 #include "dra7-iva-thermal.dtsi"
2000         };
2001
2002 };
2003
2004 &cpu_thermal {
2005         polling-delay = <500>; /* milliseconds */
2006         coefficients = <0 2000>;
2007 };
2008
2009 &gpu_thermal {
2010         coefficients = <0 2000>;
2011 };
2012
2013 &core_thermal {
2014         coefficients = <0 2000>;
2015 };
2016
2017 &dspeve_thermal {
2018         coefficients = <0 2000>;
2019 };
2020
2021 &iva_thermal {
2022         coefficients = <0 2000>;
2023 };
2024
2025 &cpu_crit {
2026         temperature = <120000>; /* milli Celsius */
2027 };
2028
2029 /include/ "dra7xx-clocks.dtsi"