arch/arm/boot/dts/dra7-l4.dtsi

   1 &l4_cfg {                                               /* 0x4a000000 */
   2         compatible = "ti,dra7-l4-cfg", "simple-bus";
   3         reg = <0x4a000000 0x800>,
   4               <0x4a000800 0x800>,
   5               <0x4a001000 0x1000>;
   6         reg-names = "ap", "la", "ia0";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         ranges = <0x00000000 0x4a000000 0x100000>,      /* segment 0 */
  10                  <0x00100000 0x4a100000 0x100000>,      /* segment 1 */
  11                  <0x00200000 0x4a200000 0x100000>;      /* segment 2 */
  12
  13         segment@0 {                                     /* 0x4a000000 */
  14                 compatible = "simple-bus";
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
  18                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
  19                          <0x00001000 0x00001000 0x001000>,      /* ap 2 */
  20                          <0x00002000 0x00002000 0x002000>,      /* ap 3 */
  21                          <0x00004000 0x00004000 0x001000>,      /* ap 4 */
  22                          <0x00005000 0x00005000 0x001000>,      /* ap 5 */
  23                          <0x00006000 0x00006000 0x001000>,      /* ap 6 */
  24                          <0x00008000 0x00008000 0x002000>,      /* ap 7 */
  25                          <0x0000a000 0x0000a000 0x001000>,      /* ap 8 */
  26                          <0x00056000 0x00056000 0x001000>,      /* ap 9 */
  27                          <0x00057000 0x00057000 0x001000>,      /* ap 10 */
  28                          <0x0005e000 0x0005e000 0x002000>,      /* ap 11 */
  29                          <0x00060000 0x00060000 0x001000>,      /* ap 12 */
  30                          <0x00080000 0x00080000 0x008000>,      /* ap 13 */
  31                          <0x00088000 0x00088000 0x001000>,      /* ap 14 */
  32                          <0x000a0000 0x000a0000 0x008000>,      /* ap 15 */
  33                          <0x000a8000 0x000a8000 0x001000>,      /* ap 16 */
  34                          <0x000d9000 0x000d9000 0x001000>,      /* ap 17 */
  35                          <0x000da000 0x000da000 0x001000>,      /* ap 18 */
  36                          <0x000dd000 0x000dd000 0x001000>,      /* ap 19 */
  37                          <0x000de000 0x000de000 0x001000>,      /* ap 20 */
  38                          <0x000e0000 0x000e0000 0x001000>,      /* ap 21 */
  39                          <0x000e1000 0x000e1000 0x001000>,      /* ap 22 */
  40                          <0x000f4000 0x000f4000 0x001000>,      /* ap 23 */
  41                          <0x000f5000 0x000f5000 0x001000>,      /* ap 24 */
  42                          <0x000f6000 0x000f6000 0x001000>,      /* ap 25 */
  43                          <0x000f7000 0x000f7000 0x001000>,      /* ap 26 */
  44                          <0x00090000 0x00090000 0x008000>,      /* ap 59 */
  45                          <0x00098000 0x00098000 0x001000>;      /* ap 60 */
  46
  47                 target-module@2000 {                    /* 0x4a002000, ap 3 08.0 */
  48                         compatible = "ti,sysc-omap4", "ti,sysc";
  49                         reg = <0x2000 0x4>;
  50                         reg-names = "rev";
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53                         ranges = <0x0 0x2000 0x2000>;
  54
  55                         scm: scm@0 {
  56                                 compatible = "ti,dra7-scm-core", "simple-bus";
  57                                 reg = <0 0x2000>;
  58                                 #address-cells = <1>;
  59                                 #size-cells = <1>;
  60                                 ranges = <0 0 0x2000>;
  61
  62                                 scm_conf: scm_conf@0 {
  63                                         compatible = "syscon", "simple-bus";
  64                                         reg = <0x0 0x1400>;
  65                                         #address-cells = <1>;
  66                                         #size-cells = <1>;
  67                                         ranges = <0 0x0 0x1400>;
  68
  69                                         pbias_regulator: pbias_regulator@e00 {
  70                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
  71                                                 reg = <0xe00 0x4>;
  72                                                 syscon = <&scm_conf>;
  73                                                 pbias_mmc_reg: pbias_mmc_omap5 {
  74                                                         regulator-name = "pbias_mmc_omap5";
  75                                                         regulator-min-microvolt = <1800000>;
  76                                                         regulator-max-microvolt = <3300000>;
  77                                                 };
  78                                         };
  79
  80                                         phy_gmii_sel: phy-gmii-sel {
  81                                                 compatible = "ti,dra7xx-phy-gmii-sel";
  82                                                 reg = <0x554 0x4>;
  83                                                 #phy-cells = <1>;
  84                                         };
  85
  86                                         scm_conf_clocks: clocks {
  87                                                 #address-cells = <1>;
  88                                                 #size-cells = <0>;
  89                                         };
  90                                 };
  91
  92                                 dra7_pmx_core: pinmux@1400 {
  93                                         compatible = "ti,dra7-padconf",
  94                                                      "pinctrl-single";
  95                                         reg = <0x1400 0x0468>;
  96                                         #address-cells = <1>;
  97                                         #size-cells = <0>;
  98                                         #pinctrl-cells = <1>;
  99                                         #interrupt-cells = <1>;
 100                                         interrupt-controller;
 101                                         pinctrl-single,register-width = <32>;
 102                                         pinctrl-single,function-mask = <0x3fffffff>;
 103                                 };
 104
 105                                 scm_conf1: scm_conf@1c04 {
 106                                         compatible = "syscon";
 107                                         reg = <0x1c04 0x0020>;
 108                                         #syscon-cells = <2>;
 109                                 };
 110
 111                                 scm_conf_pcie: scm_conf@1c24 {
 112                                         compatible = "syscon";
 113                                         reg = <0x1c24 0x0024>;
 114                                 };
 115
 116                                 sdma_xbar: dma-router@b78 {
 117                                         compatible = "ti,dra7-dma-crossbar";
 118                                         reg = <0xb78 0xfc>;
 119                                         #dma-cells = <1>;
 120                                         dma-requests = <205>;
 121                                         ti,dma-safe-map = <0>;
 122                                         dma-masters = <&sdma>;
 123                                 };
 124
 125                                 edma_xbar: dma-router@c78 {
 126                                         compatible = "ti,dra7-dma-crossbar";
 127                                         reg = <0xc78 0x7c>;
 128                                         #dma-cells = <2>;
 129                                         dma-requests = <204>;
 130                                         ti,dma-safe-map = <0>;
 131                                         dma-masters = <&edma>;
 132                                 };
 133                         };
 134                 };
 135
 136                 target-module@5000 {                    /* 0x4a005000, ap 5 10.0 */
 137                         compatible = "ti,sysc-omap4", "ti,sysc";
 138                         reg = <0x5000 0x4>;
 139                         reg-names = "rev";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         ranges = <0x0 0x5000 0x1000>;
 143
 144                         cm_core_aon: cm_core_aon@0 {
 145                                 compatible = "ti,dra7-cm-core-aon",
 146                                               "simple-bus";
 147                                 #address-cells = <1>;
 148                                 #size-cells = <1>;
 149                                 reg = <0 0x2000>;
 150                                 ranges = <0 0 0x2000>;
 151
 152                                 cm_core_aon_clocks: clocks {
 153                                         #address-cells = <1>;
 154                                         #size-cells = <0>;
 155                                 };
 156
 157                                 cm_core_aon_clockdomains: clockdomains {
 158                                 };
 159                         };
 160                 };
 161
 162                 target-module@8000 {                    /* 0x4a008000, ap 7 0e.0 */
 163                         compatible = "ti,sysc-omap4", "ti,sysc";
 164                         reg = <0x8000 0x4>;
 165                         reg-names = "rev";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x0 0x8000 0x2000>;
 169
 170                         cm_core: cm_core@0 {
 171                                 compatible = "ti,dra7-cm-core", "simple-bus";
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 reg = <0 0x3000>;
 175                                 ranges = <0 0 0x3000>;
 176
 177                                 cm_core_clocks: clocks {
 178                                         #address-cells = <1>;
 179                                         #size-cells = <0>;
 180                                 };
 181
 182                                 cm_core_clockdomains: clockdomains {
 183                                 };
 184                         };
 185                 };
 186
 187                 target-module@56000 {                   /* 0x4a056000, ap 9 02.0 */
 188                         compatible = "ti,sysc-omap2", "ti,sysc";
 189                         reg = <0x56000 0x4>,
 190                               <0x5602c 0x4>,
 191                               <0x56028 0x4>;
 192                         reg-names = "rev", "sysc", "syss";
 193                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 194                                          SYSC_OMAP2_EMUFREE |
 195                                          SYSC_OMAP2_SOFTRESET |
 196                                          SYSC_OMAP2_AUTOIDLE)>;
 197                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 198                                         <SYSC_IDLE_NO>,
 199                                         <SYSC_IDLE_SMART>,
 200                                         <SYSC_IDLE_SMART_WKUP>;
 201                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 202                                         <SYSC_IDLE_NO>,
 203                                         <SYSC_IDLE_SMART>,
 204                                         <SYSC_IDLE_SMART_WKUP>;
 205                         ti,syss-mask = <1>;
 206                         /* Domains (P, C): core_pwrdm, dma_clkdm */
 207                         clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
 208                         clock-names = "fck";
 209                         #address-cells = <1>;
 210                         #size-cells = <1>;
 211                         ranges = <0x0 0x56000 0x1000>;
 212
 213                         sdma: dma-controller@0 {
 214                                 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
 215                                 reg = <0x0 0x1000>;
 216                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 217                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 218                                              <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 219                                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 220                                 #dma-cells = <1>;
 221                                 dma-channels = <32>;
 222                                 dma-requests = <127>;
 223                         };
 224                 };
 225
 226                 target-module@5e000 {                   /* 0x4a05e000, ap 11 1a.0 */
 227                         compatible = "ti,sysc";
 228                         status = "disabled";
 229                         #address-cells = <1>;
 230                         #size-cells = <1>;
 231                         ranges = <0x0 0x5e000 0x2000>;
 232                 };
 233
 234                 target-module@80000 {                   /* 0x4a080000, ap 13 20.0 */
 235                         compatible = "ti,sysc-omap2", "ti,sysc";
 236                         reg = <0x80000 0x4>,
 237                               <0x80010 0x4>,
 238                               <0x80014 0x4>;
 239                         reg-names = "rev", "sysc", "syss";
 240                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 241                                          SYSC_OMAP2_AUTOIDLE)>;
 242                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 243                                         <SYSC_IDLE_NO>,
 244                                         <SYSC_IDLE_SMART>;
 245                         ti,syss-mask = <1>;
 246                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 247                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
 248                         clock-names = "fck";
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         ranges = <0x0 0x80000 0x8000>;
 252
 253                         ocp2scp@0 {
 254                                 compatible = "ti,omap-ocp2scp";
 255                                 #address-cells = <1>;
 256                                 #size-cells = <1>;
 257                                 ranges = <0 0 0x8000>;
 258                                 reg = <0x0 0x20>;
 259
 260                                 usb2_phy1: phy@4000 {
 261                                         compatible = "ti,dra7x-usb2", "ti,omap-usb2";
 262                                         reg = <0x4000 0x400>;
 263                                         syscon-phy-power = <&scm_conf 0x300>;
 264                                         clocks = <&usb_phy1_always_on_clk32k>,
 265                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 266                                         clock-names =   "wkupclk",
 267                                                         "refclk";
 268                                         #phy-cells = <0>;
 269                                 };
 270
 271                                 usb2_phy2: phy@5000 {
 272                                         compatible = "ti,dra7x-usb2-phy2",
 273                                                      "ti,omap-usb2";
 274                                         reg = <0x5000 0x400>;
 275                                         syscon-phy-power = <&scm_conf 0xe74>;
 276                                         clocks = <&usb_phy2_always_on_clk32k>,
 277                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
 278                                         clock-names =   "wkupclk",
 279                                                         "refclk";
 280                                         #phy-cells = <0>;
 281                                 };
 282
 283                                 usb3_phy1: phy@4400 {
 284                                         compatible = "ti,omap-usb3";
 285                                         reg = <0x4400 0x80>,
 286                                               <0x4800 0x64>,
 287                                               <0x4c00 0x40>;
 288                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 289                                         syscon-phy-power = <&scm_conf 0x370>;
 290                                         clocks = <&usb_phy3_always_on_clk32k>,
 291                                                  <&sys_clkin1>,
 292                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 293                                         clock-names =   "wkupclk",
 294                                                         "sysclk",
 295                                                         "refclk";
 296                                         #phy-cells = <0>;
 297                                 };
 298                         };
 299                 };
 300
 301                 target-module@90000 {                   /* 0x4a090000, ap 59 42.0 */
 302                         compatible = "ti,sysc-omap2", "ti,sysc";
 303                         reg = <0x90000 0x4>,
 304                               <0x90010 0x4>,
 305                               <0x90014 0x4>;
 306                         reg-names = "rev", "sysc", "syss";
 307                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 308                                          SYSC_OMAP2_AUTOIDLE)>;
 309                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 310                                         <SYSC_IDLE_NO>,
 311                                         <SYSC_IDLE_SMART>;
 312                         ti,syss-mask = <1>;
 313                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 314                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
 315                         clock-names = "fck";
 316                         #address-cells = <1>;
 317                         #size-cells = <1>;
 318                         ranges = <0x0 0x90000 0x8000>;
 319
 320                         ocp2scp@0 {
 321                                 compatible = "ti,omap-ocp2scp";
 322                                 #address-cells = <1>;
 323                                 #size-cells = <1>;
 324                                 ranges = <0 0 0x8000>;
 325                                 reg = <0x0 0x20>;
 326
 327                                 pcie1_phy: pciephy@4000 {
 328                                         compatible = "ti,phy-pipe3-pcie";
 329                                         reg = <0x4000 0x80>, /* phy_rx */
 330                                               <0x4400 0x64>; /* phy_tx */
 331                                         reg-names = "phy_rx", "phy_tx";
 332                                         syscon-phy-power = <&scm_conf_pcie 0x1c>;
 333                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 334                                         clocks = <&dpll_pcie_ref_ck>,
 335                                                  <&dpll_pcie_ref_m2ldo_ck>,
 336                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
 337                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
 338                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
 339                                                  <&optfclk_pciephy_div>,
 340                                                  <&sys_clkin1>;
 341                                         clock-names = "dpll_ref", "dpll_ref_m2",
 342                                                       "wkupclk", "refclk",
 343                                                       "div-clk", "phy-div", "sysclk";
 344                                         #phy-cells = <0>;
 345                                 };
 346
 347                                 pcie2_phy: pciephy@5000 {
 348                                         compatible = "ti,phy-pipe3-pcie";
 349                                         reg = <0x5000 0x80>, /* phy_rx */
 350                                               <0x5400 0x64>; /* phy_tx */
 351                                         reg-names = "phy_rx", "phy_tx";
 352                                         syscon-phy-power = <&scm_conf_pcie 0x20>;
 353                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 354                                         clocks = <&dpll_pcie_ref_ck>,
 355                                                  <&dpll_pcie_ref_m2ldo_ck>,
 356                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
 357                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
 358                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
 359                                                  <&optfclk_pciephy_div>,
 360                                                  <&sys_clkin1>;
 361                                         clock-names = "dpll_ref", "dpll_ref_m2",
 362                                                       "wkupclk", "refclk",
 363                                                       "div-clk", "phy-div", "sysclk";
 364                                         #phy-cells = <0>;
 365                                         status = "disabled";
 366                                 };
 367
 368                                 sata_phy: phy@6000 {
 369                                         compatible = "ti,phy-pipe3-sata";
 370                                         reg = <0x6000 0x80>, /* phy_rx */
 371                                               <0x6400 0x64>, /* phy_tx */
 372                                               <0x6800 0x40>; /* pll_ctrl */
 373                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 374                                         syscon-phy-power = <&scm_conf 0x374>;
 375                                         clocks = <&sys_clkin1>,
 376                                                  <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
 377                                         clock-names = "sysclk", "refclk";
 378                                         syscon-pllreset = <&scm_conf 0x3fc>;
 379                                         #phy-cells = <0>;
 380                                 };
 381                         };
 382                 };
 383
 384                 target-module@a0000 {                   /* 0x4a0a0000, ap 15 40.0 */
 385                         compatible = "ti,sysc";
 386                         status = "disabled";
 387                         #address-cells = <1>;
 388                         #size-cells = <1>;
 389                         ranges = <0x0 0xa0000 0x8000>;
 390                 };
 391
 392                 target-module@d9000 {                   /* 0x4a0d9000, ap 17 72.0 */
 393                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 394                         reg = <0xd9038 0x4>;
 395                         reg-names = "sysc";
 396                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 397                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 398                                         <SYSC_IDLE_NO>,
 399                                         <SYSC_IDLE_SMART>,
 400                                         <SYSC_IDLE_SMART_WKUP>;
 401                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 402                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
 403                         clock-names = "fck";
 404                         #address-cells = <1>;
 405                         #size-cells = <1>;
 406                         ranges = <0x0 0xd9000 0x1000>;
 407
 408                         /* SmartReflex child device marked reserved in TRM */
 409                 };
 410
 411                 target-module@dd000 {                   /* 0x4a0dd000, ap 19 18.0 */
 412                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 413                         reg = <0xdd038 0x4>;
 414                         reg-names = "sysc";
 415                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 416                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 417                                         <SYSC_IDLE_NO>,
 418                                         <SYSC_IDLE_SMART>,
 419                                         <SYSC_IDLE_SMART_WKUP>;
 420                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 421                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
 422                         clock-names = "fck";
 423                         #address-cells = <1>;
 424                         #size-cells = <1>;
 425                         ranges = <0x0 0xdd000 0x1000>;
 426
 427                         /* SmartReflex child device marked reserved in TRM */
 428                 };
 429
 430                 target-module@e0000 {                   /* 0x4a0e0000, ap 21 28.0 */
 431                         compatible = "ti,sysc";
 432                         status = "disabled";
 433                         #address-cells = <1>;
 434                         #size-cells = <1>;
 435                         ranges = <0x0 0xe0000 0x1000>;
 436                 };
 437
 438                 target-module@f4000 {                   /* 0x4a0f4000, ap 23 04.0 */
 439                         compatible = "ti,sysc-omap4", "ti,sysc";
 440                         reg = <0xf4000 0x4>,
 441                               <0xf4010 0x4>;
 442                         reg-names = "rev", "sysc";
 443                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 444                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 445                                         <SYSC_IDLE_NO>,
 446                                         <SYSC_IDLE_SMART>;
 447                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 448                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
 449                         clock-names = "fck";
 450                         #address-cells = <1>;
 451                         #size-cells = <1>;
 452                         ranges = <0x0 0xf4000 0x1000>;
 453
 454                         mailbox1: mailbox@0 {
 455                                 compatible = "ti,omap4-mailbox";
 456                                 reg = <0x0 0x200>;
 457                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 458                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 459                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 460                                 #mbox-cells = <1>;
 461                                 ti,mbox-num-users = <3>;
 462                                 ti,mbox-num-fifos = <8>;
 463                                 status = "disabled";
 464                         };
 465                 };
 466
 467                 target-module@f6000 {                   /* 0x4a0f6000, ap 25 78.0 */
 468                         compatible = "ti,sysc-omap2", "ti,sysc";
 469                         reg = <0xf6000 0x4>,
 470                               <0xf6010 0x4>,
 471                               <0xf6014 0x4>;
 472                         reg-names = "rev", "sysc", "syss";
 473                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 474                                          SYSC_OMAP2_SOFTRESET |
 475                                          SYSC_OMAP2_AUTOIDLE)>;
 476                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 477                                         <SYSC_IDLE_NO>,
 478                                         <SYSC_IDLE_SMART>;
 479                         ti,syss-mask = <1>;
 480                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 481                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
 482                         clock-names = "fck";
 483                         #address-cells = <1>;
 484                         #size-cells = <1>;
 485                         ranges = <0x0 0xf6000 0x1000>;
 486
 487                         hwspinlock: spinlock@0 {
 488                                 compatible = "ti,omap4-hwspinlock";
 489                                 reg = <0x0 0x1000>;
 490                                 #hwlock-cells = <1>;
 491                         };
 492                 };
 493         };
 494
 495         segment@100000 {                                        /* 0x4a100000 */
 496                 compatible = "simple-bus";
 497                 #address-cells = <1>;
 498                 #size-cells = <1>;
 499                 ranges = <0x00002000 0x00102000 0x001000>,      /* ap 27 */
 500                          <0x00003000 0x00103000 0x001000>,      /* ap 28 */
 501                          <0x00008000 0x00108000 0x001000>,      /* ap 29 */
 502                          <0x00009000 0x00109000 0x001000>,      /* ap 30 */
 503                          <0x00040000 0x00140000 0x010000>,      /* ap 31 */
 504                          <0x00050000 0x00150000 0x001000>,      /* ap 32 */
 505                          <0x00051000 0x00151000 0x001000>,      /* ap 33 */
 506                          <0x00052000 0x00152000 0x001000>,      /* ap 34 */
 507                          <0x00053000 0x00153000 0x001000>,      /* ap 35 */
 508                          <0x00054000 0x00154000 0x001000>,      /* ap 36 */
 509                          <0x00055000 0x00155000 0x001000>,      /* ap 37 */
 510                          <0x00056000 0x00156000 0x001000>,      /* ap 38 */
 511                          <0x00057000 0x00157000 0x001000>,      /* ap 39 */
 512                          <0x00058000 0x00158000 0x001000>,      /* ap 40 */
 513                          <0x0005b000 0x0015b000 0x001000>,      /* ap 41 */
 514                          <0x0005c000 0x0015c000 0x001000>,      /* ap 42 */
 515                          <0x0005d000 0x0015d000 0x001000>,      /* ap 45 */
 516                          <0x0005e000 0x0015e000 0x001000>,      /* ap 46 */
 517                          <0x0005f000 0x0015f000 0x001000>,      /* ap 47 */
 518                          <0x00060000 0x00160000 0x001000>,      /* ap 48 */
 519                          <0x00061000 0x00161000 0x001000>,      /* ap 49 */
 520                          <0x00062000 0x00162000 0x001000>,      /* ap 50 */
 521                          <0x00063000 0x00163000 0x001000>,      /* ap 51 */
 522                          <0x00064000 0x00164000 0x001000>,      /* ap 52 */
 523                          <0x00065000 0x00165000 0x001000>,      /* ap 53 */
 524                          <0x00066000 0x00166000 0x001000>,      /* ap 54 */
 525                          <0x00067000 0x00167000 0x001000>,      /* ap 55 */
 526                          <0x00068000 0x00168000 0x001000>,      /* ap 56 */
 527                          <0x0006d000 0x0016d000 0x001000>,      /* ap 57 */
 528                          <0x0006e000 0x0016e000 0x001000>,      /* ap 58 */
 529                          <0x00071000 0x00171000 0x001000>,      /* ap 61 */
 530                          <0x00072000 0x00172000 0x001000>,      /* ap 62 */
 531                          <0x00073000 0x00173000 0x001000>,      /* ap 63 */
 532                          <0x00074000 0x00174000 0x001000>,      /* ap 64 */
 533                          <0x00075000 0x00175000 0x001000>,      /* ap 65 */
 534                          <0x00076000 0x00176000 0x001000>,      /* ap 66 */
 535                          <0x00077000 0x00177000 0x001000>,      /* ap 67 */
 536                          <0x00078000 0x00178000 0x001000>,      /* ap 68 */
 537                          <0x00081000 0x00181000 0x001000>,      /* ap 69 */
 538                          <0x00082000 0x00182000 0x001000>,      /* ap 70 */
 539                          <0x00083000 0x00183000 0x001000>,      /* ap 71 */
 540                          <0x00084000 0x00184000 0x001000>,      /* ap 72 */
 541                          <0x00085000 0x00185000 0x001000>,      /* ap 73 */
 542                          <0x00086000 0x00186000 0x001000>,      /* ap 74 */
 543                          <0x00087000 0x00187000 0x001000>,      /* ap 75 */
 544                          <0x00088000 0x00188000 0x001000>,      /* ap 76 */
 545                          <0x00069000 0x00169000 0x001000>,      /* ap 103 */
 546                          <0x0006a000 0x0016a000 0x001000>,      /* ap 104 */
 547                          <0x00079000 0x00179000 0x001000>,      /* ap 105 */
 548                          <0x0007a000 0x0017a000 0x001000>,      /* ap 106 */
 549                          <0x0006b000 0x0016b000 0x001000>,      /* ap 107 */
 550                          <0x0006c000 0x0016c000 0x001000>,      /* ap 108 */
 551                          <0x0007b000 0x0017b000 0x001000>,      /* ap 121 */
 552                          <0x0007c000 0x0017c000 0x001000>,      /* ap 122 */
 553                          <0x0007d000 0x0017d000 0x001000>,      /* ap 123 */
 554                          <0x0007e000 0x0017e000 0x001000>,      /* ap 124 */
 555                          <0x00059000 0x00159000 0x001000>,      /* ap 125 */
 556                          <0x0005a000 0x0015a000 0x001000>;      /* ap 126 */
 557
 558                 target-module@2000 {                    /* 0x4a102000, ap 27 3c.0 */
 559                         compatible = "ti,sysc";
 560                         status = "disabled";
 561                         #address-cells = <1>;
 562                         #size-cells = <1>;
 563                         ranges = <0x0 0x2000 0x1000>;
 564                 };
 565
 566                 target-module@8000 {                    /* 0x4a108000, ap 29 1e.0 */
 567                         compatible = "ti,sysc";
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <1>;
 571                         ranges = <0x0 0x8000 0x1000>;
 572                 };
 573
 574                 target-module@40000 {                   /* 0x4a140000, ap 31 06.0 */
 575                         compatible = "ti,sysc";
 576                         status = "disabled";
 577                         #address-cells = <1>;
 578                         #size-cells = <1>;
 579                         ranges = <0x0 0x40000 0x10000>;
 580                 };
 581
 582                 target-module@51000 {                   /* 0x4a151000, ap 33 50.0 */
 583                         compatible = "ti,sysc";
 584                         status = "disabled";
 585                         #address-cells = <1>;
 586                         #size-cells = <1>;
 587                         ranges = <0x0 0x51000 0x1000>;
 588                 };
 589
 590                 target-module@53000 {                   /* 0x4a153000, ap 35 54.0 */
 591                         compatible = "ti,sysc";
 592                         status = "disabled";
 593                         #address-cells = <1>;
 594                         #size-cells = <1>;
 595                         ranges = <0x0 0x53000 0x1000>;
 596                 };
 597
 598                 target-module@55000 {                   /* 0x4a155000, ap 37 46.0 */
 599                         compatible = "ti,sysc";
 600                         status = "disabled";
 601                         #address-cells = <1>;
 602                         #size-cells = <1>;
 603                         ranges = <0x0 0x55000 0x1000>;
 604                 };
 605
 606                 target-module@57000 {                   /* 0x4a157000, ap 39 58.0 */
 607                         compatible = "ti,sysc";
 608                         status = "disabled";
 609                         #address-cells = <1>;
 610                         #size-cells = <1>;
 611                         ranges = <0x0 0x57000 0x1000>;
 612                 };
 613
 614                 target-module@59000 {                   /* 0x4a159000, ap 125 6a.0 */
 615                         compatible = "ti,sysc";
 616                         status = "disabled";
 617                         #address-cells = <1>;
 618                         #size-cells = <1>;
 619                         ranges = <0x0 0x59000 0x1000>;
 620                 };
 621
 622                 target-module@5b000 {                   /* 0x4a15b000, ap 41 60.0 */
 623                         compatible = "ti,sysc";
 624                         status = "disabled";
 625                         #address-cells = <1>;
 626                         #size-cells = <1>;
 627                         ranges = <0x0 0x5b000 0x1000>;
 628                 };
 629
 630                 target-module@5d000 {                   /* 0x4a15d000, ap 45 3a.0 */
 631                         compatible = "ti,sysc";
 632                         status = "disabled";
 633                         #address-cells = <1>;
 634                         #size-cells = <1>;
 635                         ranges = <0x0 0x5d000 0x1000>;
 636                 };
 637
 638                 target-module@5f000 {                   /* 0x4a15f000, ap 47 56.0 */
 639                         compatible = "ti,sysc";
 640                         status = "disabled";
 641                         #address-cells = <1>;
 642                         #size-cells = <1>;
 643                         ranges = <0x0 0x5f000 0x1000>;
 644                 };
 645
 646                 target-module@61000 {                   /* 0x4a161000, ap 49 32.0 */
 647                         compatible = "ti,sysc";
 648                         status = "disabled";
 649                         #address-cells = <1>;
 650                         #size-cells = <1>;
 651                         ranges = <0x0 0x61000 0x1000>;
 652                 };
 653
 654                 target-module@63000 {                   /* 0x4a163000, ap 51 5c.0 */
 655                         compatible = "ti,sysc";
 656                         status = "disabled";
 657                         #address-cells = <1>;
 658                         #size-cells = <1>;
 659                         ranges = <0x0 0x63000 0x1000>;
 660                 };
 661
 662                 target-module@65000 {                   /* 0x4a165000, ap 53 4e.0 */
 663                         compatible = "ti,sysc";
 664                         status = "disabled";
 665                         #address-cells = <1>;
 666                         #size-cells = <1>;
 667                         ranges = <0x0 0x65000 0x1000>;
 668                 };
 669
 670                 target-module@67000 {                   /* 0x4a167000, ap 55 5e.0 */
 671                         compatible = "ti,sysc";
 672                         status = "disabled";
 673                         #address-cells = <1>;
 674                         #size-cells = <1>;
 675                         ranges = <0x0 0x67000 0x1000>;
 676                 };
 677
 678                 target-module@69000 {                   /* 0x4a169000, ap 103 4a.0 */
 679                         compatible = "ti,sysc";
 680                         status = "disabled";
 681                         #address-cells = <1>;
 682                         #size-cells = <1>;
 683                         ranges = <0x0 0x69000 0x1000>;
 684                 };
 685
 686                 target-module@6b000 {                   /* 0x4a16b000, ap 107 52.0 */
 687                         compatible = "ti,sysc";
 688                         status = "disabled";
 689                         #address-cells = <1>;
 690                         #size-cells = <1>;
 691                         ranges = <0x0 0x6b000 0x1000>;
 692                 };
 693
 694                 target-module@6d000 {                   /* 0x4a16d000, ap 57 68.0 */
 695                         compatible = "ti,sysc";
 696                         status = "disabled";
 697                         #address-cells = <1>;
 698                         #size-cells = <1>;
 699                         ranges = <0x0 0x6d000 0x1000>;
 700                 };
 701
 702                 target-module@71000 {                   /* 0x4a171000, ap 61 48.0 */
 703                         compatible = "ti,sysc";
 704                         status = "disabled";
 705                         #address-cells = <1>;
 706                         #size-cells = <1>;
 707                         ranges = <0x0 0x71000 0x1000>;
 708                 };
 709
 710                 target-module@73000 {                   /* 0x4a173000, ap 63 2a.0 */
 711                         compatible = "ti,sysc";
 712                         status = "disabled";
 713                         #address-cells = <1>;
 714                         #size-cells = <1>;
 715                         ranges = <0x0 0x73000 0x1000>;
 716                 };
 717
 718                 target-module@75000 {                   /* 0x4a175000, ap 65 64.0 */
 719                         compatible = "ti,sysc";
 720                         status = "disabled";
 721                         #address-cells = <1>;
 722                         #size-cells = <1>;
 723                         ranges = <0x0 0x75000 0x1000>;
 724                 };
 725
 726                 target-module@77000 {                   /* 0x4a177000, ap 67 66.0 */
 727                         compatible = "ti,sysc";
 728                         status = "disabled";
 729                         #address-cells = <1>;
 730                         #size-cells = <1>;
 731                         ranges = <0x0 0x77000 0x1000>;
 732                 };
 733
 734                 target-module@79000 {                   /* 0x4a179000, ap 105 34.0 */
 735                         compatible = "ti,sysc";
 736                         status = "disabled";
 737                         #address-cells = <1>;
 738                         #size-cells = <1>;
 739                         ranges = <0x0 0x79000 0x1000>;
 740                 };
 741
 742                 target-module@7b000 {                   /* 0x4a17b000, ap 121 7c.0 */
 743                         compatible = "ti,sysc";
 744                         status = "disabled";
 745                         #address-cells = <1>;
 746                         #size-cells = <1>;
 747                         ranges = <0x0 0x7b000 0x1000>;
 748                 };
 749
 750                 target-module@7d000 {                   /* 0x4a17d000, ap 123 7e.0 */
 751                         compatible = "ti,sysc";
 752                         status = "disabled";
 753                         #address-cells = <1>;
 754                         #size-cells = <1>;
 755                         ranges = <0x0 0x7d000 0x1000>;
 756                 };
 757
 758                 target-module@81000 {                   /* 0x4a181000, ap 69 26.0 */
 759                         compatible = "ti,sysc";
 760                         status = "disabled";
 761                         #address-cells = <1>;
 762                         #size-cells = <1>;
 763                         ranges = <0x0 0x81000 0x1000>;
 764                 };
 765
 766                 target-module@83000 {                   /* 0x4a183000, ap 71 2e.0 */
 767                         compatible = "ti,sysc";
 768                         status = "disabled";
 769                         #address-cells = <1>;
 770                         #size-cells = <1>;
 771                         ranges = <0x0 0x83000 0x1000>;
 772                 };
 773
 774                 target-module@85000 {                   /* 0x4a185000, ap 73 36.0 */
 775                         compatible = "ti,sysc";
 776                         status = "disabled";
 777                         #address-cells = <1>;
 778                         #size-cells = <1>;
 779                         ranges = <0x0 0x85000 0x1000>;
 780                 };
 781
 782                 target-module@87000 {                   /* 0x4a187000, ap 75 74.0 */
 783                         compatible = "ti,sysc";
 784                         status = "disabled";
 785                         #address-cells = <1>;
 786                         #size-cells = <1>;
 787                         ranges = <0x0 0x87000 0x1000>;
 788                 };
 789         };
 790
 791         segment@200000 {                                        /* 0x4a200000 */
 792                 compatible = "simple-bus";
 793                 #address-cells = <1>;
 794                 #size-cells = <1>;
 795                 ranges = <0x00018000 0x00218000 0x001000>,      /* ap 43 */
 796                          <0x00019000 0x00219000 0x001000>,      /* ap 44 */
 797                          <0x00000000 0x00200000 0x001000>,      /* ap 77 */
 798                          <0x00001000 0x00201000 0x001000>,      /* ap 78 */
 799                          <0x0000a000 0x0020a000 0x001000>,      /* ap 79 */
 800                          <0x0000b000 0x0020b000 0x001000>,      /* ap 80 */
 801                          <0x0000c000 0x0020c000 0x001000>,      /* ap 81 */
 802                          <0x0000d000 0x0020d000 0x001000>,      /* ap 82 */
 803                          <0x0000e000 0x0020e000 0x001000>,      /* ap 83 */
 804                          <0x0000f000 0x0020f000 0x001000>,      /* ap 84 */
 805                          <0x00010000 0x00210000 0x001000>,      /* ap 85 */
 806                          <0x00011000 0x00211000 0x001000>,      /* ap 86 */
 807                          <0x00012000 0x00212000 0x001000>,      /* ap 87 */
 808                          <0x00013000 0x00213000 0x001000>,      /* ap 88 */
 809                          <0x00014000 0x00214000 0x001000>,      /* ap 89 */
 810                          <0x00015000 0x00215000 0x001000>,      /* ap 90 */
 811                          <0x0002a000 0x0022a000 0x001000>,      /* ap 91 */
 812                          <0x0002b000 0x0022b000 0x001000>,      /* ap 92 */
 813                          <0x0001c000 0x0021c000 0x001000>,      /* ap 93 */
 814                          <0x0001d000 0x0021d000 0x001000>,      /* ap 94 */
 815                          <0x0001e000 0x0021e000 0x001000>,      /* ap 95 */
 816                          <0x0001f000 0x0021f000 0x001000>,      /* ap 96 */
 817                          <0x00020000 0x00220000 0x001000>,      /* ap 97 */
 818                          <0x00021000 0x00221000 0x001000>,      /* ap 98 */
 819                          <0x00024000 0x00224000 0x001000>,      /* ap 99 */
 820                          <0x00025000 0x00225000 0x001000>,      /* ap 100 */
 821                          <0x00026000 0x00226000 0x001000>,      /* ap 101 */
 822                          <0x00027000 0x00227000 0x001000>,      /* ap 102 */
 823                          <0x0002c000 0x0022c000 0x001000>,      /* ap 109 */
 824                          <0x0002d000 0x0022d000 0x001000>,      /* ap 110 */
 825                          <0x0002e000 0x0022e000 0x001000>,      /* ap 111 */
 826                          <0x0002f000 0x0022f000 0x001000>,      /* ap 112 */
 827                          <0x00030000 0x00230000 0x001000>,      /* ap 113 */
 828                          <0x00031000 0x00231000 0x001000>,      /* ap 114 */
 829                          <0x00032000 0x00232000 0x001000>,      /* ap 115 */
 830                          <0x00033000 0x00233000 0x001000>,      /* ap 116 */
 831                          <0x00034000 0x00234000 0x001000>,      /* ap 117 */
 832                          <0x00035000 0x00235000 0x001000>,      /* ap 118 */
 833                          <0x00036000 0x00236000 0x001000>,      /* ap 119 */
 834                          <0x00037000 0x00237000 0x001000>,      /* ap 120 */
 835                          <0x0001a000 0x0021a000 0x001000>,      /* ap 127 */
 836                          <0x0001b000 0x0021b000 0x001000>;      /* ap 128 */
 837
 838                 target-module@0 {                       /* 0x4a200000, ap 77 3e.0 */
 839                         compatible = "ti,sysc";
 840                         status = "disabled";
 841                         #address-cells = <1>;
 842                         #size-cells = <1>;
 843                         ranges = <0x0 0x0 0x1000>;
 844                 };
 845
 846                 target-module@a000 {                    /* 0x4a20a000, ap 79 30.0 */
 847                         compatible = "ti,sysc";
 848                         status = "disabled";
 849                         #address-cells = <1>;
 850                         #size-cells = <1>;
 851                         ranges = <0x0 0xa000 0x1000>;
 852                 };
 853
 854                 target-module@c000 {                    /* 0x4a20c000, ap 81 0c.0 */
 855                         compatible = "ti,sysc";
 856                         status = "disabled";
 857                         #address-cells = <1>;
 858                         #size-cells = <1>;
 859                         ranges = <0x0 0xc000 0x1000>;
 860                 };
 861
 862                 target-module@e000 {                    /* 0x4a20e000, ap 83 22.0 */
 863                         compatible = "ti,sysc";
 864                         status = "disabled";
 865                         #address-cells = <1>;
 866                         #size-cells = <1>;
 867                         ranges = <0x0 0xe000 0x1000>;
 868                 };
 869
 870                 target-module@10000 {                   /* 0x4a210000, ap 85 14.0 */
 871                         compatible = "ti,sysc";
 872                         status = "disabled";
 873                         #address-cells = <1>;
 874                         #size-cells = <1>;
 875                         ranges = <0x0 0x10000 0x1000>;
 876                 };
 877
 878                 target-module@12000 {                   /* 0x4a212000, ap 87 16.0 */
 879                         compatible = "ti,sysc";
 880                         status = "disabled";
 881                         #address-cells = <1>;
 882                         #size-cells = <1>;
 883                         ranges = <0x0 0x12000 0x1000>;
 884                 };
 885
 886                 target-module@14000 {                   /* 0x4a214000, ap 89 1c.0 */
 887                         compatible = "ti,sysc";
 888                         status = "disabled";
 889                         #address-cells = <1>;
 890                         #size-cells = <1>;
 891                         ranges = <0x0 0x14000 0x1000>;
 892                 };
 893
 894                 target-module@18000 {                   /* 0x4a218000, ap 43 12.0 */
 895                         compatible = "ti,sysc";
 896                         status = "disabled";
 897                         #address-cells = <1>;
 898                         #size-cells = <1>;
 899                         ranges = <0x0 0x18000 0x1000>;
 900                 };
 901
 902                 target-module@1a000 {                   /* 0x4a21a000, ap 127 7a.0 */
 903                         compatible = "ti,sysc";
 904                         status = "disabled";
 905                         #address-cells = <1>;
 906                         #size-cells = <1>;
 907                         ranges = <0x0 0x1a000 0x1000>;
 908                 };
 909
 910                 target-module@1c000 {                   /* 0x4a21c000, ap 93 38.0 */
 911                         compatible = "ti,sysc";
 912                         status = "disabled";
 913                         #address-cells = <1>;
 914                         #size-cells = <1>;
 915                         ranges = <0x0 0x1c000 0x1000>;
 916                 };
 917
 918                 target-module@1e000 {                   /* 0x4a21e000, ap 95 0a.0 */
 919                         compatible = "ti,sysc";
 920                         status = "disabled";
 921                         #address-cells = <1>;
 922                         #size-cells = <1>;
 923                         ranges = <0x0 0x1e000 0x1000>;
 924                 };
 925
 926                 target-module@20000 {                   /* 0x4a220000, ap 97 24.0 */
 927                         compatible = "ti,sysc";
 928                         status = "disabled";
 929                         #address-cells = <1>;
 930                         #size-cells = <1>;
 931                         ranges = <0x0 0x20000 0x1000>;
 932                 };
 933
 934                 target-module@24000 {                   /* 0x4a224000, ap 99 44.0 */
 935                         compatible = "ti,sysc";
 936                         status = "disabled";
 937                         #address-cells = <1>;
 938                         #size-cells = <1>;
 939                         ranges = <0x0 0x24000 0x1000>;
 940                 };
 941
 942                 target-module@26000 {                   /* 0x4a226000, ap 101 2c.0 */
 943                         compatible = "ti,sysc";
 944                         status = "disabled";
 945                         #address-cells = <1>;
 946                         #size-cells = <1>;
 947                         ranges = <0x0 0x26000 0x1000>;
 948                 };
 949
 950                 target-module@2a000 {                   /* 0x4a22a000, ap 91 4c.0 */
 951                         compatible = "ti,sysc";
 952                         status = "disabled";
 953                         #address-cells = <1>;
 954                         #size-cells = <1>;
 955                         ranges = <0x0 0x2a000 0x1000>;
 956                 };
 957
 958                 target-module@2c000 {                   /* 0x4a22c000, ap 109 6c.0 */
 959                         compatible = "ti,sysc";
 960                         status = "disabled";
 961                         #address-cells = <1>;
 962                         #size-cells = <1>;
 963                         ranges = <0x0 0x2c000 0x1000>;
 964                 };
 965
 966                 target-module@2e000 {                   /* 0x4a22e000, ap 111 6e.0 */
 967                         compatible = "ti,sysc";
 968                         status = "disabled";
 969                         #address-cells = <1>;
 970                         #size-cells = <1>;
 971                         ranges = <0x0 0x2e000 0x1000>;
 972                 };
 973
 974                 target-module@30000 {                   /* 0x4a230000, ap 113 70.0 */
 975                         compatible = "ti,sysc";
 976                         status = "disabled";
 977                         #address-cells = <1>;
 978                         #size-cells = <1>;
 979                         ranges = <0x0 0x30000 0x1000>;
 980                 };
 981
 982                 target-module@32000 {                   /* 0x4a232000, ap 115 5a.0 */
 983                         compatible = "ti,sysc";
 984                         status = "disabled";
 985                         #address-cells = <1>;
 986                         #size-cells = <1>;
 987                         ranges = <0x0 0x32000 0x1000>;
 988                 };
 989
 990                 target-module@34000 {                   /* 0x4a234000, ap 117 76.1 */
 991                         compatible = "ti,sysc";
 992                         status = "disabled";
 993                         #address-cells = <1>;
 994                         #size-cells = <1>;
 995                         ranges = <0x0 0x34000 0x1000>;
 996                 };
 997
 998                 target-module@36000 {                   /* 0x4a236000, ap 119 62.0 */
 999                         compatible = "ti,sysc";
1000                         status = "disabled";
1001                         #address-cells = <1>;
1002                         #size-cells = <1>;
1003                         ranges = <0x0 0x36000 0x1000>;
1004                 };
1005         };
1006 };
1007
1008 &l4_per1 {                                              /* 0x48000000 */
1009         compatible = "ti,dra7-l4-per1", "simple-bus";
1010         reg = <0x48000000 0x800>,
1011               <0x48000800 0x800>,
1012               <0x48001000 0x400>,
1013               <0x48001400 0x400>,
1014               <0x48001800 0x400>,
1015               <0x48001c00 0x400>;
1016         reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1017         #address-cells = <1>;
1018         #size-cells = <1>;
1019         ranges = <0x00000000 0x48000000 0x200000>,      /* segment 0 */
1020                  <0x00200000 0x48200000 0x200000>;      /* segment 1 */
1021
1022         segment@0 {                                     /* 0x48000000 */
1023                 compatible = "simple-bus";
1024                 #address-cells = <1>;
1025                 #size-cells = <1>;
1026                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
1027                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
1028                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
1029                          <0x00020000 0x00020000 0x001000>,      /* ap 3 */
1030                          <0x00021000 0x00021000 0x001000>,      /* ap 4 */
1031                          <0x00032000 0x00032000 0x001000>,      /* ap 5 */
1032                          <0x00033000 0x00033000 0x001000>,      /* ap 6 */
1033                          <0x00034000 0x00034000 0x001000>,      /* ap 7 */
1034                          <0x00035000 0x00035000 0x001000>,      /* ap 8 */
1035                          <0x00036000 0x00036000 0x001000>,      /* ap 9 */
1036                          <0x00037000 0x00037000 0x001000>,      /* ap 10 */
1037                          <0x0003e000 0x0003e000 0x001000>,      /* ap 11 */
1038                          <0x0003f000 0x0003f000 0x001000>,      /* ap 12 */
1039                          <0x00055000 0x00055000 0x001000>,      /* ap 13 */
1040                          <0x00056000 0x00056000 0x001000>,      /* ap 14 */
1041                          <0x00057000 0x00057000 0x001000>,      /* ap 15 */
1042                          <0x00058000 0x00058000 0x001000>,      /* ap 16 */
1043                          <0x00059000 0x00059000 0x001000>,      /* ap 17 */
1044                          <0x0005a000 0x0005a000 0x001000>,      /* ap 18 */
1045                          <0x0005b000 0x0005b000 0x001000>,      /* ap 19 */
1046                          <0x0005c000 0x0005c000 0x001000>,      /* ap 20 */
1047                          <0x0005d000 0x0005d000 0x001000>,      /* ap 21 */
1048                          <0x0005e000 0x0005e000 0x001000>,      /* ap 22 */
1049                          <0x00060000 0x00060000 0x001000>,      /* ap 23 */
1050                          <0x0006a000 0x0006a000 0x001000>,      /* ap 24 */
1051                          <0x0006b000 0x0006b000 0x001000>,      /* ap 25 */
1052                          <0x0006c000 0x0006c000 0x001000>,      /* ap 26 */
1053                          <0x0006d000 0x0006d000 0x001000>,      /* ap 27 */
1054                          <0x0006e000 0x0006e000 0x001000>,      /* ap 28 */
1055                          <0x0006f000 0x0006f000 0x001000>,      /* ap 29 */
1056                          <0x00070000 0x00070000 0x001000>,      /* ap 30 */
1057                          <0x00071000 0x00071000 0x001000>,      /* ap 31 */
1058                          <0x00072000 0x00072000 0x001000>,      /* ap 32 */
1059                          <0x00073000 0x00073000 0x001000>,      /* ap 33 */
1060                          <0x00061000 0x00061000 0x001000>,      /* ap 34 */
1061                          <0x00053000 0x00053000 0x001000>,      /* ap 35 */
1062                          <0x00054000 0x00054000 0x001000>,      /* ap 36 */
1063                          <0x000b2000 0x000b2000 0x001000>,      /* ap 37 */
1064                          <0x000b3000 0x000b3000 0x001000>,      /* ap 38 */
1065                          <0x00078000 0x00078000 0x001000>,      /* ap 39 */
1066                          <0x00079000 0x00079000 0x001000>,      /* ap 40 */
1067                          <0x00086000 0x00086000 0x001000>,      /* ap 41 */
1068                          <0x00087000 0x00087000 0x001000>,      /* ap 42 */
1069                          <0x00088000 0x00088000 0x001000>,      /* ap 43 */
1070                          <0x00089000 0x00089000 0x001000>,      /* ap 44 */
1071                          <0x00051000 0x00051000 0x001000>,      /* ap 45 */
1072                          <0x00052000 0x00052000 0x001000>,      /* ap 46 */
1073                          <0x00098000 0x00098000 0x001000>,      /* ap 47 */
1074                          <0x00099000 0x00099000 0x001000>,      /* ap 48 */
1075                          <0x0009a000 0x0009a000 0x001000>,      /* ap 49 */
1076                          <0x0009b000 0x0009b000 0x001000>,      /* ap 50 */
1077                          <0x0009c000 0x0009c000 0x001000>,      /* ap 51 */
1078                          <0x0009d000 0x0009d000 0x001000>,      /* ap 52 */
1079                          <0x00068000 0x00068000 0x001000>,      /* ap 53 */
1080                          <0x00069000 0x00069000 0x001000>,      /* ap 54 */
1081                          <0x00090000 0x00090000 0x002000>,      /* ap 55 */
1082                          <0x00092000 0x00092000 0x001000>,      /* ap 56 */
1083                          <0x000a4000 0x000a4000 0x001000>,      /* ap 57 */
1084                          <0x000a6000 0x000a6000 0x001000>,      /* ap 58 */
1085                          <0x000a8000 0x000a8000 0x004000>,      /* ap 59 */
1086                          <0x000ac000 0x000ac000 0x001000>,      /* ap 60 */
1087                          <0x000ad000 0x000ad000 0x001000>,      /* ap 61 */
1088                          <0x000ae000 0x000ae000 0x001000>,      /* ap 62 */
1089                          <0x00066000 0x00066000 0x001000>,      /* ap 63 */
1090                          <0x00067000 0x00067000 0x001000>,      /* ap 64 */
1091                          <0x000b4000 0x000b4000 0x001000>,      /* ap 65 */
1092                          <0x000b5000 0x000b5000 0x001000>,      /* ap 66 */
1093                          <0x000b8000 0x000b8000 0x001000>,      /* ap 67 */
1094                          <0x000b9000 0x000b9000 0x001000>,      /* ap 68 */
1095                          <0x000ba000 0x000ba000 0x001000>,      /* ap 69 */
1096                          <0x000bb000 0x000bb000 0x001000>,      /* ap 70 */
1097                          <0x000d1000 0x000d1000 0x001000>,      /* ap 71 */
1098                          <0x000d2000 0x000d2000 0x001000>,      /* ap 72 */
1099                          <0x000d5000 0x000d5000 0x001000>,      /* ap 73 */
1100                          <0x000d6000 0x000d6000 0x001000>,      /* ap 74 */
1101                          <0x000a2000 0x000a2000 0x001000>,      /* ap 75 */
1102                          <0x000a3000 0x000a3000 0x001000>,      /* ap 76 */
1103                          <0x00001400 0x00001400 0x000400>,      /* ap 77 */
1104                          <0x00001800 0x00001800 0x000400>,      /* ap 78 */
1105                          <0x00001c00 0x00001c00 0x000400>,      /* ap 79 */
1106                          <0x000a5000 0x000a5000 0x001000>,      /* ap 80 */
1107                          <0x0007a000 0x0007a000 0x001000>,      /* ap 81 */
1108                          <0x0007b000 0x0007b000 0x001000>,      /* ap 82 */
1109                          <0x0007c000 0x0007c000 0x001000>,      /* ap 83 */
1110                          <0x0007d000 0x0007d000 0x001000>;      /* ap 84 */
1111
1112                 target-module@20000 {                   /* 0x48020000, ap 3 04.0 */
1113                         compatible = "ti,sysc-omap2", "ti,sysc";
1114                         reg = <0x20050 0x4>,
1115                               <0x20054 0x4>,
1116                               <0x20058 0x4>;
1117                         reg-names = "rev", "sysc", "syss";
1118                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1119                                          SYSC_OMAP2_SOFTRESET |
1120                                          SYSC_OMAP2_AUTOIDLE)>;
1121                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1122                                         <SYSC_IDLE_NO>,
1123                                         <SYSC_IDLE_SMART>,
1124                                         <SYSC_IDLE_SMART_WKUP>;
1125                         ti,syss-mask = <1>;
1126                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1127                         clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1128                         clock-names = "fck";
1129                         #address-cells = <1>;
1130                         #size-cells = <1>;
1131                         ranges = <0x0 0x20000 0x1000>;
1132
1133                         uart3: serial@0 {
1134                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1135                                 reg = <0x0 0x100>;
1136                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1137                                 clock-frequency = <48000000>;
1138                                 status = "disabled";
1139                                 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1140                                 dma-names = "tx", "rx";
1141                         };
1142                 };
1143
1144                 target-module@32000 {                   /* 0x48032000, ap 5 3e.0 */
1145                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1146                         ti,hwmods = "timer2";
1147                         reg = <0x32000 0x4>,
1148                               <0x32010 0x4>;
1149                         reg-names = "rev", "sysc";
1150                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1151                                          SYSC_OMAP4_SOFTRESET)>;
1152                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1153                                         <SYSC_IDLE_NO>,
1154                                         <SYSC_IDLE_SMART>,
1155                                         <SYSC_IDLE_SMART_WKUP>;
1156                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1157                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1158                         clock-names = "fck";
1159                         #address-cells = <1>;
1160                         #size-cells = <1>;
1161                         ranges = <0x0 0x32000 0x1000>;
1162
1163                         timer2: timer@0 {
1164                                 compatible = "ti,omap5430-timer";
1165                                 reg = <0x0 0x80>;
1166                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
1167                                 clock-names = "fck";
1168                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1169                         };
1170                 };
1171
1172                 target-module@34000 {                   /* 0x48034000, ap 7 46.0 */
1173                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1174                         ti,hwmods = "timer3";
1175                         reg = <0x34000 0x4>,
1176                               <0x34010 0x4>;
1177                         reg-names = "rev", "sysc";
1178                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1179                                          SYSC_OMAP4_SOFTRESET)>;
1180                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1181                                         <SYSC_IDLE_NO>,
1182                                         <SYSC_IDLE_SMART>,
1183                                         <SYSC_IDLE_SMART_WKUP>;
1184                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1185                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1186                         clock-names = "fck";
1187                         #address-cells = <1>;
1188                         #size-cells = <1>;
1189                         ranges = <0x0 0x34000 0x1000>;
1190
1191                         timer3: timer@0 {
1192                                 compatible = "ti,omap5430-timer";
1193                                 reg = <0x0 0x80>;
1194                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1195                                 clock-names = "fck";
1196                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1197                         };
1198                 };
1199
1200                 target-module@36000 {                   /* 0x48036000, ap 9 4e.0 */
1201                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1202                         ti,hwmods = "timer4";
1203                         reg = <0x36000 0x4>,
1204                               <0x36010 0x4>;
1205                         reg-names = "rev", "sysc";
1206                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1207                                          SYSC_OMAP4_SOFTRESET)>;
1208                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1209                                         <SYSC_IDLE_NO>,
1210                                         <SYSC_IDLE_SMART>,
1211                                         <SYSC_IDLE_SMART_WKUP>;
1212                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1213                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1214                         clock-names = "fck";
1215                         #address-cells = <1>;
1216                         #size-cells = <1>;
1217                         ranges = <0x0 0x36000 0x1000>;
1218
1219                         timer4: timer@0 {
1220                                 compatible = "ti,omap5430-timer";
1221                                 reg = <0x0 0x80>;
1222                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1223                                 clock-names = "fck";
1224                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1225                         };
1226                 };
1227
1228                 target-module@3e000 {                   /* 0x4803e000, ap 11 56.0 */
1229                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1230                         reg = <0x3e000 0x4>,
1231                               <0x3e010 0x4>;
1232                         reg-names = "rev", "sysc";
1233                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1234                                          SYSC_OMAP4_SOFTRESET)>;
1235                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1236                                         <SYSC_IDLE_NO>,
1237                                         <SYSC_IDLE_SMART>,
1238                                         <SYSC_IDLE_SMART_WKUP>;
1239                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1240                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1241                         clock-names = "fck";
1242                         #address-cells = <1>;
1243                         #size-cells = <1>;
1244                         ranges = <0x0 0x3e000 0x1000>;
1245
1246                         timer9: timer@0 {
1247                                 compatible = "ti,omap5430-timer";
1248                                 reg = <0x0 0x80>;
1249                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
1250                                 clock-names = "fck";
1251                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1252                         };
1253                 };
1254
1255                 gpio7_target: target-module@51000 {             /* 0x48051000, ap 45 2e.0 */
1256                         compatible = "ti,sysc-omap2", "ti,sysc";
1257                         reg = <0x51000 0x4>,
1258                               <0x51010 0x4>,
1259                               <0x51114 0x4>;
1260                         reg-names = "rev", "sysc", "syss";
1261                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1262                                          SYSC_OMAP2_SOFTRESET |
1263                                          SYSC_OMAP2_AUTOIDLE)>;
1264                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1265                                         <SYSC_IDLE_NO>,
1266                                         <SYSC_IDLE_SMART>,
1267                                         <SYSC_IDLE_SMART_WKUP>;
1268                         ti,syss-mask = <1>;
1269                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1270                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1271                                  <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1272                         clock-names = "fck", "dbclk";
1273                         #address-cells = <1>;
1274                         #size-cells = <1>;
1275                         ranges = <0x0 0x51000 0x1000>;
1276
1277                         gpio7: gpio@0 {
1278                                 compatible = "ti,omap4-gpio";
1279                                 reg = <0x0 0x200>;
1280                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1281                                 gpio-controller;
1282                                 #gpio-cells = <2>;
1283                                 interrupt-controller;
1284                                 #interrupt-cells = <2>;
1285                         };
1286                 };
1287
1288                 target-module@53000 {                   /* 0x48053000, ap 35 36.0 */
1289                         compatible = "ti,sysc-omap2", "ti,sysc";
1290                         reg = <0x53000 0x4>,
1291                               <0x53010 0x4>,
1292                               <0x53114 0x4>;
1293                         reg-names = "rev", "sysc", "syss";
1294                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1295                                          SYSC_OMAP2_SOFTRESET |
1296                                          SYSC_OMAP2_AUTOIDLE)>;
1297                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1298                                         <SYSC_IDLE_NO>,
1299                                         <SYSC_IDLE_SMART>,
1300                                         <SYSC_IDLE_SMART_WKUP>;
1301                         ti,syss-mask = <1>;
1302                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1303                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1304                                  <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1305                         clock-names = "fck", "dbclk";
1306                         #address-cells = <1>;
1307                         #size-cells = <1>;
1308                         ranges = <0x0 0x53000 0x1000>;
1309
1310                         gpio8: gpio@0 {
1311                                 compatible = "ti,omap4-gpio";
1312                                 reg = <0x0 0x200>;
1313                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1314                                 gpio-controller;
1315                                 #gpio-cells = <2>;
1316                                 interrupt-controller;
1317                                 #interrupt-cells = <2>;
1318                         };
1319                 };
1320
1321                 target-module@55000 {                   /* 0x48055000, ap 13 0e.0 */
1322                         compatible = "ti,sysc-omap2", "ti,sysc";
1323                         reg = <0x55000 0x4>,
1324                               <0x55010 0x4>,
1325                               <0x55114 0x4>;
1326                         reg-names = "rev", "sysc", "syss";
1327                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1328                                          SYSC_OMAP2_SOFTRESET |
1329                                          SYSC_OMAP2_AUTOIDLE)>;
1330                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1331                                         <SYSC_IDLE_NO>,
1332                                         <SYSC_IDLE_SMART>,
1333                                         <SYSC_IDLE_SMART_WKUP>;
1334                         ti,syss-mask = <1>;
1335                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1336                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1337                                  <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1338                         clock-names = "fck", "dbclk";
1339                         #address-cells = <1>;
1340                         #size-cells = <1>;
1341                         ranges = <0x0 0x55000 0x1000>;
1342
1343                         gpio2: gpio@0 {
1344                                 compatible = "ti,omap4-gpio";
1345                                 reg = <0x0 0x200>;
1346                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1347                                 gpio-controller;
1348                                 #gpio-cells = <2>;
1349                                 interrupt-controller;
1350                                 #interrupt-cells = <2>;
1351                         };
1352                 };
1353
1354                 target-module@57000 {                   /* 0x48057000, ap 15 06.0 */
1355                         compatible = "ti,sysc-omap2", "ti,sysc";
1356                         reg = <0x57000 0x4>,
1357                               <0x57010 0x4>,
1358                               <0x57114 0x4>;
1359                         reg-names = "rev", "sysc", "syss";
1360                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1361                                          SYSC_OMAP2_SOFTRESET |
1362                                          SYSC_OMAP2_AUTOIDLE)>;
1363                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1364                                         <SYSC_IDLE_NO>,
1365                                         <SYSC_IDLE_SMART>,
1366                                         <SYSC_IDLE_SMART_WKUP>;
1367                         ti,syss-mask = <1>;
1368                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1369                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1370                                  <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1371                         clock-names = "fck", "dbclk";
1372                         #address-cells = <1>;
1373                         #size-cells = <1>;
1374                         ranges = <0x0 0x57000 0x1000>;
1375
1376                         gpio3: gpio@0 {
1377                                 compatible = "ti,omap4-gpio";
1378                                 reg = <0x0 0x200>;
1379                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1380                                 gpio-controller;
1381                                 #gpio-cells = <2>;
1382                                 interrupt-controller;
1383                                 #interrupt-cells = <2>;
1384                         };
1385                 };
1386
1387                 target-module@59000 {                   /* 0x48059000, ap 17 16.0 */
1388                         compatible = "ti,sysc-omap2", "ti,sysc";
1389                         reg = <0x59000 0x4>,
1390                               <0x59010 0x4>,
1391                               <0x59114 0x4>;
1392                         reg-names = "rev", "sysc", "syss";
1393                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1394                                          SYSC_OMAP2_SOFTRESET |
1395                                          SYSC_OMAP2_AUTOIDLE)>;
1396                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1397                                         <SYSC_IDLE_NO>,
1398                                         <SYSC_IDLE_SMART>,
1399                                         <SYSC_IDLE_SMART_WKUP>;
1400                         ti,syss-mask = <1>;
1401                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1402                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1403                                  <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1404                         clock-names = "fck", "dbclk";
1405                         #address-cells = <1>;
1406                         #size-cells = <1>;
1407                         ranges = <0x0 0x59000 0x1000>;
1408
1409                         gpio4: gpio@0 {
1410                                 compatible = "ti,omap4-gpio";
1411                                 reg = <0x0 0x200>;
1412                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1413                                 gpio-controller;
1414                                 #gpio-cells = <2>;
1415                                 interrupt-controller;
1416                                 #interrupt-cells = <2>;
1417                         };
1418                 };
1419
1420                 target-module@5b000 {                   /* 0x4805b000, ap 19 1e.0 */
1421                         compatible = "ti,sysc-omap2", "ti,sysc";
1422                         reg = <0x5b000 0x4>,
1423                               <0x5b010 0x4>,
1424                               <0x5b114 0x4>;
1425                         reg-names = "rev", "sysc", "syss";
1426                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1427                                          SYSC_OMAP2_SOFTRESET |
1428                                          SYSC_OMAP2_AUTOIDLE)>;
1429                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1430                                         <SYSC_IDLE_NO>,
1431                                         <SYSC_IDLE_SMART>,
1432                                         <SYSC_IDLE_SMART_WKUP>;
1433                         ti,syss-mask = <1>;
1434                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1435                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1436                                  <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1437                         clock-names = "fck", "dbclk";
1438                         #address-cells = <1>;
1439                         #size-cells = <1>;
1440                         ranges = <0x0 0x5b000 0x1000>;
1441
1442                         gpio5: gpio@0 {
1443                                 compatible = "ti,omap4-gpio";
1444                                 reg = <0x0 0x200>;
1445                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1446                                 gpio-controller;
1447                                 #gpio-cells = <2>;
1448                                 interrupt-controller;
1449                                 #interrupt-cells = <2>;
1450                         };
1451                 };
1452
1453                 target-module@5d000 {                   /* 0x4805d000, ap 21 26.0 */
1454                         compatible = "ti,sysc-omap2", "ti,sysc";
1455                         reg = <0x5d000 0x4>,
1456                               <0x5d010 0x4>,
1457                               <0x5d114 0x4>;
1458                         reg-names = "rev", "sysc", "syss";
1459                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1460                                          SYSC_OMAP2_SOFTRESET |
1461                                          SYSC_OMAP2_AUTOIDLE)>;
1462                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1463                                         <SYSC_IDLE_NO>,
1464                                         <SYSC_IDLE_SMART>,
1465                                         <SYSC_IDLE_SMART_WKUP>;
1466                         ti,syss-mask = <1>;
1467                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1468                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1469                                  <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1470                         clock-names = "fck", "dbclk";
1471                         #address-cells = <1>;
1472                         #size-cells = <1>;
1473                         ranges = <0x0 0x5d000 0x1000>;
1474
1475                         gpio6: gpio@0 {
1476                                 compatible = "ti,omap4-gpio";
1477                                 reg = <0x0 0x200>;
1478                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1479                                 gpio-controller;
1480                                 #gpio-cells = <2>;
1481                                 interrupt-controller;
1482                                 #interrupt-cells = <2>;
1483                         };
1484                 };
1485
1486                 target-module@60000 {                   /* 0x48060000, ap 23 32.0 */
1487                         compatible = "ti,sysc-omap2", "ti,sysc";
1488                         reg = <0x60000 0x8>,
1489                               <0x60010 0x8>,
1490                               <0x60090 0x8>;
1491                         reg-names = "rev", "sysc", "syss";
1492                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1493                                          SYSC_OMAP2_ENAWAKEUP |
1494                                          SYSC_OMAP2_SOFTRESET |
1495                                          SYSC_OMAP2_AUTOIDLE)>;
1496                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1497                                         <SYSC_IDLE_NO>,
1498                                         <SYSC_IDLE_SMART>,
1499                                         <SYSC_IDLE_SMART_WKUP>;
1500                         ti,syss-mask = <1>;
1501                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1502                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1503                         clock-names = "fck";
1504                         #address-cells = <1>;
1505                         #size-cells = <1>;
1506                         ranges = <0x0 0x60000 0x1000>;
1507
1508                         i2c3: i2c@0 {
1509                                 compatible = "ti,omap4-i2c";
1510                                 reg = <0x0 0x100>;
1511                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1512                                 #address-cells = <1>;
1513                                 #size-cells = <0>;
1514                                 status = "disabled";
1515                         };
1516                 };
1517
1518                 target-module@66000 {                   /* 0x48066000, ap 63 14.0 */
1519                         compatible = "ti,sysc-omap2", "ti,sysc";
1520                         reg = <0x66050 0x4>,
1521                               <0x66054 0x4>,
1522                               <0x66058 0x4>;
1523                         reg-names = "rev", "sysc", "syss";
1524                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1525                                          SYSC_OMAP2_SOFTRESET |
1526                                          SYSC_OMAP2_AUTOIDLE)>;
1527                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1528                                         <SYSC_IDLE_NO>,
1529                                         <SYSC_IDLE_SMART>,
1530                                         <SYSC_IDLE_SMART_WKUP>;
1531                         ti,syss-mask = <1>;
1532                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1533                         clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1534                         clock-names = "fck";
1535                         #address-cells = <1>;
1536                         #size-cells = <1>;
1537                         ranges = <0x0 0x66000 0x1000>;
1538
1539                         uart5: serial@0 {
1540                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1541                                 reg = <0x0 0x100>;
1542                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1543                                 clock-frequency = <48000000>;
1544                                 status = "disabled";
1545                                 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1546                                 dma-names = "tx", "rx";
1547                         };
1548                 };
1549
1550                 target-module@68000 {                   /* 0x48068000, ap 53 1c.0 */
1551                         compatible = "ti,sysc-omap2", "ti,sysc";
1552                         reg = <0x68050 0x4>,
1553                               <0x68054 0x4>,
1554                               <0x68058 0x4>;
1555                         reg-names = "rev", "sysc", "syss";
1556                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1557                                          SYSC_OMAP2_SOFTRESET |
1558                                          SYSC_OMAP2_AUTOIDLE)>;
1559                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1560                                         <SYSC_IDLE_NO>,
1561                                         <SYSC_IDLE_SMART>,
1562                                         <SYSC_IDLE_SMART_WKUP>;
1563                         ti,syss-mask = <1>;
1564                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1565                         clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1566                         clock-names = "fck";
1567                         #address-cells = <1>;
1568                         #size-cells = <1>;
1569                         ranges = <0x0 0x68000 0x1000>;
1570
1571                         uart6: serial@0 {
1572                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1573                                 reg = <0x0 0x100>;
1574                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1575                                 clock-frequency = <48000000>;
1576                                 status = "disabled";
1577                                 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1578                                 dma-names = "tx", "rx";
1579                         };
1580                 };
1581
1582                 target-module@6a000 {                   /* 0x4806a000, ap 24 24.0 */
1583                         compatible = "ti,sysc-omap2", "ti,sysc";
1584                         reg = <0x6a050 0x4>,
1585                               <0x6a054 0x4>,
1586                               <0x6a058 0x4>;
1587                         reg-names = "rev", "sysc", "syss";
1588                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1589                                          SYSC_OMAP2_SOFTRESET |
1590                                          SYSC_OMAP2_AUTOIDLE)>;
1591                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1592                                         <SYSC_IDLE_NO>,
1593                                         <SYSC_IDLE_SMART>,
1594                                         <SYSC_IDLE_SMART_WKUP>;
1595                         ti,syss-mask = <1>;
1596                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1597                         clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1598                         clock-names = "fck";
1599                         #address-cells = <1>;
1600                         #size-cells = <1>;
1601                         ranges = <0x0 0x6a000 0x1000>;
1602
1603                         uart1: serial@0 {
1604                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1605                                 reg = <0x0 0x100>;
1606                                 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1607                                 clock-frequency = <48000000>;
1608                                 status = "disabled";
1609                                 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1610                                 dma-names = "tx", "rx";
1611                         };
1612                 };
1613
1614                 target-module@6c000 {                   /* 0x4806c000, ap 26 2c.0 */
1615                         compatible = "ti,sysc-omap2", "ti,sysc";
1616                         reg = <0x6c050 0x4>,
1617                               <0x6c054 0x4>,
1618                               <0x6c058 0x4>;
1619                         reg-names = "rev", "sysc", "syss";
1620                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1621                                          SYSC_OMAP2_SOFTRESET |
1622                                          SYSC_OMAP2_AUTOIDLE)>;
1623                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1624                                         <SYSC_IDLE_NO>,
1625                                         <SYSC_IDLE_SMART>,
1626                                         <SYSC_IDLE_SMART_WKUP>;
1627                         ti,syss-mask = <1>;
1628                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1629                         clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1630                         clock-names = "fck";
1631                         #address-cells = <1>;
1632                         #size-cells = <1>;
1633                         ranges = <0x0 0x6c000 0x1000>;
1634
1635                         uart2: serial@0 {
1636                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1637                                 reg = <0x0 0x100>;
1638                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1639                                 clock-frequency = <48000000>;
1640                                 status = "disabled";
1641                                 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1642                                 dma-names = "tx", "rx";
1643                         };
1644                 };
1645
1646                 target-module@6e000 {                   /* 0x4806e000, ap 28 0c.1 */
1647                         compatible = "ti,sysc-omap2", "ti,sysc";
1648                         reg = <0x6e050 0x4>,
1649                               <0x6e054 0x4>,
1650                               <0x6e058 0x4>;
1651                         reg-names = "rev", "sysc", "syss";
1652                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1653                                          SYSC_OMAP2_SOFTRESET |
1654                                          SYSC_OMAP2_AUTOIDLE)>;
1655                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1656                                         <SYSC_IDLE_NO>,
1657                                         <SYSC_IDLE_SMART>,
1658                                         <SYSC_IDLE_SMART_WKUP>;
1659                         ti,syss-mask = <1>;
1660                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1661                         clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1662                         clock-names = "fck";
1663                         #address-cells = <1>;
1664                         #size-cells = <1>;
1665                         ranges = <0x0 0x6e000 0x1000>;
1666
1667                         uart4: serial@0 {
1668                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1669                                 reg = <0x0 0x100>;
1670                                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1671                                 clock-frequency = <48000000>;
1672                                                 status = "disabled";
1673                                 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1674                                 dma-names = "tx", "rx";
1675                         };
1676                 };
1677
1678                 target-module@70000 {                   /* 0x48070000, ap 30 22.0 */
1679                         compatible = "ti,sysc-omap2", "ti,sysc";
1680                         reg = <0x70000 0x8>,
1681                               <0x70010 0x8>,
1682                               <0x70090 0x8>;
1683                         reg-names = "rev", "sysc", "syss";
1684                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1685                                          SYSC_OMAP2_ENAWAKEUP |
1686                                          SYSC_OMAP2_SOFTRESET |
1687                                          SYSC_OMAP2_AUTOIDLE)>;
1688                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1689                                         <SYSC_IDLE_NO>,
1690                                         <SYSC_IDLE_SMART>,
1691                                         <SYSC_IDLE_SMART_WKUP>;
1692                         ti,syss-mask = <1>;
1693                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1694                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1695                         clock-names = "fck";
1696                         #address-cells = <1>;
1697                         #size-cells = <1>;
1698                         ranges = <0x0 0x70000 0x1000>;
1699
1700                         i2c1: i2c@0 {
1701                                 compatible = "ti,omap4-i2c";
1702                                 reg = <0x0 0x100>;
1703                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1704                                 #address-cells = <1>;
1705                                 #size-cells = <0>;
1706                                 status = "disabled";
1707                         };
1708                 };
1709
1710                 target-module@72000 {                   /* 0x48072000, ap 32 2a.0 */
1711                         compatible = "ti,sysc-omap2", "ti,sysc";
1712                         reg = <0x72000 0x8>,
1713                               <0x72010 0x8>,
1714                               <0x72090 0x8>;
1715                         reg-names = "rev", "sysc", "syss";
1716                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1717                                          SYSC_OMAP2_ENAWAKEUP |
1718                                          SYSC_OMAP2_SOFTRESET |
1719                                          SYSC_OMAP2_AUTOIDLE)>;
1720                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1721                                         <SYSC_IDLE_NO>,
1722                                         <SYSC_IDLE_SMART>,
1723                                         <SYSC_IDLE_SMART_WKUP>;
1724                         ti,syss-mask = <1>;
1725                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1726                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1727                         clock-names = "fck";
1728                         #address-cells = <1>;
1729                         #size-cells = <1>;
1730                         ranges = <0x0 0x72000 0x1000>;
1731
1732                         i2c2: i2c@0 {
1733                                 compatible = "ti,omap4-i2c";
1734                                 reg = <0x0 0x100>;
1735                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1736                                 #address-cells = <1>;
1737                                 #size-cells = <0>;
1738                                 status = "disabled";
1739                         };
1740                 };
1741
1742                 target-module@78000 {                   /* 0x48078000, ap 39 0a.0 */
1743                         compatible = "ti,sysc-omap2", "ti,sysc";
1744                         reg = <0x78000 0x4>,
1745                               <0x78010 0x4>,
1746                               <0x78014 0x4>;
1747                         reg-names = "rev", "sysc", "syss";
1748                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1749                                          SYSC_OMAP2_SOFTRESET |
1750                                          SYSC_OMAP2_AUTOIDLE)>;
1751                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1752                                         <SYSC_IDLE_NO>,
1753                                         <SYSC_IDLE_SMART>,
1754                                         <SYSC_IDLE_SMART_WKUP>;
1755                         ti,syss-mask = <1>;
1756                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1757                         clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1758                         clock-names = "fck";
1759                         #address-cells = <1>;
1760                         #size-cells = <1>;
1761                         ranges = <0x0 0x78000 0x1000>;
1762
1763                         elm: elm@0 {
1764                                 compatible = "ti,am3352-elm";
1765                                 reg = <0x0 0xfc0>;      /* device IO registers */
1766                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1767                                 status = "disabled";
1768                         };
1769                 };
1770
1771                 target-module@7a000 {                   /* 0x4807a000, ap 81 3a.0 */
1772                         compatible = "ti,sysc-omap2", "ti,sysc";
1773                         reg = <0x7a000 0x8>,
1774                               <0x7a010 0x8>,
1775                               <0x7a090 0x8>;
1776                         reg-names = "rev", "sysc", "syss";
1777                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1778                                          SYSC_OMAP2_ENAWAKEUP |
1779                                          SYSC_OMAP2_SOFTRESET |
1780                                          SYSC_OMAP2_AUTOIDLE)>;
1781                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1782                                         <SYSC_IDLE_NO>,
1783                                         <SYSC_IDLE_SMART>,
1784                                         <SYSC_IDLE_SMART_WKUP>;
1785                         ti,syss-mask = <1>;
1786                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1787                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1788                         clock-names = "fck";
1789                         #address-cells = <1>;
1790                         #size-cells = <1>;
1791                         ranges = <0x0 0x7a000 0x1000>;
1792
1793                         i2c4: i2c@0 {
1794                                 compatible = "ti,omap4-i2c";
1795                                 reg = <0x0 0x100>;
1796                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1797                                 #address-cells = <1>;
1798                                 #size-cells = <0>;
1799                                 status = "disabled";
1800                         };
1801                 };
1802
1803                 target-module@7c000 {                   /* 0x4807c000, ap 83 4a.0 */
1804                         compatible = "ti,sysc-omap2", "ti,sysc";
1805                         reg = <0x7c000 0x8>,
1806                               <0x7c010 0x8>,
1807                               <0x7c090 0x8>;
1808                         reg-names = "rev", "sysc", "syss";
1809                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1810                                          SYSC_OMAP2_ENAWAKEUP |
1811                                          SYSC_OMAP2_SOFTRESET |
1812                                          SYSC_OMAP2_AUTOIDLE)>;
1813                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1814                                         <SYSC_IDLE_NO>,
1815                                         <SYSC_IDLE_SMART>,
1816                                         <SYSC_IDLE_SMART_WKUP>;
1817                         ti,syss-mask = <1>;
1818                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1819                         clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1820                         clock-names = "fck";
1821                         #address-cells = <1>;
1822                         #size-cells = <1>;
1823                         ranges = <0x0 0x7c000 0x1000>;
1824
1825                         i2c5: i2c@0 {
1826                                 compatible = "ti,omap4-i2c";
1827                                 reg = <0x0 0x100>;
1828                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1829                                 #address-cells = <1>;
1830                                 #size-cells = <0>;
1831                                 status = "disabled";
1832                         };
1833                 };
1834
1835                 target-module@86000 {                   /* 0x48086000, ap 41 5e.0 */
1836                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1837                         reg = <0x86000 0x4>,
1838                               <0x86010 0x4>;
1839                         reg-names = "rev", "sysc";
1840                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1841                                          SYSC_OMAP4_SOFTRESET)>;
1842                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1843                                         <SYSC_IDLE_NO>,
1844                                         <SYSC_IDLE_SMART>,
1845                                         <SYSC_IDLE_SMART_WKUP>;
1846                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1847                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1848                         clock-names = "fck";
1849                         #address-cells = <1>;
1850                         #size-cells = <1>;
1851                         ranges = <0x0 0x86000 0x1000>;
1852
1853                         timer10: timer@0 {
1854                                 compatible = "ti,omap5430-timer";
1855                                 reg = <0x0 0x80>;
1856                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
1857                                 clock-names = "fck";
1858                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1859                         };
1860                 };
1861
1862                 target-module@88000 {                   /* 0x48088000, ap 43 66.0 */
1863                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1864                         reg = <0x88000 0x4>,
1865                               <0x88010 0x4>;
1866                         reg-names = "rev", "sysc";
1867                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1868                                          SYSC_OMAP4_SOFTRESET)>;
1869                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1870                                         <SYSC_IDLE_NO>,
1871                                         <SYSC_IDLE_SMART>,
1872                                         <SYSC_IDLE_SMART_WKUP>;
1873                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1874                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1875                         clock-names = "fck";
1876                         #address-cells = <1>;
1877                         #size-cells = <1>;
1878                         ranges = <0x0 0x88000 0x1000>;
1879
1880                         timer11: timer@0 {
1881                                 compatible = "ti,omap5430-timer";
1882                                 reg = <0x0 0x80>;
1883                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
1884                                 clock-names = "fck";
1885                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1886                         };
1887                 };
1888
1889                 target-module@90000 {                   /* 0x48090000, ap 55 12.0 */
1890                         compatible = "ti,sysc-omap2", "ti,sysc";
1891                         reg = <0x91fe0 0x4>,
1892                               <0x91fe4 0x4>;
1893                         reg-names = "rev", "sysc";
1894                         ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1895                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1896                                         <SYSC_IDLE_NO>;
1897                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1898                         clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1899                         clock-names = "fck";
1900                         #address-cells = <1>;
1901                         #size-cells = <1>;
1902                         ranges = <0x0 0x90000 0x2000>;
1903
1904                         rng: rng@0 {
1905                                 compatible = "ti,omap4-rng";
1906                                 reg = <0x0 0x2000>;
1907                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1908                                 clocks = <&l3_iclk_div>;
1909                                 clock-names = "fck";
1910                         };
1911                 };
1912
1913                 target-module@98000 {                   /* 0x48098000, ap 47 08.0 */
1914                         compatible = "ti,sysc-omap4", "ti,sysc";
1915                         reg = <0x98000 0x4>,
1916                               <0x98010 0x4>;
1917                         reg-names = "rev", "sysc";
1918                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1919                                          SYSC_OMAP4_SOFTRESET)>;
1920                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1921                                         <SYSC_IDLE_NO>,
1922                                         <SYSC_IDLE_SMART>,
1923                                         <SYSC_IDLE_SMART_WKUP>;
1924                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1925                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1926                         clock-names = "fck";
1927                         #address-cells = <1>;
1928                         #size-cells = <1>;
1929                         ranges = <0x0 0x98000 0x1000>;
1930
1931                         mcspi1: spi@0 {
1932                                 compatible = "ti,omap4-mcspi";
1933                                 reg = <0x0 0x200>;
1934                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1935                                 #address-cells = <1>;
1936                                 #size-cells = <0>;
1937                                 ti,spi-num-cs = <4>;
1938                                 dmas = <&sdma_xbar 35>,
1939                                        <&sdma_xbar 36>,
1940                                        <&sdma_xbar 37>,
1941                                        <&sdma_xbar 38>,
1942                                        <&sdma_xbar 39>,
1943                                        <&sdma_xbar 40>,
1944                                        <&sdma_xbar 41>,
1945                                        <&sdma_xbar 42>;
1946                                 dma-names = "tx0", "rx0", "tx1", "rx1",
1947                                             "tx2", "rx2", "tx3", "rx3";
1948                                 status = "disabled";
1949                         };
1950                 };
1951
1952                 target-module@9a000 {                   /* 0x4809a000, ap 49 10.0 */
1953                         compatible = "ti,sysc-omap4", "ti,sysc";
1954                         reg = <0x9a000 0x4>,
1955                               <0x9a010 0x4>;
1956                         reg-names = "rev", "sysc";
1957                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1958                                          SYSC_OMAP4_SOFTRESET)>;
1959                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1960                                         <SYSC_IDLE_NO>,
1961                                         <SYSC_IDLE_SMART>,
1962                                         <SYSC_IDLE_SMART_WKUP>;
1963                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1964                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1965                         clock-names = "fck";
1966                         #address-cells = <1>;
1967                         #size-cells = <1>;
1968                         ranges = <0x0 0x9a000 0x1000>;
1969
1970                         mcspi2: spi@0 {
1971                                 compatible = "ti,omap4-mcspi";
1972                                 reg = <0x0 0x200>;
1973                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1974                                 #address-cells = <1>;
1975                                 #size-cells = <0>;
1976                                 ti,spi-num-cs = <2>;
1977                                 dmas = <&sdma_xbar 43>,
1978                                        <&sdma_xbar 44>,
1979                                        <&sdma_xbar 45>,
1980                                        <&sdma_xbar 46>;
1981                                 dma-names = "tx0", "rx0", "tx1", "rx1";
1982                                 status = "disabled";
1983                         };
1984                 };
1985
1986                 target-module@9c000 {                   /* 0x4809c000, ap 51 38.0 */
1987                         compatible = "ti,sysc-omap4", "ti,sysc";
1988                         reg = <0x9c000 0x4>,
1989                               <0x9c010 0x4>;
1990                         reg-names = "rev", "sysc";
1991                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1992                                          SYSC_OMAP4_SOFTRESET)>;
1993                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
1994                                         <SYSC_IDLE_NO>,
1995                                         <SYSC_IDLE_SMART>,
1996                                         <SYSC_IDLE_SMART_WKUP>;
1997                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1998                                         <SYSC_IDLE_NO>,
1999                                         <SYSC_IDLE_SMART>,
2000                                         <SYSC_IDLE_SMART_WKUP>;
2001                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2002                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2003                         clock-names = "fck";
2004                         #address-cells = <1>;
2005                         #size-cells = <1>;
2006                         ranges = <0x0 0x9c000 0x1000>;
2007
2008                         mmc1: mmc@0 {
2009                                 compatible = "ti,dra7-sdhci";
2010                                 reg = <0x0 0x400>;
2011                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2012                                 status = "disabled";
2013                                 pbias-supply = <&pbias_mmc_reg>;
2014                                 max-frequency = <192000000>;
2015                                 mmc-ddr-1_8v;
2016                                 mmc-ddr-3_3v;
2017                         };
2018                 };
2019
2020                 target-module@a2000 {                   /* 0x480a2000, ap 75 02.0 */
2021                         compatible = "ti,sysc";
2022                         status = "disabled";
2023                         #address-cells = <1>;
2024                         #size-cells = <1>;
2025                         ranges = <0x0 0xa2000 0x1000>;
2026                 };
2027
2028                 target-module@a4000 {                   /* 0x480a4000, ap 57 42.0 */
2029                         compatible = "ti,sysc";
2030                         status = "disabled";
2031                         #address-cells = <1>;
2032                         #size-cells = <1>;
2033                         ranges = <0x00000000 0x000a4000 0x00001000>,
2034                                  <0x00001000 0x000a5000 0x00001000>;
2035                 };
2036
2037                 des_target: target-module@a5000 {       /* 0x480a5000 */
2038                         compatible = "ti,sysc-omap2", "ti,sysc";
2039                         reg = <0xa5030 0x4>,
2040                               <0xa5034 0x4>,
2041                               <0xa5038 0x4>;
2042                         reg-names = "rev", "sysc", "syss";
2043                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2044                                          SYSC_OMAP2_AUTOIDLE)>;
2045                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2046                                         <SYSC_IDLE_NO>,
2047                                         <SYSC_IDLE_SMART>,
2048                                         <SYSC_IDLE_SMART_WKUP>;
2049                         ti,syss-mask = <1>;
2050                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
2051                         clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2052                         clock-names = "fck";
2053                         #address-cells = <1>;
2054                         #size-cells = <1>;
2055                         ranges = <0 0xa5000 0x00001000>;
2056
2057                         des: des@0 {
2058                                 compatible = "ti,omap4-des";
2059                                 reg = <0 0xa0>;
2060                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2061                                 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2062                                 dma-names = "tx", "rx";
2063                                 clocks = <&l3_iclk_div>;
2064                                 clock-names = "fck";
2065                         };
2066                 };
2067
2068                 target-module@a8000 {                   /* 0x480a8000, ap 59 1a.0 */
2069                         compatible = "ti,sysc";
2070                         status = "disabled";
2071                         #address-cells = <1>;
2072                         #size-cells = <1>;
2073                         ranges = <0x0 0xa8000 0x4000>;
2074                 };
2075
2076                 target-module@ad000 {                   /* 0x480ad000, ap 61 20.0 */
2077                         compatible = "ti,sysc-omap4", "ti,sysc";
2078                         reg = <0xad000 0x4>,
2079                               <0xad010 0x4>;
2080                         reg-names = "rev", "sysc";
2081                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2082                                          SYSC_OMAP4_SOFTRESET)>;
2083                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2084                                         <SYSC_IDLE_NO>,
2085                                         <SYSC_IDLE_SMART>,
2086                                         <SYSC_IDLE_SMART_WKUP>;
2087                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2088                                         <SYSC_IDLE_NO>,
2089                                         <SYSC_IDLE_SMART>,
2090                                         <SYSC_IDLE_SMART_WKUP>;
2091                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2092                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2093                         clock-names = "fck";
2094                         #address-cells = <1>;
2095                         #size-cells = <1>;
2096                         ranges = <0x0 0xad000 0x1000>;
2097
2098                         mmc3: mmc@0 {
2099                                 compatible = "ti,dra7-sdhci";
2100                                 reg = <0x0 0x400>;
2101                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2102                                 status = "disabled";
2103                                 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2104                                 max-frequency = <64000000>;
2105                                 /* SDMA is not supported */
2106                                 sdhci-caps-mask = <0x0 0x400000>;
2107                         };
2108                 };
2109
2110                 target-module@b2000 {                   /* 0x480b2000, ap 37 52.0 */
2111                         compatible = "ti,sysc-omap2", "ti,sysc";
2112                         reg = <0xb2000 0x4>,
2113                               <0xb2014 0x4>,
2114                               <0xb2018 0x4>;
2115                         reg-names = "rev", "sysc", "syss";
2116                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2117                                          SYSC_OMAP2_AUTOIDLE)>;
2118                         ti,syss-mask = <1>;
2119                         ti,no-reset-on-init;
2120                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2121                         clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2122                         clock-names = "fck";
2123                         #address-cells = <1>;
2124                         #size-cells = <1>;
2125                         ranges = <0x0 0xb2000 0x1000>;
2126
2127                         hdqw1w: 1w@0 {
2128                                 compatible = "ti,omap3-1w";
2129                                 reg = <0x0 0x1000>;
2130                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2131                         };
2132                 };
2133
2134                 target-module@b4000 {                   /* 0x480b4000, ap 65 40.0 */
2135                         compatible = "ti,sysc-omap4", "ti,sysc";
2136                         reg = <0xb4000 0x4>,
2137                               <0xb4010 0x4>;
2138                         reg-names = "rev", "sysc";
2139                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2140                                          SYSC_OMAP4_SOFTRESET)>;
2141                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2142                                         <SYSC_IDLE_NO>,
2143                                         <SYSC_IDLE_SMART>,
2144                                         <SYSC_IDLE_SMART_WKUP>;
2145                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2146                                         <SYSC_IDLE_NO>,
2147                                         <SYSC_IDLE_SMART>,
2148                                         <SYSC_IDLE_SMART_WKUP>;
2149                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2150                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2151                         clock-names = "fck";
2152                         #address-cells = <1>;
2153                         #size-cells = <1>;
2154                         ranges = <0x0 0xb4000 0x1000>;
2155
2156                         mmc2: mmc@0 {
2157                                 compatible = "ti,dra7-sdhci";
2158                                 reg = <0x0 0x400>;
2159                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2160                                 status = "disabled";
2161                                 max-frequency = <192000000>;
2162                                 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2163                                 sdhci-caps-mask = <0x7 0x0>;
2164                                 mmc-hs200-1_8v;
2165                                 mmc-ddr-1_8v;
2166                                 mmc-ddr-3_3v;
2167                         };
2168                 };
2169
2170                 target-module@b8000 {                   /* 0x480b8000, ap 67 48.0 */
2171                         compatible = "ti,sysc-omap4", "ti,sysc";
2172                         reg = <0xb8000 0x4>,
2173                               <0xb8010 0x4>;
2174                         reg-names = "rev", "sysc";
2175                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2176                                          SYSC_OMAP4_SOFTRESET)>;
2177                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2178                                         <SYSC_IDLE_NO>,
2179                                         <SYSC_IDLE_SMART>,
2180                                         <SYSC_IDLE_SMART_WKUP>;
2181                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2182                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2183                         clock-names = "fck";
2184                         #address-cells = <1>;
2185                         #size-cells = <1>;
2186                         ranges = <0x0 0xb8000 0x1000>;
2187
2188                         mcspi3: spi@0 {
2189                                 compatible = "ti,omap4-mcspi";
2190                                 reg = <0x0 0x200>;
2191                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2192                                 #address-cells = <1>;
2193                                 #size-cells = <0>;
2194                                 ti,spi-num-cs = <2>;
2195                                 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2196                                 dma-names = "tx0", "rx0";
2197                                 status = "disabled";
2198                         };
2199                 };
2200
2201                 target-module@ba000 {                   /* 0x480ba000, ap 69 18.0 */
2202                         compatible = "ti,sysc-omap4", "ti,sysc";
2203                         reg = <0xba000 0x4>,
2204                               <0xba010 0x4>;
2205                         reg-names = "rev", "sysc";
2206                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2207                                          SYSC_OMAP4_SOFTRESET)>;
2208                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2209                                         <SYSC_IDLE_NO>,
2210                                         <SYSC_IDLE_SMART>,
2211                                         <SYSC_IDLE_SMART_WKUP>;
2212                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2213                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2214                         clock-names = "fck";
2215                         #address-cells = <1>;
2216                         #size-cells = <1>;
2217                         ranges = <0x0 0xba000 0x1000>;
2218
2219                         mcspi4: spi@0 {
2220                                 compatible = "ti,omap4-mcspi";
2221                                 reg = <0x0 0x200>;
2222                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2223                                 #address-cells = <1>;
2224                                 #size-cells = <0>;
2225                                 ti,spi-num-cs = <1>;
2226                                 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2227                                 dma-names = "tx0", "rx0";
2228                                 status = "disabled";
2229                         };
2230                 };
2231
2232                 target-module@d1000 {                   /* 0x480d1000, ap 71 28.0 */
2233                         compatible = "ti,sysc-omap4", "ti,sysc";
2234                         reg = <0xd1000 0x4>,
2235                               <0xd1010 0x4>;
2236                         reg-names = "rev", "sysc";
2237                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2238                                          SYSC_OMAP4_SOFTRESET)>;
2239                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2240                                         <SYSC_IDLE_NO>,
2241                                         <SYSC_IDLE_SMART>,
2242                                         <SYSC_IDLE_SMART_WKUP>;
2243                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2244                                         <SYSC_IDLE_NO>,
2245                                         <SYSC_IDLE_SMART>,
2246                                         <SYSC_IDLE_SMART_WKUP>;
2247                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2248                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2249                         clock-names = "fck";
2250                         #address-cells = <1>;
2251                         #size-cells = <1>;
2252                         ranges = <0x0 0xd1000 0x1000>;
2253
2254                         mmc4: mmc@0 {
2255                                 compatible = "ti,dra7-sdhci";
2256                                 reg = <0x0 0x400>;
2257                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2258                                 status = "disabled";
2259                                 max-frequency = <192000000>;
2260                                 /* SDMA is not supported */
2261                                 sdhci-caps-mask = <0x0 0x400000>;
2262                         };
2263                 };
2264
2265                 target-module@d5000 {                   /* 0x480d5000, ap 73 30.0 */
2266                         compatible = "ti,sysc";
2267                         status = "disabled";
2268                         #address-cells = <1>;
2269                         #size-cells = <1>;
2270                         ranges = <0x0 0xd5000 0x1000>;
2271                 };
2272         };
2273
2274         segment@200000 {                                        /* 0x48200000 */
2275                 compatible = "simple-bus";
2276                 #address-cells = <1>;
2277                 #size-cells = <1>;
2278         };
2279 };
2280
2281 &l4_per2 {                                              /* 0x48400000 */
2282         compatible = "ti,dra7-l4-per2", "simple-bus";
2283         reg = <0x48400000 0x800>,
2284               <0x48400800 0x800>,
2285               <0x48401000 0x400>,
2286               <0x48401400 0x400>,
2287               <0x48401800 0x400>;
2288         reg-names = "ap", "la", "ia0", "ia1", "ia2";
2289         #address-cells = <1>;
2290         #size-cells = <1>;
2291         ranges = <0x00000000 0x48400000 0x400000>,      /* segment 0 */
2292                  <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2293                  <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2294                  <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2295                  <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2296                  <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2297                  <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2298                  <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2299                  <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2300
2301         segment@0 {                                     /* 0x48400000 */
2302                 compatible = "simple-bus";
2303                 #address-cells = <1>;
2304                 #size-cells = <1>;
2305                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
2306                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
2307                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
2308                          <0x00084000 0x00084000 0x004000>,      /* ap 3 */
2309                          <0x00001400 0x00001400 0x000400>,      /* ap 4 */
2310                          <0x00001800 0x00001800 0x000400>,      /* ap 5 */
2311                          <0x00088000 0x00088000 0x001000>,      /* ap 6 */
2312                          <0x0002c000 0x0002c000 0x001000>,      /* ap 7 */
2313                          <0x0002d000 0x0002d000 0x001000>,      /* ap 8 */
2314                          <0x00060000 0x00060000 0x002000>,      /* ap 9 */
2315                          <0x00062000 0x00062000 0x001000>,      /* ap 10 */
2316                          <0x00064000 0x00064000 0x002000>,      /* ap 11 */
2317                          <0x00066000 0x00066000 0x001000>,      /* ap 12 */
2318                          <0x00068000 0x00068000 0x002000>,      /* ap 13 */
2319                          <0x0006a000 0x0006a000 0x001000>,      /* ap 14 */
2320                          <0x0006c000 0x0006c000 0x002000>,      /* ap 15 */
2321                          <0x0006e000 0x0006e000 0x001000>,      /* ap 16 */
2322                          <0x00036000 0x00036000 0x001000>,      /* ap 17 */
2323                          <0x00037000 0x00037000 0x001000>,      /* ap 18 */
2324                          <0x00070000 0x00070000 0x002000>,      /* ap 19 */
2325                          <0x00072000 0x00072000 0x001000>,      /* ap 20 */
2326                          <0x0003a000 0x0003a000 0x001000>,      /* ap 21 */
2327                          <0x0003b000 0x0003b000 0x001000>,      /* ap 22 */
2328                          <0x0003c000 0x0003c000 0x001000>,      /* ap 23 */
2329                          <0x0003d000 0x0003d000 0x001000>,      /* ap 24 */
2330                          <0x0003e000 0x0003e000 0x001000>,      /* ap 25 */
2331                          <0x0003f000 0x0003f000 0x001000>,      /* ap 26 */
2332                          <0x00040000 0x00040000 0x001000>,      /* ap 27 */
2333                          <0x00041000 0x00041000 0x001000>,      /* ap 28 */
2334                          <0x00042000 0x00042000 0x001000>,      /* ap 29 */
2335                          <0x00043000 0x00043000 0x001000>,      /* ap 30 */
2336                          <0x00080000 0x00080000 0x002000>,      /* ap 31 */
2337                          <0x00082000 0x00082000 0x001000>,      /* ap 32 */
2338                          <0x0004a000 0x0004a000 0x001000>,      /* ap 33 */
2339                          <0x0004b000 0x0004b000 0x001000>,      /* ap 34 */
2340                          <0x00074000 0x00074000 0x002000>,      /* ap 35 */
2341                          <0x00076000 0x00076000 0x001000>,      /* ap 36 */
2342                          <0x00050000 0x00050000 0x001000>,      /* ap 37 */
2343                          <0x00051000 0x00051000 0x001000>,      /* ap 38 */
2344                          <0x00078000 0x00078000 0x002000>,      /* ap 39 */
2345                          <0x0007a000 0x0007a000 0x001000>,      /* ap 40 */
2346                          <0x00054000 0x00054000 0x001000>,      /* ap 41 */
2347                          <0x00055000 0x00055000 0x001000>,      /* ap 42 */
2348                          <0x0007c000 0x0007c000 0x002000>,      /* ap 43 */
2349                          <0x0007e000 0x0007e000 0x001000>,      /* ap 44 */
2350                          <0x0004c000 0x0004c000 0x001000>,      /* ap 45 */
2351                          <0x0004d000 0x0004d000 0x001000>,      /* ap 46 */
2352                          <0x00020000 0x00020000 0x001000>,      /* ap 47 */
2353                          <0x00021000 0x00021000 0x001000>,      /* ap 48 */
2354                          <0x00022000 0x00022000 0x001000>,      /* ap 49 */
2355                          <0x00023000 0x00023000 0x001000>,      /* ap 50 */
2356                          <0x00024000 0x00024000 0x001000>,      /* ap 51 */
2357                          <0x00025000 0x00025000 0x001000>,      /* ap 52 */
2358                          <0x00046000 0x00046000 0x001000>,      /* ap 53 */
2359                          <0x00047000 0x00047000 0x001000>,      /* ap 54 */
2360                          <0x00048000 0x00048000 0x001000>,      /* ap 55 */
2361                          <0x00049000 0x00049000 0x001000>,      /* ap 56 */
2362                          <0x00058000 0x00058000 0x002000>,      /* ap 57 */
2363                          <0x0005a000 0x0005a000 0x001000>,      /* ap 58 */
2364                          <0x0005b000 0x0005b000 0x001000>,      /* ap 59 */
2365                          <0x0005c000 0x0005c000 0x001000>,      /* ap 60 */
2366                          <0x0005d000 0x0005d000 0x001000>,      /* ap 61 */
2367                          <0x0005e000 0x0005e000 0x001000>,      /* ap 62 */
2368                          <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2369                          <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2370                          <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2371                          <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2372                          <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2373                          <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2374                          <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2375                          <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2376
2377                 target-module@20000 {                   /* 0x48420000, ap 47 02.0 */
2378                         compatible = "ti,sysc-omap2", "ti,sysc";
2379                         reg = <0x20050 0x4>,
2380                               <0x20054 0x4>,
2381                               <0x20058 0x4>;
2382                         reg-names = "rev", "sysc", "syss";
2383                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2384                                          SYSC_OMAP2_SOFTRESET |
2385                                          SYSC_OMAP2_AUTOIDLE)>;
2386                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2387                                         <SYSC_IDLE_NO>,
2388                                         <SYSC_IDLE_SMART>,
2389                                         <SYSC_IDLE_SMART_WKUP>;
2390                         ti,syss-mask = <1>;
2391                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2392                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2393                         clock-names = "fck";
2394                         #address-cells = <1>;
2395                         #size-cells = <1>;
2396                         ranges = <0x0 0x20000 0x1000>;
2397
2398                         uart7: serial@0 {
2399                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2400                                 reg = <0x0 0x100>;
2401                                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2402                                 clock-frequency = <48000000>;
2403                                 status = "disabled";
2404                         };
2405                 };
2406
2407                 target-module@22000 {                   /* 0x48422000, ap 49 0a.0 */
2408                         compatible = "ti,sysc-omap2", "ti,sysc";
2409                         reg = <0x22050 0x4>,
2410                               <0x22054 0x4>,
2411                               <0x22058 0x4>;
2412                         reg-names = "rev", "sysc", "syss";
2413                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2414                                          SYSC_OMAP2_SOFTRESET |
2415                                          SYSC_OMAP2_AUTOIDLE)>;
2416                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2417                                         <SYSC_IDLE_NO>,
2418                                         <SYSC_IDLE_SMART>,
2419                                         <SYSC_IDLE_SMART_WKUP>;
2420                         ti,syss-mask = <1>;
2421                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2422                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2423                         clock-names = "fck";
2424                         #address-cells = <1>;
2425                         #size-cells = <1>;
2426                         ranges = <0x0 0x22000 0x1000>;
2427
2428                         uart8: serial@0 {
2429                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2430                                 reg = <0x0 0x100>;
2431                                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2432                                 clock-frequency = <48000000>;
2433                                 status = "disabled";
2434                         };
2435                 };
2436
2437                 target-module@24000 {                   /* 0x48424000, ap 51 12.0 */
2438                         compatible = "ti,sysc-omap2", "ti,sysc";
2439                         reg = <0x24050 0x4>,
2440                               <0x24054 0x4>,
2441                               <0x24058 0x4>;
2442                         reg-names = "rev", "sysc", "syss";
2443                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2444                                          SYSC_OMAP2_SOFTRESET |
2445                                          SYSC_OMAP2_AUTOIDLE)>;
2446                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2447                                         <SYSC_IDLE_NO>,
2448                                         <SYSC_IDLE_SMART>,
2449                                         <SYSC_IDLE_SMART_WKUP>;
2450                         ti,syss-mask = <1>;
2451                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2452                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2453                         clock-names = "fck";
2454                         #address-cells = <1>;
2455                         #size-cells = <1>;
2456                         ranges = <0x0 0x24000 0x1000>;
2457
2458                         uart9: serial@0 {
2459                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2460                                 reg = <0x0 0x100>;
2461                                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2462                                 clock-frequency = <48000000>;
2463                                 status = "disabled";
2464                         };
2465                 };
2466
2467                 target-module@2c000 {                   /* 0x4842c000, ap 7 18.0 */
2468                         compatible = "ti,sysc";
2469                         status = "disabled";
2470                         #address-cells = <1>;
2471                         #size-cells = <1>;
2472                         ranges = <0x0 0x2c000 0x1000>;
2473                 };
2474
2475                 target-module@36000 {                   /* 0x48436000, ap 17 06.0 */
2476                         compatible = "ti,sysc";
2477                         status = "disabled";
2478                         #address-cells = <1>;
2479                         #size-cells = <1>;
2480                         ranges = <0x0 0x36000 0x1000>;
2481                 };
2482
2483                 target-module@3a000 {                   /* 0x4843a000, ap 21 3e.0 */
2484                         compatible = "ti,sysc";
2485                         status = "disabled";
2486                         #address-cells = <1>;
2487                         #size-cells = <1>;
2488                         ranges = <0x0 0x3a000 0x1000>;
2489                 };
2490
2491                 atl_tm: target-module@3c000 {           /* 0x4843c000, ap 23 08.0 */
2492                         compatible = "ti,sysc-omap4", "ti,sysc";
2493                         reg = <0x3c000 0x4>;
2494                         reg-names = "rev";
2495                         clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2496                         clock-names = "fck";
2497                         #address-cells = <1>;
2498                         #size-cells = <1>;
2499                         ranges = <0x0 0x3c000 0x1000>;
2500
2501                         atl: atl@0 {
2502                                 compatible = "ti,dra7-atl";
2503                                 reg = <0x0 0x3ff>;
2504                                 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2505                                                      <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2506                                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2507                                 clock-names = "fck";
2508                                 status = "disabled";
2509                         };
2510                 };
2511
2512                 target-module@3e000 {                   /* 0x4843e000, ap 25 30.0 */
2513                         compatible = "ti,sysc-omap4", "ti,sysc";
2514                         reg = <0x3e000 0x4>,
2515                               <0x3e004 0x4>;
2516                         reg-names = "rev", "sysc";
2517                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2518                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2519                                         <SYSC_IDLE_NO>,
2520                                         <SYSC_IDLE_SMART>;
2521                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2522                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2523                         clock-names = "fck";
2524                         #address-cells = <1>;
2525                         #size-cells = <1>;
2526                         ranges = <0x0 0x3e000 0x1000>;
2527
2528                         epwmss0: epwmss@0 {
2529                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2530                                 reg = <0x0 0x30>;
2531                                 #address-cells = <1>;
2532                                 #size-cells = <1>;
2533                                 status = "disabled";
2534                                 ranges = <0 0 0x1000>;
2535
2536                                 ecap0: ecap@100 {
2537                                         compatible = "ti,dra746-ecap",
2538                                                      "ti,am3352-ecap";
2539                                         #pwm-cells = <3>;
2540                                         reg = <0x100 0x80>;
2541                                         clocks = <&l4_root_clk_div>;
2542                                         clock-names = "fck";
2543                                         status = "disabled";
2544                                 };
2545
2546                                 ehrpwm0: pwm@200 {
2547                                         compatible = "ti,dra746-ehrpwm",
2548                                                      "ti,am3352-ehrpwm";
2549                                         #pwm-cells = <3>;
2550                                         reg = <0x200 0x80>;
2551                                         clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2552                                         clock-names = "tbclk", "fck";
2553                                         status = "disabled";
2554                                 };
2555                         };
2556                 };
2557
2558                 target-module@40000 {                   /* 0x48440000, ap 27 38.0 */
2559                         compatible = "ti,sysc-omap4", "ti,sysc";
2560                         reg = <0x40000 0x4>,
2561                               <0x40004 0x4>;
2562                         reg-names = "rev", "sysc";
2563                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2564                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2565                                         <SYSC_IDLE_NO>,
2566                                         <SYSC_IDLE_SMART>;
2567                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2568                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2569                         clock-names = "fck";
2570                         #address-cells = <1>;
2571                         #size-cells = <1>;
2572                         ranges = <0x0 0x40000 0x1000>;
2573
2574                         epwmss1: epwmss@0 {
2575                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2576                                 reg = <0x0 0x30>;
2577                                 #address-cells = <1>;
2578                                 #size-cells = <1>;
2579                                 status = "disabled";
2580                                 ranges = <0 0 0x1000>;
2581
2582                                 ecap1: ecap@100 {
2583                                         compatible = "ti,dra746-ecap",
2584                                                      "ti,am3352-ecap";
2585                                         #pwm-cells = <3>;
2586                                         reg = <0x100 0x80>;
2587                                         clocks = <&l4_root_clk_div>;
2588                                         clock-names = "fck";
2589                                         status = "disabled";
2590                                 };
2591
2592                                 ehrpwm1: pwm@200 {
2593                                         compatible = "ti,dra746-ehrpwm",
2594                                                      "ti,am3352-ehrpwm";
2595                                         #pwm-cells = <3>;
2596                                         reg = <0x200 0x80>;
2597                                         clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2598                                         clock-names = "tbclk", "fck";
2599                                         status = "disabled";
2600                                 };
2601                         };
2602                 };
2603
2604                 target-module@42000 {                   /* 0x48442000, ap 29 20.0 */
2605                         compatible = "ti,sysc-omap4", "ti,sysc";
2606                         reg = <0x42000 0x4>,
2607                               <0x42004 0x4>;
2608                         reg-names = "rev", "sysc";
2609                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2610                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2611                                         <SYSC_IDLE_NO>,
2612                                         <SYSC_IDLE_SMART>;
2613                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2614                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2615                         clock-names = "fck";
2616                         #address-cells = <1>;
2617                         #size-cells = <1>;
2618                         ranges = <0x0 0x42000 0x1000>;
2619
2620                         epwmss2: epwmss@0 {
2621                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2622                                 reg = <0x0 0x30>;
2623                                 #address-cells = <1>;
2624                                 #size-cells = <1>;
2625                                 status = "disabled";
2626                                 ranges = <0 0 0x1000>;
2627
2628                                 ecap2: ecap@100 {
2629                                         compatible = "ti,dra746-ecap",
2630                                                      "ti,am3352-ecap";
2631                                         #pwm-cells = <3>;
2632                                         reg = <0x100 0x80>;
2633                                         clocks = <&l4_root_clk_div>;
2634                                         clock-names = "fck";
2635                                         status = "disabled";
2636                                 };
2637
2638                                 ehrpwm2: pwm@200 {
2639                                         compatible = "ti,dra746-ehrpwm",
2640                                                      "ti,am3352-ehrpwm";
2641                                         #pwm-cells = <3>;
2642                                         reg = <0x200 0x80>;
2643                                         clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2644                                         clock-names = "tbclk", "fck";
2645                                         status = "disabled";
2646                                 };
2647                         };
2648                 };
2649
2650                 target-module@46000 {                   /* 0x48446000, ap 53 40.0 */
2651                         compatible = "ti,sysc";
2652                         status = "disabled";
2653                         #address-cells = <1>;
2654                         #size-cells = <1>;
2655                         ranges = <0x0 0x46000 0x1000>;
2656                 };
2657
2658                 target-module@48000 {                   /* 0x48448000, ap 55 48.0 */
2659                         compatible = "ti,sysc";
2660                         status = "disabled";
2661                         #address-cells = <1>;
2662                         #size-cells = <1>;
2663                         ranges = <0x0 0x48000 0x1000>;
2664                 };
2665
2666                 target-module@4a000 {                   /* 0x4844a000, ap 33 1a.0 */
2667                         compatible = "ti,sysc";
2668                         status = "disabled";
2669                         #address-cells = <1>;
2670                         #size-cells = <1>;
2671                         ranges = <0x0 0x4a000 0x1000>;
2672                 };
2673
2674                 target-module@4c000 {                   /* 0x4844c000, ap 45 1c.0 */
2675                         compatible = "ti,sysc";
2676                         status = "disabled";
2677                         #address-cells = <1>;
2678                         #size-cells = <1>;
2679                         ranges = <0x0 0x4c000 0x1000>;
2680                 };
2681
2682                 target-module@50000 {                   /* 0x48450000, ap 37 24.0 */
2683                         compatible = "ti,sysc";
2684                         status = "disabled";
2685                         #address-cells = <1>;
2686                         #size-cells = <1>;
2687                         ranges = <0x0 0x50000 0x1000>;
2688                 };
2689
2690                 target-module@54000 {                   /* 0x48454000, ap 41 2c.0 */
2691                         compatible = "ti,sysc";
2692                         status = "disabled";
2693                         #address-cells = <1>;
2694                         #size-cells = <1>;
2695                         ranges = <0x0 0x54000 0x1000>;
2696                 };
2697
2698                 target-module@58000 {                   /* 0x48458000, ap 57 28.0 */
2699                         compatible = "ti,sysc";
2700                         status = "disabled";
2701                         #address-cells = <1>;
2702                         #size-cells = <1>;
2703                         ranges = <0x0 0x58000 0x2000>;
2704                 };
2705
2706                 target-module@5b000 {                   /* 0x4845b000, ap 59 46.0 */
2707                         compatible = "ti,sysc";
2708                         status = "disabled";
2709                         #address-cells = <1>;
2710                         #size-cells = <1>;
2711                         ranges = <0x0 0x5b000 0x1000>;
2712                 };
2713
2714                 target-module@5d000 {                   /* 0x4845d000, ap 61 22.0 */
2715                         compatible = "ti,sysc";
2716                         status = "disabled";
2717                         #address-cells = <1>;
2718                         #size-cells = <1>;
2719                         ranges = <0x0 0x5d000 0x1000>;
2720                 };
2721
2722                 target-module@60000 {                   /* 0x48460000, ap 9 0e.0 */
2723                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2724                         reg = <0x60000 0x4>,
2725                               <0x60004 0x4>;
2726                         reg-names = "rev", "sysc";
2727                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2728                                         <SYSC_IDLE_NO>,
2729                                         <SYSC_IDLE_SMART>;
2730                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2731                         clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2732                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2733                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2734                         clock-names = "fck", "ahclkx", "ahclkr";
2735                         #address-cells = <1>;
2736                         #size-cells = <1>;
2737                         ranges = <0x0 0x60000 0x2000>,
2738                                  <0x45800000 0x45800000 0x400000>;
2739
2740                         mcasp1: mcasp@0 {
2741                                 compatible = "ti,dra7-mcasp-audio";
2742                                 reg = <0x0 0x2000>,
2743                                       <0x45800000 0x1000>;      /* L3 data port */
2744                                 reg-names = "mpu","dat";
2745                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2746                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2747                                 interrupt-names = "tx", "rx";
2748                                 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2749                                 dma-names = "tx", "rx";
2750                                 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2751                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2752                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2753                                 clock-names = "fck", "ahclkx", "ahclkr";
2754                                 status = "disabled";
2755                         };
2756                 };
2757
2758                 target-module@64000 {                   /* 0x48464000, ap 11 1e.0 */
2759                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2760                         reg = <0x64000 0x4>,
2761                               <0x64004 0x4>;
2762                         reg-names = "rev", "sysc";
2763                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2764                                         <SYSC_IDLE_NO>,
2765                                         <SYSC_IDLE_SMART>;
2766                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2767                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2768                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2769                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2770                         clock-names = "fck", "ahclkx", "ahclkr";
2771                         #address-cells = <1>;
2772                         #size-cells = <1>;
2773                         ranges = <0x0 0x64000 0x2000>,
2774                                  <0x45c00000 0x45c00000 0x400000>;
2775
2776                         mcasp2: mcasp@0 {
2777                                 compatible = "ti,dra7-mcasp-audio";
2778                                 reg = <0x0 0x2000>,
2779                                       <0x45c00000 0x1000>;      /* L3 data port */
2780                                 reg-names = "mpu","dat";
2781                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2782                                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2783                                 interrupt-names = "tx", "rx";
2784                                 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2785                                 dma-names = "tx", "rx";
2786                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2787                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2788                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2789                                 clock-names = "fck", "ahclkx", "ahclkr";
2790                                 status = "disabled";
2791                         };
2792                 };
2793
2794                 target-module@68000 {                   /* 0x48468000, ap 13 26.0 */
2795                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2796                         reg = <0x68000 0x4>,
2797                               <0x68004 0x4>;
2798                         reg-names = "rev", "sysc";
2799                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2800                                         <SYSC_IDLE_NO>,
2801                                         <SYSC_IDLE_SMART>;
2802                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2803                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2804                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2805                         clock-names = "fck", "ahclkx";
2806                         #address-cells = <1>;
2807                         #size-cells = <1>;
2808                         ranges = <0x0 0x68000 0x2000>,
2809                                  <0x46000000 0x46000000 0x400000>;
2810
2811                         mcasp3: mcasp@0 {
2812                                 compatible = "ti,dra7-mcasp-audio";
2813                                 reg = <0x0 0x2000>,
2814                                       <0x46000000 0x1000>;      /* L3 data port */
2815                                 reg-names = "mpu","dat";
2816                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2817                                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2818                                 interrupt-names = "tx", "rx";
2819                                 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2820                                 dma-names = "tx", "rx";
2821                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2822                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2823                                 clock-names = "fck", "ahclkx";
2824                                 status = "disabled";
2825                         };
2826                 };
2827
2828                 target-module@6c000 {                   /* 0x4846c000, ap 15 2e.0 */
2829                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2830                         reg = <0x6c000 0x4>,
2831                               <0x6c004 0x4>;
2832                         reg-names = "rev", "sysc";
2833                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2834                                         <SYSC_IDLE_NO>,
2835                                         <SYSC_IDLE_SMART>;
2836                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2837                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2838                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2839                         clock-names = "fck", "ahclkx";
2840                         #address-cells = <1>;
2841                         #size-cells = <1>;
2842                         ranges = <0x0 0x6c000 0x2000>,
2843                                  <0x48436000 0x48436000 0x400000>;
2844
2845                         mcasp4: mcasp@0 {
2846                                 compatible = "ti,dra7-mcasp-audio";
2847                                 reg = <0x0 0x2000>,
2848                                       <0x48436000 0x1000>;      /* L3 data port */
2849                                 reg-names = "mpu","dat";
2850                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2851                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2852                                 interrupt-names = "tx", "rx";
2853                                 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2854                                 dma-names = "tx", "rx";
2855                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2856                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2857                                 clock-names = "fck", "ahclkx";
2858                                 status = "disabled";
2859                         };
2860                 };
2861
2862                 target-module@70000 {                   /* 0x48470000, ap 19 36.0 */
2863                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2864                         reg = <0x70000 0x4>,
2865                               <0x70004 0x4>;
2866                         reg-names = "rev", "sysc";
2867                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2868                                         <SYSC_IDLE_NO>,
2869                                         <SYSC_IDLE_SMART>;
2870                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2871                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2872                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2873                         clock-names = "fck", "ahclkx";
2874                         #address-cells = <1>;
2875                         #size-cells = <1>;
2876                         ranges = <0x0 0x70000 0x2000>,
2877                                  <0x4843a000 0x4843a000 0x400000>;
2878
2879                         mcasp5: mcasp@0 {
2880                                 compatible = "ti,dra7-mcasp-audio";
2881                                 reg = <0x0 0x2000>,
2882                                       <0x4843a000 0x1000>;      /* L3 data port */
2883                                 reg-names = "mpu","dat";
2884                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2885                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2886                                 interrupt-names = "tx", "rx";
2887                                 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2888                                 dma-names = "tx", "rx";
2889                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2890                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2891                                 clock-names = "fck", "ahclkx";
2892                                 status = "disabled";
2893                         };
2894                 };
2895
2896                 target-module@74000 {                   /* 0x48474000, ap 35 14.0 */
2897                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2898                         reg = <0x74000 0x4>,
2899                               <0x74004 0x4>;
2900                         reg-names = "rev", "sysc";
2901                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2902                                         <SYSC_IDLE_NO>,
2903                                         <SYSC_IDLE_SMART>;
2904                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2905                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2906                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2907                         clock-names = "fck", "ahclkx";
2908                         #address-cells = <1>;
2909                         #size-cells = <1>;
2910                         ranges = <0x0 0x74000 0x2000>,
2911                                  <0x4844c000 0x4844c000 0x400000>;
2912
2913                         mcasp6: mcasp@0 {
2914                                 compatible = "ti,dra7-mcasp-audio";
2915                                 reg = <0x0 0x2000>,
2916                                       <0x4844c000 0x1000>;      /* L3 data port */
2917                                 reg-names = "mpu","dat";
2918                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2919                                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2920                                 interrupt-names = "tx", "rx";
2921                                 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2922                                 dma-names = "tx", "rx";
2923                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2924                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2925                                 clock-names = "fck", "ahclkx";
2926                                 status = "disabled";
2927                         };
2928                 };
2929
2930                 target-module@78000 {                   /* 0x48478000, ap 39 0c.0 */
2931                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2932                         reg = <0x78000 0x4>,
2933                               <0x78004 0x4>;
2934                         reg-names = "rev", "sysc";
2935                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2936                                         <SYSC_IDLE_NO>,
2937                                         <SYSC_IDLE_SMART>;
2938                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2939                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2940                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2941                         clock-names = "fck", "ahclkx";
2942                         #address-cells = <1>;
2943                         #size-cells = <1>;
2944                         ranges = <0x0 0x78000 0x2000>,
2945                                  <0x48450000 0x48450000 0x400000>;
2946
2947                         mcasp7: mcasp@0 {
2948                                 compatible = "ti,dra7-mcasp-audio";
2949                                 reg = <0x0 0x2000>,
2950                                       <0x48450000 0x1000>;      /* L3 data port */
2951                                 reg-names = "mpu","dat";
2952                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2953                                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2954                                 interrupt-names = "tx", "rx";
2955                                 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2956                                 dma-names = "tx", "rx";
2957                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2958                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2959                                 clock-names = "fck", "ahclkx";
2960                                 status = "disabled";
2961                         };
2962                 };
2963
2964                 target-module@7c000 {                   /* 0x4847c000, ap 43 04.0 */
2965                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2966                         reg = <0x7c000 0x4>,
2967                               <0x7c004 0x4>;
2968                         reg-names = "rev", "sysc";
2969                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2970                                         <SYSC_IDLE_NO>,
2971                                         <SYSC_IDLE_SMART>;
2972                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2973                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2974                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2975                         clock-names = "fck", "ahclkx";
2976                         #address-cells = <1>;
2977                         #size-cells = <1>;
2978                         ranges = <0x0 0x7c000 0x2000>,
2979                                  <0x48454000 0x48454000 0x400000>;
2980
2981                         mcasp8: mcasp@0 {
2982                                 compatible = "ti,dra7-mcasp-audio";
2983                                 reg = <0x0 0x2000>,
2984                                       <0x48454000 0x1000>;      /* L3 data port */
2985                                 reg-names = "mpu","dat";
2986                                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2987                                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2988                                 interrupt-names = "tx", "rx";
2989                                 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2990                                 dma-names = "tx", "rx";
2991                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2992                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2993                                 clock-names = "fck", "ahclkx";
2994                                 status = "disabled";
2995                         };
2996                 };
2997
2998                 target-module@80000 {                   /* 0x48480000, ap 31 16.0 */
2999                         compatible = "ti,sysc-omap4", "ti,sysc";
3000                         reg = <0x80020 0x4>;
3001                         reg-names = "rev";
3002                         clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3003                         clock-names = "fck";
3004                         #address-cells = <1>;
3005                         #size-cells = <1>;
3006                         ranges = <0x0 0x80000 0x2000>;
3007
3008                         dcan2: can@0 {
3009                                 compatible = "ti,dra7-d_can";
3010                                 reg = <0x0 0x2000>;
3011                                 syscon-raminit = <&scm_conf 0x558 1>;
3012                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
3013                                 clocks = <&sys_clkin1>;
3014                                 status = "disabled";
3015                         };
3016                 };
3017
3018                 target-module@84000 {                   /* 0x48484000, ap 3 10.0 */
3019                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3020                         reg = <0x85200 0x4>,
3021                               <0x85208 0x4>,
3022                               <0x85204 0x4>;
3023                         reg-names = "rev", "sysc", "syss";
3024                         ti,sysc-mask = <0>;
3025                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
3026                                         <SYSC_IDLE_NO>;
3027                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3028                                         <SYSC_IDLE_NO>;
3029                         ti,syss-mask = <1>;
3030                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3031                         clock-names = "fck";
3032                         #address-cells = <1>;
3033                         #size-cells = <1>;
3034                         ranges = <0x0 0x84000 0x4000>;
3035                         /*
3036                          * Do not allow gating of cpsw clock as workaround
3037                          * for errata i877. Keeping internal clock disabled
3038                          * causes the device switching characteristics
3039                          * to degrade over time and eventually fail to meet
3040                          * the data manual delay time/skew specs.
3041                          */
3042                         ti,no-idle;
3043
3044                         mac: ethernet@0 {
3045                                 compatible = "ti,dra7-cpsw","ti,cpsw";
3046                                 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3047                                 clock-names = "fck", "cpts";
3048                                 cpdma_channels = <8>;
3049                                 ale_entries = <1024>;
3050                                 bd_ram_size = <0x2000>;
3051                                 mac_control = <0x20>;
3052                                 slaves = <2>;
3053                                 active_slave = <0>;
3054                                 cpts_clock_mult = <0x784CFE14>;
3055                                 cpts_clock_shift = <29>;
3056                                 reg = <0x0 0x1000
3057                                        0x1200 0x2e00>;
3058                                 #address-cells = <1>;
3059                                 #size-cells = <1>;
3060
3061                                 /*
3062                                  * rx_thresh_pend
3063                                  * rx_pend
3064                                  * tx_pend
3065                                  * misc_pend
3066                                  */
3067                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3068                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3069                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3070                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3071                                 ranges = <0 0 0x4000>;
3072                                 syscon = <&scm_conf>;
3073                                 status = "disabled";
3074
3075                                 davinci_mdio: mdio@1000 {
3076                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3077                                         clocks = <&gmac_main_clk>;
3078                                         clock-names = "fck";
3079                                         #address-cells = <1>;
3080                                         #size-cells = <0>;
3081                                         bus_freq = <1000000>;
3082                                         reg = <0x1000 0x100>;
3083                                 };
3084
3085                                 cpsw_emac0: slave@200 {
3086                                         /* Filled in by U-Boot */
3087                                         mac-address = [ 00 00 00 00 00 00 ];
3088                                         phys = <&phy_gmii_sel 1>;
3089                                 };
3090
3091                                 cpsw_emac1: slave@300 {
3092                                         /* Filled in by U-Boot */
3093                                         mac-address = [ 00 00 00 00 00 00 ];
3094                                         phys = <&phy_gmii_sel 2>;
3095                                 };
3096                         };
3097
3098                         mac_sw: switch@0 {
3099                                 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
3100                                 reg = <0x0 0x4000>;
3101                                 ranges = <0 0 0x4000>;
3102                                 clocks = <&gmac_main_clk>;
3103                                 clock-names = "fck";
3104                                 #address-cells = <1>;
3105                                 #size-cells = <1>;
3106                                 syscon = <&scm_conf>;
3107                                 status = "disabled";
3108
3109                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3110                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3111                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3112                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3113                                 interrupt-names = "rx_thresh", "rx", "tx", "misc";
3114
3115                                 ethernet-ports {
3116                                         #address-cells = <1>;
3117                                         #size-cells = <0>;
3118
3119                                         cpsw_port1: port@1 {
3120                                                 reg = <1>;
3121                                                 label = "port1";
3122                                                 mac-address = [ 00 00 00 00 00 00 ];
3123                                                 phys = <&phy_gmii_sel 1>;
3124                                         };
3125
3126                                         cpsw_port2: port@2 {
3127                                                 reg = <2>;
3128                                                 label = "port2";
3129                                                 mac-address = [ 00 00 00 00 00 00 ];
3130                                                 phys = <&phy_gmii_sel 2>;
3131                                         };
3132                                 };
3133
3134                                 davinci_mdio_sw: mdio@1000 {
3135                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3136                                         clocks = <&gmac_main_clk>;
3137                                         clock-names = "fck";
3138                                         #address-cells = <1>;
3139                                         #size-cells = <0>;
3140                                         bus_freq = <1000000>;
3141                                         reg = <0x1000 0x100>;
3142                                 };
3143
3144                                 cpts {
3145                                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3146                                         clock-names = "cpts";
3147                                 };
3148                         };
3149                 };
3150         };
3151 };
3152
3153 &l4_per3 {                                              /* 0x48800000 */
3154         compatible = "ti,dra7-l4-per3", "simple-bus";
3155         reg = <0x48800000 0x800>,
3156               <0x48800800 0x800>,
3157               <0x48801000 0x400>,
3158               <0x48801400 0x400>,
3159               <0x48801800 0x400>;
3160         reg-names = "ap", "la", "ia0", "ia1", "ia2";
3161         #address-cells = <1>;
3162         #size-cells = <1>;
3163         ranges = <0x00000000 0x48800000 0x200000>;      /* segment 0 */
3164
3165         segment@0 {                                     /* 0x48800000 */
3166                 compatible = "simple-bus";
3167                 #address-cells = <1>;
3168                 #size-cells = <1>;
3169                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
3170                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
3171                          <0x00001000 0x00001000 0x000400>,      /* ap 2 */
3172                          <0x00001400 0x00001400 0x000400>,      /* ap 3 */
3173                          <0x00001800 0x00001800 0x000400>,      /* ap 4 */
3174                          <0x00020000 0x00020000 0x001000>,      /* ap 5 */
3175                          <0x00021000 0x00021000 0x001000>,      /* ap 6 */
3176                          <0x00022000 0x00022000 0x001000>,      /* ap 7 */
3177                          <0x00023000 0x00023000 0x001000>,      /* ap 8 */
3178                          <0x00024000 0x00024000 0x001000>,      /* ap 9 */
3179                          <0x00025000 0x00025000 0x001000>,      /* ap 10 */
3180                          <0x00026000 0x00026000 0x001000>,      /* ap 11 */
3181                          <0x00027000 0x00027000 0x001000>,      /* ap 12 */
3182                          <0x00028000 0x00028000 0x001000>,      /* ap 13 */
3183                          <0x00029000 0x00029000 0x001000>,      /* ap 14 */
3184                          <0x0002a000 0x0002a000 0x001000>,      /* ap 15 */
3185                          <0x0002b000 0x0002b000 0x001000>,      /* ap 16 */
3186                          <0x0002c000 0x0002c000 0x001000>,      /* ap 17 */
3187                          <0x0002d000 0x0002d000 0x001000>,      /* ap 18 */
3188                          <0x0002e000 0x0002e000 0x001000>,      /* ap 19 */
3189                          <0x0002f000 0x0002f000 0x001000>,      /* ap 20 */
3190                          <0x00170000 0x00170000 0x010000>,      /* ap 21 */
3191                          <0x00180000 0x00180000 0x001000>,      /* ap 22 */
3192                          <0x00190000 0x00190000 0x010000>,      /* ap 23 */
3193                          <0x001a0000 0x001a0000 0x001000>,      /* ap 24 */
3194                          <0x001b0000 0x001b0000 0x010000>,      /* ap 25 */
3195                          <0x001c0000 0x001c0000 0x001000>,      /* ap 26 */
3196                          <0x001d0000 0x001d0000 0x010000>,      /* ap 27 */
3197                          <0x001e0000 0x001e0000 0x001000>,      /* ap 28 */
3198                          <0x00038000 0x00038000 0x001000>,      /* ap 29 */
3199                          <0x00039000 0x00039000 0x001000>,      /* ap 30 */
3200                          <0x0005c000 0x0005c000 0x001000>,      /* ap 31 */
3201                          <0x0005d000 0x0005d000 0x001000>,      /* ap 32 */
3202                          <0x0003a000 0x0003a000 0x001000>,      /* ap 33 */
3203                          <0x0003b000 0x0003b000 0x001000>,      /* ap 34 */
3204                          <0x0003c000 0x0003c000 0x001000>,      /* ap 35 */
3205                          <0x0003d000 0x0003d000 0x001000>,      /* ap 36 */
3206                          <0x0003e000 0x0003e000 0x001000>,      /* ap 37 */
3207                          <0x0003f000 0x0003f000 0x001000>,      /* ap 38 */
3208                          <0x00040000 0x00040000 0x001000>,      /* ap 39 */
3209                          <0x00041000 0x00041000 0x001000>,      /* ap 40 */
3210                          <0x00042000 0x00042000 0x001000>,      /* ap 41 */
3211                          <0x00043000 0x00043000 0x001000>,      /* ap 42 */
3212                          <0x00044000 0x00044000 0x001000>,      /* ap 43 */
3213                          <0x00045000 0x00045000 0x001000>,      /* ap 44 */
3214                          <0x00046000 0x00046000 0x001000>,      /* ap 45 */
3215                          <0x00047000 0x00047000 0x001000>,      /* ap 46 */
3216                          <0x00048000 0x00048000 0x001000>,      /* ap 47 */
3217                          <0x00049000 0x00049000 0x001000>,      /* ap 48 */
3218                          <0x0004a000 0x0004a000 0x001000>,      /* ap 49 */
3219                          <0x0004b000 0x0004b000 0x001000>,      /* ap 50 */
3220                          <0x0004c000 0x0004c000 0x001000>,      /* ap 51 */
3221                          <0x0004d000 0x0004d000 0x001000>,      /* ap 52 */
3222                          <0x0004e000 0x0004e000 0x001000>,      /* ap 53 */
3223                          <0x0004f000 0x0004f000 0x001000>,      /* ap 54 */
3224                          <0x00050000 0x00050000 0x001000>,      /* ap 55 */
3225                          <0x00051000 0x00051000 0x001000>,      /* ap 56 */
3226                          <0x00052000 0x00052000 0x001000>,      /* ap 57 */
3227                          <0x00053000 0x00053000 0x001000>,      /* ap 58 */
3228                          <0x00054000 0x00054000 0x001000>,      /* ap 59 */
3229                          <0x00055000 0x00055000 0x001000>,      /* ap 60 */
3230                          <0x00056000 0x00056000 0x001000>,      /* ap 61 */
3231                          <0x00057000 0x00057000 0x001000>,      /* ap 62 */
3232                          <0x00058000 0x00058000 0x001000>,      /* ap 63 */
3233                          <0x00059000 0x00059000 0x001000>,      /* ap 64 */
3234                          <0x0005a000 0x0005a000 0x001000>,      /* ap 65 */
3235                          <0x0005b000 0x0005b000 0x001000>,      /* ap 66 */
3236                          <0x00064000 0x00064000 0x001000>,      /* ap 67 */
3237                          <0x00065000 0x00065000 0x001000>,      /* ap 68 */
3238                          <0x0005e000 0x0005e000 0x001000>,      /* ap 69 */
3239                          <0x0005f000 0x0005f000 0x001000>,      /* ap 70 */
3240                          <0x00060000 0x00060000 0x001000>,      /* ap 71 */
3241                          <0x00061000 0x00061000 0x001000>,      /* ap 72 */
3242                          <0x00062000 0x00062000 0x001000>,      /* ap 73 */
3243                          <0x00063000 0x00063000 0x001000>,      /* ap 74 */
3244                          <0x00140000 0x00140000 0x020000>,      /* ap 75 */
3245                          <0x00160000 0x00160000 0x001000>,      /* ap 76 */
3246                          <0x00016000 0x00016000 0x001000>,      /* ap 77 */
3247                          <0x00017000 0x00017000 0x001000>,      /* ap 78 */
3248                          <0x000c0000 0x000c0000 0x020000>,      /* ap 79 */
3249                          <0x000e0000 0x000e0000 0x001000>,      /* ap 80 */
3250                          <0x00004000 0x00004000 0x001000>,      /* ap 81 */
3251                          <0x00005000 0x00005000 0x001000>,      /* ap 82 */
3252                          <0x00080000 0x00080000 0x020000>,      /* ap 83 */
3253                          <0x000a0000 0x000a0000 0x001000>,      /* ap 84 */
3254                          <0x00100000 0x00100000 0x020000>,      /* ap 85 */
3255                          <0x00120000 0x00120000 0x001000>,      /* ap 86 */
3256                          <0x00010000 0x00010000 0x001000>,      /* ap 87 */
3257                          <0x00011000 0x00011000 0x001000>,      /* ap 88 */
3258                          <0x0000a000 0x0000a000 0x001000>,      /* ap 89 */
3259                          <0x0000b000 0x0000b000 0x001000>,      /* ap 90 */
3260                          <0x0001c000 0x0001c000 0x001000>,      /* ap 91 */
3261                          <0x0001d000 0x0001d000 0x001000>,      /* ap 92 */
3262                          <0x0001e000 0x0001e000 0x001000>,      /* ap 93 */
3263                          <0x0001f000 0x0001f000 0x001000>,      /* ap 94 */
3264                          <0x00002000 0x00002000 0x001000>,      /* ap 95 */
3265                          <0x00003000 0x00003000 0x001000>;      /* ap 96 */
3266
3267                 target-module@2000 {                    /* 0x48802000, ap 95 7c.0 */
3268                         compatible = "ti,sysc-omap4", "ti,sysc";
3269                         reg = <0x2000 0x4>,
3270                               <0x2010 0x4>;
3271                         reg-names = "rev", "sysc";
3272                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3273                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3274                                         <SYSC_IDLE_NO>,
3275                                         <SYSC_IDLE_SMART>;
3276                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3277                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3278                         clock-names = "fck";
3279                         #address-cells = <1>;
3280                         #size-cells = <1>;
3281                         ranges = <0x0 0x2000 0x1000>;
3282
3283                         mailbox13: mailbox@0 {
3284                                 compatible = "ti,omap4-mailbox";
3285                                 reg = <0x0 0x200>;
3286                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3287                                              <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3288                                              <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3289                                              <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3290                                 #mbox-cells = <1>;
3291                                 ti,mbox-num-users = <4>;
3292                                 ti,mbox-num-fifos = <12>;
3293                                 status = "disabled";
3294                         };
3295                 };
3296
3297                 target-module@4000 {                    /* 0x48804000, ap 81 20.0 */
3298                         compatible = "ti,sysc";
3299                         status = "disabled";
3300                         #address-cells = <1>;
3301                         #size-cells = <1>;
3302                         ranges = <0x0 0x4000 0x1000>;
3303                 };
3304
3305                 target-module@a000 {                    /* 0x4880a000, ap 89 18.0 */
3306                         compatible = "ti,sysc";
3307                         status = "disabled";
3308                         #address-cells = <1>;
3309                         #size-cells = <1>;
3310                         ranges = <0x0 0xa000 0x1000>;
3311                 };
3312
3313                 target-module@10000 {                   /* 0x48810000, ap 87 28.0 */
3314                         compatible = "ti,sysc";
3315                         status = "disabled";
3316                         #address-cells = <1>;
3317                         #size-cells = <1>;
3318                         ranges = <0x0 0x10000 0x1000>;
3319                 };
3320
3321                 target-module@16000 {                   /* 0x48816000, ap 77 1e.0 */
3322                         compatible = "ti,sysc";
3323                         status = "disabled";
3324                         #address-cells = <1>;
3325                         #size-cells = <1>;
3326                         ranges = <0x0 0x16000 0x1000>;
3327                 };
3328
3329                 target-module@1c000 {                   /* 0x4881c000, ap 91 1c.0 */
3330                         compatible = "ti,sysc";
3331                         status = "disabled";
3332                         #address-cells = <1>;
3333                         #size-cells = <1>;
3334                         ranges = <0x0 0x1c000 0x1000>;
3335                 };
3336
3337                 target-module@1e000 {                   /* 0x4881e000, ap 93 2c.0 */
3338                         compatible = "ti,sysc";
3339                         status = "disabled";
3340                         #address-cells = <1>;
3341                         #size-cells = <1>;
3342                         ranges = <0x0 0x1e000 0x1000>;
3343                 };
3344
3345                 target-module@20000 {                   /* 0x48820000, ap 5 08.0 */
3346                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3347                         reg = <0x20000 0x4>,
3348                               <0x20010 0x4>;
3349                         reg-names = "rev", "sysc";
3350                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3351                                          SYSC_OMAP4_SOFTRESET)>;
3352                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3353                                         <SYSC_IDLE_NO>,
3354                                         <SYSC_IDLE_SMART>,
3355                                         <SYSC_IDLE_SMART_WKUP>;
3356                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3357                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3358                         clock-names = "fck";
3359                         #address-cells = <1>;
3360                         #size-cells = <1>;
3361                         ranges = <0x0 0x20000 0x1000>;
3362
3363                         timer5: timer@0 {
3364                                 compatible = "ti,omap5430-timer";
3365                                 reg = <0x0 0x80>;
3366                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
3367                                 clock-names = "fck";
3368                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3369                         };
3370                 };
3371
3372                 target-module@22000 {                   /* 0x48822000, ap 7 24.0 */
3373                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3374                         reg = <0x22000 0x4>,
3375                               <0x22010 0x4>;
3376                         reg-names = "rev", "sysc";
3377                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3378                                          SYSC_OMAP4_SOFTRESET)>;
3379                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3380                                         <SYSC_IDLE_NO>,
3381                                         <SYSC_IDLE_SMART>,
3382                                         <SYSC_IDLE_SMART_WKUP>;
3383                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3384                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3385                         clock-names = "fck";
3386                         #address-cells = <1>;
3387                         #size-cells = <1>;
3388                         ranges = <0x0 0x22000 0x1000>;
3389
3390                         timer6: timer@0 {
3391                                 compatible = "ti,omap5430-timer";
3392                                 reg = <0x0 0x80>;
3393                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
3394                                 clock-names = "fck";
3395                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3396                         };
3397                 };
3398
3399                 target-module@24000 {                   /* 0x48824000, ap 9 26.0 */
3400                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3401                         reg = <0x24000 0x4>,
3402                               <0x24010 0x4>;
3403                         reg-names = "rev", "sysc";
3404                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3405                                          SYSC_OMAP4_SOFTRESET)>;
3406                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3407                                         <SYSC_IDLE_NO>,
3408                                         <SYSC_IDLE_SMART>,
3409                                         <SYSC_IDLE_SMART_WKUP>;
3410                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3411                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3412                         clock-names = "fck";
3413                         #address-cells = <1>;
3414                         #size-cells = <1>;
3415                         ranges = <0x0 0x24000 0x1000>;
3416
3417                         timer7: timer@0 {
3418                                 compatible = "ti,omap5430-timer";
3419                                 reg = <0x0 0x80>;
3420                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
3421                                 clock-names = "fck";
3422                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3423                         };
3424                 };
3425
3426                 target-module@26000 {                   /* 0x48826000, ap 11 0c.0 */
3427                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3428                         reg = <0x26000 0x4>,
3429                               <0x26010 0x4>;
3430                         reg-names = "rev", "sysc";
3431                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3432                                          SYSC_OMAP4_SOFTRESET)>;
3433                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3434                                         <SYSC_IDLE_NO>,
3435                                         <SYSC_IDLE_SMART>,
3436                                         <SYSC_IDLE_SMART_WKUP>;
3437                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3438                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3439                         clock-names = "fck";
3440                         #address-cells = <1>;
3441                         #size-cells = <1>;
3442                         ranges = <0x0 0x26000 0x1000>;
3443
3444                         timer8: timer@0 {
3445                                 compatible = "ti,omap5430-timer";
3446                                 reg = <0x0 0x80>;
3447                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
3448                                 clock-names = "fck";
3449                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3450                         };
3451                 };
3452
3453                 target-module@28000 {                   /* 0x48828000, ap 13 16.0 */
3454                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3455                         reg = <0x28000 0x4>,
3456                               <0x28010 0x4>;
3457                         reg-names = "rev", "sysc";
3458                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3459                                          SYSC_OMAP4_SOFTRESET)>;
3460                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3461                                         <SYSC_IDLE_NO>,
3462                                         <SYSC_IDLE_SMART>,
3463                                         <SYSC_IDLE_SMART_WKUP>;
3464                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3465                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3466                         clock-names = "fck";
3467                         #address-cells = <1>;
3468                         #size-cells = <1>;
3469                         ranges = <0x0 0x28000 0x1000>;
3470
3471                         timer13: timer@0 {
3472                                 compatible = "ti,omap5430-timer";
3473                                 reg = <0x0 0x80>;
3474                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
3475                                 clock-names = "fck";
3476                                 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3477                                 ti,timer-pwm;
3478                         };
3479                 };
3480
3481                 target-module@2a000 {                   /* 0x4882a000, ap 15 10.0 */
3482                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3483                         reg = <0x2a000 0x4>,
3484                               <0x2a010 0x4>;
3485                         reg-names = "rev", "sysc";
3486                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3487                                          SYSC_OMAP4_SOFTRESET)>;
3488                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3489                                         <SYSC_IDLE_NO>,
3490                                         <SYSC_IDLE_SMART>,
3491                                         <SYSC_IDLE_SMART_WKUP>;
3492                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3493                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3494                         clock-names = "fck";
3495                         #address-cells = <1>;
3496                         #size-cells = <1>;
3497                         ranges = <0x0 0x2a000 0x1000>;
3498
3499                         timer14: timer@0 {
3500                                 compatible = "ti,omap5430-timer";
3501                                 reg = <0x0 0x80>;
3502                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
3503                                 clock-names = "fck";
3504                                 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3505                                 ti,timer-pwm;
3506                         };
3507                 };
3508
3509                 target-module@2c000 {                   /* 0x4882c000, ap 17 02.0 */
3510                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3511                         reg = <0x2c000 0x4>,
3512                               <0x2c010 0x4>;
3513                         reg-names = "rev", "sysc";
3514                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3515                                          SYSC_OMAP4_SOFTRESET)>;
3516                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3517                                         <SYSC_IDLE_NO>,
3518                                         <SYSC_IDLE_SMART>,
3519                                         <SYSC_IDLE_SMART_WKUP>;
3520                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3521                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3522                         clock-names = "fck";
3523                         #address-cells = <1>;
3524                         #size-cells = <1>;
3525                         ranges = <0x0 0x2c000 0x1000>;
3526
3527                         timer15: timer@0 {
3528                                 compatible = "ti,omap5430-timer";
3529                                 reg = <0x0 0x80>;
3530                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
3531                                 clock-names = "fck";
3532                                 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3533                                 ti,timer-pwm;
3534                         };
3535                 };
3536
3537                 target-module@2e000 {                   /* 0x4882e000, ap 19 14.0 */
3538                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3539                         reg = <0x2e000 0x4>,
3540                               <0x2e010 0x4>;
3541                         reg-names = "rev", "sysc";
3542                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3543                                          SYSC_OMAP4_SOFTRESET)>;
3544                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3545                                         <SYSC_IDLE_NO>,
3546                                         <SYSC_IDLE_SMART>,
3547                                         <SYSC_IDLE_SMART_WKUP>;
3548                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3549                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3550                         clock-names = "fck";
3551                         #address-cells = <1>;
3552                         #size-cells = <1>;
3553                         ranges = <0x0 0x2e000 0x1000>;
3554
3555                         timer16: timer@0 {
3556                                 compatible = "ti,omap5430-timer";
3557                                 reg = <0x0 0x80>;
3558                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
3559                                 clock-names = "fck";
3560                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3561                                 ti,timer-pwm;
3562                         };
3563                 };
3564
3565                 rtctarget: target-module@38000 {                        /* 0x48838000, ap 29 12.0 */
3566                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3567                         ti,hwmods = "rtcss";
3568                         reg = <0x38074 0x4>,
3569                               <0x38078 0x4>;
3570                         reg-names = "rev", "sysc";
3571                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3572                                         <SYSC_IDLE_NO>,
3573                                         <SYSC_IDLE_SMART>,
3574                                         <SYSC_IDLE_SMART_WKUP>;
3575                         /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3576                         clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3577                         clock-names = "fck";
3578                         #address-cells = <1>;
3579                         #size-cells = <1>;
3580                         ranges = <0x0 0x38000 0x1000>;
3581
3582                         rtc: rtc@0 {
3583                                 compatible = "ti,am3352-rtc";
3584                                 reg = <0x0 0x100>;
3585                                 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3586                                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3587                                 clocks = <&sys_32k_ck>;
3588                         };
3589                 };
3590
3591                 target-module@3a000 {                   /* 0x4883a000, ap 33 3e.0 */
3592                         compatible = "ti,sysc-omap4", "ti,sysc";
3593                         reg = <0x3a000 0x4>,
3594                               <0x3a010 0x4>;
3595                         reg-names = "rev", "sysc";
3596                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3597                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3598                                         <SYSC_IDLE_NO>,
3599                                         <SYSC_IDLE_SMART>;
3600                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3601                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3602                         clock-names = "fck";
3603                         #address-cells = <1>;
3604                         #size-cells = <1>;
3605                         ranges = <0x0 0x3a000 0x1000>;
3606
3607                         mailbox2: mailbox@0 {
3608                                 compatible = "ti,omap4-mailbox";
3609                                 reg = <0x0 0x200>;
3610                                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3611                                              <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3612                                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3613                                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3614                                 #mbox-cells = <1>;
3615                                 ti,mbox-num-users = <4>;
3616                                 ti,mbox-num-fifos = <12>;
3617                                 status = "disabled";
3618                         };
3619                 };
3620
3621                 target-module@3c000 {                   /* 0x4883c000, ap 35 3a.0 */
3622                         compatible = "ti,sysc-omap4", "ti,sysc";
3623                         reg = <0x3c000 0x4>,
3624                               <0x3c010 0x4>;
3625                         reg-names = "rev", "sysc";
3626                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3627                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3628                                         <SYSC_IDLE_NO>,
3629                                         <SYSC_IDLE_SMART>;
3630                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3631                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3632                         clock-names = "fck";
3633                         #address-cells = <1>;
3634                         #size-cells = <1>;
3635                         ranges = <0x0 0x3c000 0x1000>;
3636
3637                         mailbox3: mailbox@0 {
3638                                 compatible = "ti,omap4-mailbox";
3639                                 reg = <0x0 0x200>;
3640                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3641                                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3642                                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3643                                              <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3644                                 #mbox-cells = <1>;
3645                                 ti,mbox-num-users = <4>;
3646                                 ti,mbox-num-fifos = <12>;
3647                                 status = "disabled";
3648                         };
3649                 };
3650
3651                 target-module@3e000 {                   /* 0x4883e000, ap 37 46.0 */
3652                         compatible = "ti,sysc-omap4", "ti,sysc";
3653                         reg = <0x3e000 0x4>,
3654                               <0x3e010 0x4>;
3655                         reg-names = "rev", "sysc";
3656                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3657                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3658                                         <SYSC_IDLE_NO>,
3659                                         <SYSC_IDLE_SMART>;
3660                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3661                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3662                         clock-names = "fck";
3663                         #address-cells = <1>;
3664                         #size-cells = <1>;
3665                         ranges = <0x0 0x3e000 0x1000>;
3666
3667                         mailbox4: mailbox@0 {
3668                                 compatible = "ti,omap4-mailbox";
3669                                 reg = <0x0 0x200>;
3670                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3671                                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3672                                              <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3673                                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3674                                 #mbox-cells = <1>;
3675                                 ti,mbox-num-users = <4>;
3676                                 ti,mbox-num-fifos = <12>;
3677                                 status = "disabled";
3678                         };
3679                 };
3680
3681                 target-module@40000 {                   /* 0x48840000, ap 39 64.0 */
3682                         compatible = "ti,sysc-omap4", "ti,sysc";
3683                         reg = <0x40000 0x4>,
3684                               <0x40010 0x4>;
3685                         reg-names = "rev", "sysc";
3686                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3687                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3688                                         <SYSC_IDLE_NO>,
3689                                         <SYSC_IDLE_SMART>;
3690                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3691                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3692                         clock-names = "fck";
3693                         #address-cells = <1>;
3694                         #size-cells = <1>;
3695                         ranges = <0x0 0x40000 0x1000>;
3696
3697                         mailbox5: mailbox@0 {
3698                                 compatible = "ti,omap4-mailbox";
3699                                 reg = <0x0 0x200>;
3700                                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3701                                              <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3702                                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3703                                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3704                                 #mbox-cells = <1>;
3705                                 ti,mbox-num-users = <4>;
3706                                 ti,mbox-num-fifos = <12>;
3707                                 status = "disabled";
3708                         };
3709                 };
3710
3711                 target-module@42000 {                   /* 0x48842000, ap 41 4e.0 */
3712                         compatible = "ti,sysc-omap4", "ti,sysc";
3713                         reg = <0x42000 0x4>,
3714                               <0x42010 0x4>;
3715                         reg-names = "rev", "sysc";
3716                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3717                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3718                                         <SYSC_IDLE_NO>,
3719                                         <SYSC_IDLE_SMART>;
3720                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3721                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3722                         clock-names = "fck";
3723                         #address-cells = <1>;
3724                         #size-cells = <1>;
3725                         ranges = <0x0 0x42000 0x1000>;
3726
3727                         mailbox6: mailbox@0 {
3728                                 compatible = "ti,omap4-mailbox";
3729                                 reg = <0x0 0x200>;
3730                                 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3731                                              <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3732                                              <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3733                                              <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3734                                 #mbox-cells = <1>;
3735                                 ti,mbox-num-users = <4>;
3736                                 ti,mbox-num-fifos = <12>;
3737                                 status = "disabled";
3738                         };
3739                 };
3740
3741                 target-module@44000 {                   /* 0x48844000, ap 43 42.0 */
3742                         compatible = "ti,sysc-omap4", "ti,sysc";
3743                         reg = <0x44000 0x4>,
3744                               <0x44010 0x4>;
3745                         reg-names = "rev", "sysc";
3746                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3747                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3748                                         <SYSC_IDLE_NO>,
3749                                         <SYSC_IDLE_SMART>;
3750                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3751                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3752                         clock-names = "fck";
3753                         #address-cells = <1>;
3754                         #size-cells = <1>;
3755                         ranges = <0x0 0x44000 0x1000>;
3756
3757                         mailbox7: mailbox@0 {
3758                                 compatible = "ti,omap4-mailbox";
3759                                 reg = <0x0 0x200>;
3760                                 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3761                                              <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3762                                              <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3763                                              <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3764                                 #mbox-cells = <1>;
3765                                 ti,mbox-num-users = <4>;
3766                                 ti,mbox-num-fifos = <12>;
3767                                 status = "disabled";
3768                         };
3769                 };
3770
3771                 target-module@46000 {                   /* 0x48846000, ap 45 48.0 */
3772                         compatible = "ti,sysc-omap4", "ti,sysc";
3773                         reg = <0x46000 0x4>,
3774                               <0x46010 0x4>;
3775                         reg-names = "rev", "sysc";
3776                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3777                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3778                                         <SYSC_IDLE_NO>,
3779                                         <SYSC_IDLE_SMART>;
3780                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3781                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3782                         clock-names = "fck";
3783                         #address-cells = <1>;
3784                         #size-cells = <1>;
3785                         ranges = <0x0 0x46000 0x1000>;
3786
3787                         mailbox8: mailbox@0 {
3788                                 compatible = "ti,omap4-mailbox";
3789                                 reg = <0x0 0x200>;
3790                                 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3791                                              <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3792                                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3793                                              <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3794                                 #mbox-cells = <1>;
3795                                 ti,mbox-num-users = <4>;
3796                                 ti,mbox-num-fifos = <12>;
3797                                 status = "disabled";
3798                         };
3799                 };
3800
3801                 target-module@48000 {                   /* 0x48848000, ap 47 36.0 */
3802                         compatible = "ti,sysc";
3803                         status = "disabled";
3804                         #address-cells = <1>;
3805                         #size-cells = <1>;
3806                         ranges = <0x0 0x48000 0x1000>;
3807                 };
3808
3809                 target-module@4a000 {                   /* 0x4884a000, ap 49 38.0 */
3810                         compatible = "ti,sysc";
3811                         status = "disabled";
3812                         #address-cells = <1>;
3813                         #size-cells = <1>;
3814                         ranges = <0x0 0x4a000 0x1000>;
3815                 };
3816
3817                 target-module@4c000 {                   /* 0x4884c000, ap 51 44.0 */
3818                         compatible = "ti,sysc";
3819                         status = "disabled";
3820                         #address-cells = <1>;
3821                         #size-cells = <1>;
3822                         ranges = <0x0 0x4c000 0x1000>;
3823                 };
3824
3825                 target-module@4e000 {                   /* 0x4884e000, ap 53 4c.0 */
3826                         compatible = "ti,sysc";
3827                         status = "disabled";
3828                         #address-cells = <1>;
3829                         #size-cells = <1>;
3830                         ranges = <0x0 0x4e000 0x1000>;
3831                 };
3832
3833                 target-module@50000 {                   /* 0x48850000, ap 55 40.0 */
3834                         compatible = "ti,sysc";
3835                         status = "disabled";
3836                         #address-cells = <1>;
3837                         #size-cells = <1>;
3838                         ranges = <0x0 0x50000 0x1000>;
3839                 };
3840
3841                 target-module@52000 {                   /* 0x48852000, ap 57 54.0 */
3842                         compatible = "ti,sysc";
3843                         status = "disabled";
3844                         #address-cells = <1>;
3845                         #size-cells = <1>;
3846                         ranges = <0x0 0x52000 0x1000>;
3847                 };
3848
3849                 target-module@54000 {                   /* 0x48854000, ap 59 1a.0 */
3850                         compatible = "ti,sysc";
3851                         status = "disabled";
3852                         #address-cells = <1>;
3853                         #size-cells = <1>;
3854                         ranges = <0x0 0x54000 0x1000>;
3855                 };
3856
3857                 target-module@56000 {                   /* 0x48856000, ap 61 22.0 */
3858                         compatible = "ti,sysc";
3859                         status = "disabled";
3860                         #address-cells = <1>;
3861                         #size-cells = <1>;
3862                         ranges = <0x0 0x56000 0x1000>;
3863                 };
3864
3865                 target-module@58000 {                   /* 0x48858000, ap 63 2a.0 */
3866                         compatible = "ti,sysc";
3867                         status = "disabled";
3868                         #address-cells = <1>;
3869                         #size-cells = <1>;
3870                         ranges = <0x0 0x58000 0x1000>;
3871                 };
3872
3873                 target-module@5a000 {                   /* 0x4885a000, ap 65 5c.0 */
3874                         compatible = "ti,sysc";
3875                         status = "disabled";
3876                         #address-cells = <1>;
3877                         #size-cells = <1>;
3878                         ranges = <0x0 0x5a000 0x1000>;
3879                 };
3880
3881                 target-module@5c000 {                   /* 0x4885c000, ap 31 32.0 */
3882                         compatible = "ti,sysc";
3883                         status = "disabled";
3884                         #address-cells = <1>;
3885                         #size-cells = <1>;
3886                         ranges = <0x0 0x5c000 0x1000>;
3887                 };
3888
3889                 target-module@5e000 {                   /* 0x4885e000, ap 69 6c.0 */
3890                         compatible = "ti,sysc-omap4", "ti,sysc";
3891                         reg = <0x5e000 0x4>,
3892                               <0x5e010 0x4>;
3893                         reg-names = "rev", "sysc";
3894                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3895                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3896                                         <SYSC_IDLE_NO>,
3897                                         <SYSC_IDLE_SMART>;
3898                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3899                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3900                         clock-names = "fck";
3901                         #address-cells = <1>;
3902                         #size-cells = <1>;
3903                         ranges = <0x0 0x5e000 0x1000>;
3904
3905                         mailbox9: mailbox@0 {
3906                                 compatible = "ti,omap4-mailbox";
3907                                 reg = <0x0 0x200>;
3908                                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3909                                              <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3910                                              <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3911                                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3912                                 #mbox-cells = <1>;
3913                                 ti,mbox-num-users = <4>;
3914                                 ti,mbox-num-fifos = <12>;
3915                                 status = "disabled";
3916                         };
3917                 };
3918
3919                 target-module@60000 {                   /* 0x48860000, ap 71 4a.0 */
3920                         compatible = "ti,sysc-omap4", "ti,sysc";
3921                         reg = <0x60000 0x4>,
3922                               <0x60010 0x4>;
3923                         reg-names = "rev", "sysc";
3924                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3925                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3926                                         <SYSC_IDLE_NO>,
3927                                         <SYSC_IDLE_SMART>;
3928                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3929                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3930                         clock-names = "fck";
3931                         #address-cells = <1>;
3932                         #size-cells = <1>;
3933                         ranges = <0x0 0x60000 0x1000>;
3934
3935                         mailbox10: mailbox@0 {
3936                                 compatible = "ti,omap4-mailbox";
3937                                 reg = <0x0 0x200>;
3938                                 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3939                                              <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3940                                              <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3941                                              <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3942                                 #mbox-cells = <1>;
3943                                 ti,mbox-num-users = <4>;
3944                                 ti,mbox-num-fifos = <12>;
3945                                 status = "disabled";
3946                         };
3947                 };
3948
3949                 target-module@62000 {                   /* 0x48862000, ap 73 74.0 */
3950                         compatible = "ti,sysc-omap4", "ti,sysc";
3951                         reg = <0x62000 0x4>,
3952                               <0x62010 0x4>;
3953                         reg-names = "rev", "sysc";
3954                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3955                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3956                                         <SYSC_IDLE_NO>,
3957                                         <SYSC_IDLE_SMART>;
3958                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3959                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3960                         clock-names = "fck";
3961                         #address-cells = <1>;
3962                         #size-cells = <1>;
3963                         ranges = <0x0 0x62000 0x1000>;
3964
3965                         mailbox11: mailbox@0 {
3966                                 compatible = "ti,omap4-mailbox";
3967                                 reg = <0x0 0x200>;
3968                                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3969                                              <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3970                                              <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3971                                              <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3972                                 #mbox-cells = <1>;
3973                                 ti,mbox-num-users = <4>;
3974                                 ti,mbox-num-fifos = <12>;
3975                                 status = "disabled";
3976                         };
3977                 };
3978
3979                 target-module@64000 {                   /* 0x48864000, ap 67 52.0 */
3980                         compatible = "ti,sysc-omap4", "ti,sysc";
3981                         reg = <0x64000 0x4>,
3982                               <0x64010 0x4>;
3983                         reg-names = "rev", "sysc";
3984                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3985                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3986                                         <SYSC_IDLE_NO>,
3987                                         <SYSC_IDLE_SMART>;
3988                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3989                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3990                         clock-names = "fck";
3991                         #address-cells = <1>;
3992                         #size-cells = <1>;
3993                         ranges = <0x0 0x64000 0x1000>;
3994
3995                         mailbox12: mailbox@0 {
3996                                 compatible = "ti,omap4-mailbox";
3997                                 reg = <0x0 0x200>;
3998                                 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3999                                              <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
4000                                              <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
4001                                              <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
4002                                 #mbox-cells = <1>;
4003                                 ti,mbox-num-users = <4>;
4004                                 ti,mbox-num-fifos = <12>;
4005                                 status = "disabled";
4006                         };
4007                 };
4008
4009                 target-module@80000 {                   /* 0x48880000, ap 83 0e.1 */
4010                         compatible = "ti,sysc-omap4", "ti,sysc";
4011                         ti,hwmods = "usb_otg_ss1";
4012                         reg = <0x80000 0x4>,
4013                               <0x80010 0x4>;
4014                         reg-names = "rev", "sysc";
4015                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4016                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4017                                         <SYSC_IDLE_NO>,
4018                                         <SYSC_IDLE_SMART>,
4019                                         <SYSC_IDLE_SMART_WKUP>;
4020                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4021                                         <SYSC_IDLE_NO>,
4022                                         <SYSC_IDLE_SMART>,
4023                                         <SYSC_IDLE_SMART_WKUP>;
4024                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4025                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
4026                         clock-names = "fck";
4027                         #address-cells = <1>;
4028                         #size-cells = <1>;
4029                         ranges = <0x0 0x80000 0x20000>;
4030
4031                         omap_dwc3_1: omap_dwc3_1@0 {
4032                                 compatible = "ti,dwc3";
4033                                 reg = <0x0 0x10000>;
4034                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4035                                 #address-cells = <1>;
4036                                 #size-cells = <1>;
4037                                 utmi-mode = <2>;
4038                                 ranges = <0 0 0x20000>;
4039
4040                                 usb1: usb@10000 {
4041                                         compatible = "snps,dwc3";
4042                                         reg = <0x10000 0x17000>;
4043                                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4044                                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4045                                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4046                                         interrupt-names = "peripheral",
4047                                                           "host",
4048                                                           "otg";
4049                                         phys = <&usb2_phy1>, <&usb3_phy1>;
4050                                         phy-names = "usb2-phy", "usb3-phy";
4051                                         maximum-speed = "super-speed";
4052                                         dr_mode = "otg";
4053                                         snps,dis_u3_susphy_quirk;
4054                                         snps,dis_u2_susphy_quirk;
4055                                 };
4056                         };
4057                 };
4058
4059                 target-module@c0000 {                   /* 0x488c0000, ap 79 06.0 */
4060                         compatible = "ti,sysc-omap4", "ti,sysc";
4061                         ti,hwmods = "usb_otg_ss2";
4062                         reg = <0xc0000 0x4>,
4063                               <0xc0010 0x4>;
4064                         reg-names = "rev", "sysc";
4065                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4066                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4067                                         <SYSC_IDLE_NO>,
4068                                         <SYSC_IDLE_SMART>,
4069                                         <SYSC_IDLE_SMART_WKUP>;
4070                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4071                                         <SYSC_IDLE_NO>,
4072                                         <SYSC_IDLE_SMART>,
4073                                         <SYSC_IDLE_SMART_WKUP>;
4074                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4075                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4076                         clock-names = "fck";
4077                         #address-cells = <1>;
4078                         #size-cells = <1>;
4079                         ranges = <0x0 0xc0000 0x20000>;
4080
4081                         omap_dwc3_2: omap_dwc3_2@0 {
4082                                 compatible = "ti,dwc3";
4083                                 reg = <0x0 0x10000>;
4084                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4085                                 #address-cells = <1>;
4086                                 #size-cells = <1>;
4087                                 utmi-mode = <2>;
4088                                 ranges = <0 0 0x20000>;
4089
4090                                 usb2: usb@10000 {
4091                                         compatible = "snps,dwc3";
4092                                         reg = <0x10000 0x17000>;
4093                                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4094                                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4095                                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4096                                         interrupt-names = "peripheral",
4097                                                           "host",
4098                                                           "otg";
4099                                         phys = <&usb2_phy2>;
4100                                         phy-names = "usb2-phy";
4101                                         maximum-speed = "high-speed";
4102                                         dr_mode = "otg";
4103                                         snps,dis_u3_susphy_quirk;
4104                                         snps,dis_u2_susphy_quirk;
4105                                         snps,dis_metastability_quirk;
4106                                 };
4107                         };
4108                 };
4109
4110                 usb3_tm: target-module@100000 {         /* 0x48900000, ap 85 04.0 */
4111                         compatible = "ti,sysc-omap4", "ti,sysc";
4112                         ti,hwmods = "usb_otg_ss3";
4113                         reg = <0x100000 0x4>,
4114                               <0x100010 0x4>;
4115                         reg-names = "rev", "sysc";
4116                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4117                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4118                                         <SYSC_IDLE_NO>,
4119                                         <SYSC_IDLE_SMART>,
4120                                         <SYSC_IDLE_SMART_WKUP>;
4121                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4122                                         <SYSC_IDLE_NO>,
4123                                         <SYSC_IDLE_SMART>,
4124                                         <SYSC_IDLE_SMART_WKUP>;
4125                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4126                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4127                         clock-names = "fck";
4128                         #address-cells = <1>;
4129                         #size-cells = <1>;
4130                         ranges = <0x0 0x100000 0x20000>;
4131
4132                         omap_dwc3_3: omap_dwc3_3@0 {
4133                                 compatible = "ti,dwc3";
4134                                 reg = <0x0 0x10000>;
4135                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4136                                 #address-cells = <1>;
4137                                 #size-cells = <1>;
4138                                 utmi-mode = <2>;
4139                                 ranges = <0 0 0x20000>;
4140                                 status = "disabled";
4141
4142                                 usb3: usb@10000 {
4143                                         compatible = "snps,dwc3";
4144                                         reg = <0x10000 0x17000>;
4145                                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4146                                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4147                                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4148                                         interrupt-names = "peripheral",
4149                                                           "host",
4150                                                           "otg";
4151                                         maximum-speed = "high-speed";
4152                                         dr_mode = "otg";
4153                                         snps,dis_u3_susphy_quirk;
4154                                         snps,dis_u2_susphy_quirk;
4155                                 };
4156                         };
4157                 };
4158
4159                 usb4_tm: target-module@140000 {         /* 0x48940000, ap 75 3c.0 */
4160                         compatible = "ti,sysc-omap4", "ti,sysc";
4161                         ti,hwmods = "usb_otg_ss4";
4162                         reg = <0x140000 0x4>,
4163                               <0x140010 0x4>;
4164                         reg-names = "rev", "sysc";
4165                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4166                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4167                                         <SYSC_IDLE_NO>,
4168                                         <SYSC_IDLE_SMART>,
4169                                         <SYSC_IDLE_SMART_WKUP>;
4170                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4171                                         <SYSC_IDLE_NO>,
4172                                         <SYSC_IDLE_SMART>,
4173                                         <SYSC_IDLE_SMART_WKUP>;
4174                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4175                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4176                         clock-names = "fck";
4177                         #address-cells = <1>;
4178                         #size-cells = <1>;
4179                         ranges = <0x0 0x140000 0x20000>;
4180                 };
4181
4182                 target-module@170000 {                  /* 0x48970000, ap 21 0a.0 */
4183                         compatible = "ti,sysc-omap4", "ti,sysc";
4184                         reg = <0x170010 0x4>;
4185                         reg-names = "sysc";
4186                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4187                                         <SYSC_IDLE_NO>,
4188                                         <SYSC_IDLE_SMART>;
4189                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4190                                         <SYSC_IDLE_NO>,
4191                                         <SYSC_IDLE_SMART>;
4192                         clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4193                         clock-names = "fck";
4194                         #address-cells = <1>;
4195                         #size-cells = <1>;
4196                         ranges = <0x0 0x170000 0x10000>;
4197                         status = "disabled";
4198                 };
4199
4200                 target-module@190000 {                  /* 0x48990000, ap 23 2e.0 */
4201                         compatible = "ti,sysc-omap4", "ti,sysc";
4202                         reg = <0x190010 0x4>;
4203                         reg-names = "sysc";
4204                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4205                                         <SYSC_IDLE_NO>,
4206                                         <SYSC_IDLE_SMART>;
4207                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4208                                         <SYSC_IDLE_NO>,
4209                                         <SYSC_IDLE_SMART>;
4210                         clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4211                         clock-names = "fck";
4212                         #address-cells = <1>;
4213                         #size-cells = <1>;
4214                         ranges = <0x0 0x190000 0x10000>;
4215                         status = "disabled";
4216                 };
4217
4218                 target-module@1b0000 {                  /* 0x489b0000, ap 25 34.0 */
4219                         compatible = "ti,sysc-omap4", "ti,sysc";
4220                         reg = <0x1b0000 0x4>,
4221                               <0x1b0010 0x4>;
4222                         reg-names = "rev", "sysc";
4223                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4224                                         <SYSC_IDLE_NO>,
4225                                         <SYSC_IDLE_SMART>;
4226                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4227                                         <SYSC_IDLE_NO>,
4228                                         <SYSC_IDLE_SMART>;
4229                         clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4230                         clock-names = "fck";
4231                         #address-cells = <1>;
4232                         #size-cells = <1>;
4233                         ranges = <0x0 0x1b0000 0x10000>;
4234                         status = "disabled";
4235                 };
4236
4237                 target-module@1d0010 {                  /* 0x489d0000, ap 27 30.0 */
4238                         compatible = "ti,sysc-omap4", "ti,sysc";
4239                         reg = <0x1d0010 0x4>;
4240                         reg-names = "sysc";
4241                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4242                                         <SYSC_IDLE_NO>,
4243                                         <SYSC_IDLE_SMART>;
4244                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4245                                         <SYSC_IDLE_NO>,
4246                                         <SYSC_IDLE_SMART>;
4247                         clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4248                         clock-names = "fck";
4249                         #address-cells = <1>;
4250                         #size-cells = <1>;
4251                         ranges = <0x0 0x1d0000 0x10000>;
4252
4253                         vpe: vpe@0 {
4254                                 compatible = "ti,dra7-vpe";
4255                                 reg = <0x0000 0x120>,
4256                                       <0x0700 0x80>,
4257                                       <0x5700 0x18>,
4258                                       <0xd000 0x400>;
4259                                 reg-names = "vpe_top",
4260                                             "sc",
4261                                             "csc",
4262                                             "vpdma";
4263                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
4264                         };
4265                 };
4266         };
4267 };
4268
4269 &l4_wkup {                                              /* 0x4ae00000 */
4270         compatible = "ti,dra7-l4-wkup", "simple-bus";
4271         reg = <0x4ae00000 0x800>,
4272               <0x4ae00800 0x800>,
4273               <0x4ae01000 0x1000>;
4274         reg-names = "ap", "la", "ia0";
4275         #address-cells = <1>;
4276         #size-cells = <1>;
4277         ranges = <0x00000000 0x4ae00000 0x010000>,      /* segment 0 */
4278                  <0x00010000 0x4ae10000 0x010000>,      /* segment 1 */
4279                  <0x00020000 0x4ae20000 0x010000>,      /* segment 2 */
4280                  <0x00030000 0x4ae30000 0x010000>;      /* segment 3 */
4281
4282         segment@0 {                                     /* 0x4ae00000 */
4283                 compatible = "simple-bus";
4284                 #address-cells = <1>;
4285                 #size-cells = <1>;
4286                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
4287                          <0x00001000 0x00001000 0x001000>,      /* ap 1 */
4288                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
4289                          <0x00006000 0x00006000 0x002000>,      /* ap 3 */
4290                          <0x00008000 0x00008000 0x001000>,      /* ap 4 */
4291                          <0x00004000 0x00004000 0x001000>,      /* ap 15 */
4292                          <0x00005000 0x00005000 0x001000>,      /* ap 16 */
4293                          <0x0000c000 0x0000c000 0x001000>,      /* ap 17 */
4294                          <0x0000d000 0x0000d000 0x001000>;      /* ap 18 */
4295
4296                 target-module@4000 {                    /* 0x4ae04000, ap 15 40.0 */
4297                         compatible = "ti,sysc-omap2", "ti,sysc";
4298                         ti,hwmods = "counter_32k";
4299                         reg = <0x4000 0x4>,
4300                               <0x4010 0x4>;
4301                         reg-names = "rev", "sysc";
4302                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4303                                         <SYSC_IDLE_NO>,
4304                                         <SYSC_IDLE_SMART>,
4305                                         <SYSC_IDLE_SMART_WKUP>;
4306                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4307                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4308                         clock-names = "fck";
4309                         #address-cells = <1>;
4310                         #size-cells = <1>;
4311                         ranges = <0x0 0x4000 0x1000>;
4312
4313                         counter32k: counter@0 {
4314                                 compatible = "ti,omap-counter32k";
4315                                 reg = <0x0 0x40>;
4316                         };
4317                 };
4318
4319                 target-module@6000 {                    /* 0x4ae06000, ap 3 10.0 */
4320                         compatible = "ti,sysc-omap4", "ti,sysc";
4321                         reg = <0x6000 0x4>;
4322                         reg-names = "rev";
4323                         #address-cells = <1>;
4324                         #size-cells = <1>;
4325                         ranges = <0x0 0x6000 0x2000>;
4326
4327                         prm: prm@0 {
4328                                 compatible = "ti,dra7-prm", "simple-bus";
4329                                 reg = <0 0x3000>;
4330                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4331                                 #address-cells = <1>;
4332                                 #size-cells = <1>;
4333                                 ranges = <0 0 0x3000>;
4334
4335                                 prm_clocks: clocks {
4336                                         #address-cells = <1>;
4337                                         #size-cells = <0>;
4338                                 };
4339
4340                                 prm_clockdomains: clockdomains {
4341                                 };
4342                         };
4343                 };
4344
4345                 target-module@c000 {                    /* 0x4ae0c000, ap 17 50.0 */
4346                         compatible = "ti,sysc-omap4", "ti,sysc";
4347                         reg = <0xc000 0x4>;
4348                         reg-names = "rev";
4349                         #address-cells = <1>;
4350                         #size-cells = <1>;
4351                         ranges = <0x0 0xc000 0x1000>;
4352
4353                         scm_wkup: scm_conf@0 {
4354                                 compatible = "syscon";
4355                                 reg = <0 0x1000>;
4356                         };
4357                 };
4358         };
4359
4360         segment@10000 {                                 /* 0x4ae10000 */
4361                 compatible = "simple-bus";
4362                 #address-cells = <1>;
4363                 #size-cells = <1>;
4364                 ranges = <0x00000000 0x00010000 0x001000>,      /* ap 5 */
4365                          <0x00001000 0x00011000 0x001000>,      /* ap 6 */
4366                          <0x00004000 0x00014000 0x001000>,      /* ap 7 */
4367                          <0x00005000 0x00015000 0x001000>,      /* ap 8 */
4368                          <0x00008000 0x00018000 0x001000>,      /* ap 9 */
4369                          <0x00009000 0x00019000 0x001000>,      /* ap 10 */
4370                          <0x0000c000 0x0001c000 0x001000>,      /* ap 11 */
4371                          <0x0000d000 0x0001d000 0x001000>;      /* ap 12 */
4372
4373                 target-module@0 {                       /* 0x4ae10000, ap 5 20.0 */
4374                         compatible = "ti,sysc-omap2", "ti,sysc";
4375                         reg = <0x0 0x4>,
4376                               <0x10 0x4>,
4377                               <0x114 0x4>;
4378                         reg-names = "rev", "sysc", "syss";
4379                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4380                                          SYSC_OMAP2_SOFTRESET |
4381                                          SYSC_OMAP2_AUTOIDLE)>;
4382                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4383                                         <SYSC_IDLE_NO>,
4384                                         <SYSC_IDLE_SMART>,
4385                                         <SYSC_IDLE_SMART_WKUP>;
4386                         ti,syss-mask = <1>;
4387                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4388                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4389                                  <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4390                         clock-names = "fck", "dbclk";
4391                         #address-cells = <1>;
4392                         #size-cells = <1>;
4393                         ranges = <0x0 0x0 0x1000>;
4394
4395                         gpio1: gpio@0 {
4396                                 compatible = "ti,omap4-gpio";
4397                                 reg = <0x0 0x200>;
4398                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4399                                 gpio-controller;
4400                                 #gpio-cells = <2>;
4401                                 interrupt-controller;
4402                                 #interrupt-cells = <2>;
4403                         };
4404                 };
4405
4406                 target-module@4000 {                    /* 0x4ae14000, ap 7 28.0 */
4407                         compatible = "ti,sysc-omap2", "ti,sysc";
4408                         reg = <0x4000 0x4>,
4409                               <0x4010 0x4>,
4410                               <0x4014 0x4>;
4411                         reg-names = "rev", "sysc", "syss";
4412                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4413                                          SYSC_OMAP2_SOFTRESET)>;
4414                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4415                                         <SYSC_IDLE_NO>,
4416                                         <SYSC_IDLE_SMART>,
4417                                         <SYSC_IDLE_SMART_WKUP>;
4418                         ti,syss-mask = <1>;
4419                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4420                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4421                         clock-names = "fck";
4422                         #address-cells = <1>;
4423                         #size-cells = <1>;
4424                         ranges = <0x0 0x4000 0x1000>;
4425
4426                         wdt2: wdt@0 {
4427                                 compatible = "ti,omap3-wdt";
4428                                 reg = <0x0 0x80>;
4429                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4430                         };
4431                 };
4432
4433                 target-module@8000 {                    /* 0x4ae18000, ap 9 30.0 */
4434                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4435                         ti,hwmods = "timer1";
4436                         reg = <0x8000 0x4>,
4437                               <0x8010 0x4>;
4438                         reg-names = "rev", "sysc";
4439                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4440                                          SYSC_OMAP4_SOFTRESET)>;
4441                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4442                                         <SYSC_IDLE_NO>,
4443                                         <SYSC_IDLE_SMART>,
4444                                         <SYSC_IDLE_SMART_WKUP>;
4445                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4446                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4447                         clock-names = "fck";
4448                         #address-cells = <1>;
4449                         #size-cells = <1>;
4450                         ranges = <0x0 0x8000 0x1000>;
4451
4452                         timer1: timer@0 {
4453                                 compatible = "ti,omap5430-timer";
4454                                 reg = <0x0 0x80>;
4455                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4456                                 clock-names = "fck";
4457                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4458                                 ti,timer-alwon;
4459                         };
4460                 };
4461
4462                 target-module@c000 {                    /* 0x4ae1c000, ap 11 38.0 */
4463                         compatible = "ti,sysc";
4464                         status = "disabled";
4465                         #address-cells = <1>;
4466                         #size-cells = <1>;
4467                         ranges = <0x0 0xc000 0x1000>;
4468                 };
4469         };
4470
4471         segment@20000 {                                 /* 0x4ae20000 */
4472                 compatible = "simple-bus";
4473                 #address-cells = <1>;
4474                 #size-cells = <1>;
4475                 ranges = <0x00006000 0x00026000 0x001000>,      /* ap 13 */
4476                          <0x0000a000 0x0002a000 0x001000>,      /* ap 14 */
4477                          <0x00000000 0x00020000 0x001000>,      /* ap 19 */
4478                          <0x00001000 0x00021000 0x001000>,      /* ap 20 */
4479                          <0x00002000 0x00022000 0x001000>,      /* ap 21 */
4480                          <0x00003000 0x00023000 0x001000>,      /* ap 22 */
4481                          <0x00007000 0x00027000 0x000400>,      /* ap 23 */
4482                          <0x00008000 0x00028000 0x000800>,      /* ap 24 */
4483                          <0x00009000 0x00029000 0x000100>,      /* ap 25 */
4484                          <0x00008800 0x00028800 0x000200>,      /* ap 26 */
4485                          <0x00008a00 0x00028a00 0x000100>,      /* ap 27 */
4486                          <0x0000b000 0x0002b000 0x001000>,      /* ap 28 */
4487                          <0x0000c000 0x0002c000 0x001000>,      /* ap 29 */
4488                          <0x0000f000 0x0002f000 0x001000>;      /* ap 32 */
4489
4490                 target-module@0 {                       /* 0x4ae20000, ap 19 08.0 */
4491                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4492                         reg = <0x0 0x4>,
4493                               <0x10 0x4>;
4494                         reg-names = "rev", "sysc";
4495                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4496                                          SYSC_OMAP4_SOFTRESET)>;
4497                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4498                                         <SYSC_IDLE_NO>,
4499                                         <SYSC_IDLE_SMART>,
4500                                         <SYSC_IDLE_SMART_WKUP>;
4501                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4502                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4503                         clock-names = "fck";
4504                         #address-cells = <1>;
4505                         #size-cells = <1>;
4506                         ranges = <0x0 0x0 0x1000>;
4507
4508                         timer12: timer@0 {
4509                                 compatible = "ti,omap5430-timer";
4510                                 reg = <0x0 0x80>;
4511                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4512                                 ti,timer-alwon;
4513                                 ti,timer-secure;
4514                         };
4515                 };
4516
4517                 target-module@2000 {                    /* 0x4ae22000, ap 21 18.0 */
4518                         compatible = "ti,sysc";
4519                         status = "disabled";
4520                         #address-cells = <1>;
4521                         #size-cells = <1>;
4522                         ranges = <0x0 0x2000 0x1000>;
4523                 };
4524
4525                 target-module@6000 {                    /* 0x4ae26000, ap 13 48.0 */
4526                         compatible = "ti,sysc";
4527                         status = "disabled";
4528                         #address-cells = <1>;
4529                         #size-cells = <1>;
4530                         ranges = <0x00000000 0x00006000 0x00001000>,
4531                                  <0x00001000 0x00007000 0x00000400>,
4532                                  <0x00002000 0x00008000 0x00000800>,
4533                                  <0x00002800 0x00008800 0x00000200>,
4534                                  <0x00002a00 0x00008a00 0x00000100>,
4535                                  <0x00003000 0x00009000 0x00000100>;
4536                 };
4537
4538                 target-module@b000 {                    /* 0x4ae2b000, ap 28 02.0 */
4539                         compatible = "ti,sysc-omap2", "ti,sysc";
4540                         reg = <0xb050 0x4>,
4541                               <0xb054 0x4>,
4542                               <0xb058 0x4>;
4543                         reg-names = "rev", "sysc", "syss";
4544                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4545                                          SYSC_OMAP2_SOFTRESET |
4546                                          SYSC_OMAP2_AUTOIDLE)>;
4547                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4548                                         <SYSC_IDLE_NO>,
4549                                         <SYSC_IDLE_SMART>,
4550                                         <SYSC_IDLE_SMART_WKUP>;
4551                         ti,syss-mask = <1>;
4552                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4553                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4554                         clock-names = "fck";
4555                         #address-cells = <1>;
4556                         #size-cells = <1>;
4557                         ranges = <0x0 0xb000 0x1000>;
4558
4559                         uart10: serial@0 {
4560                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
4561                                 reg = <0x0 0x100>;
4562                                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4563                                 clock-frequency = <48000000>;
4564                                 status = "disabled";
4565                         };
4566                 };
4567
4568                 target-module@f000 {                    /* 0x4ae2f000, ap 32 58.0 */
4569                         compatible = "ti,sysc";
4570                         status = "disabled";
4571                         #address-cells = <1>;
4572                         #size-cells = <1>;
4573                         ranges = <0x0 0xf000 0x1000>;
4574                 };
4575         };
4576
4577         segment@30000 {                                 /* 0x4ae30000 */
4578                 compatible = "simple-bus";
4579                 #address-cells = <1>;
4580                 #size-cells = <1>;
4581                 ranges = <0x0000c000 0x0003c000 0x002000>,      /* ap 30 */
4582                          <0x0000e000 0x0003e000 0x001000>,      /* ap 31 */
4583                          <0x00000000 0x00030000 0x001000>,      /* ap 33 */
4584                          <0x00001000 0x00031000 0x001000>,      /* ap 34 */
4585                          <0x00002000 0x00032000 0x001000>,      /* ap 35 */
4586                          <0x00003000 0x00033000 0x001000>,      /* ap 36 */
4587                          <0x00004000 0x00034000 0x001000>,      /* ap 37 */
4588                          <0x00005000 0x00035000 0x001000>,      /* ap 38 */
4589                          <0x00006000 0x00036000 0x001000>,      /* ap 39 */
4590                          <0x00007000 0x00037000 0x001000>,      /* ap 40 */
4591                          <0x00008000 0x00038000 0x001000>,      /* ap 41 */
4592                          <0x00009000 0x00039000 0x001000>,      /* ap 42 */
4593                          <0x0000a000 0x0003a000 0x001000>;      /* ap 43 */
4594
4595                 target-module@1000 {                    /* 0x4ae31000, ap 34 60.0 */
4596                         compatible = "ti,sysc";
4597                         status = "disabled";
4598                         #address-cells = <1>;
4599                         #size-cells = <1>;
4600                         ranges = <0x0 0x1000 0x1000>;
4601                 };
4602
4603                 target-module@3000 {                    /* 0x4ae33000, ap 36 0a.0 */
4604                         compatible = "ti,sysc";
4605                         status = "disabled";
4606                         #address-cells = <1>;
4607                         #size-cells = <1>;
4608                         ranges = <0x0 0x3000 0x1000>;
4609                 };
4610
4611                 target-module@5000 {                    /* 0x4ae35000, ap 38 0c.0 */
4612                         compatible = "ti,sysc";
4613                         status = "disabled";
4614                         #address-cells = <1>;
4615                         #size-cells = <1>;
4616                         ranges = <0x0 0x5000 0x1000>;
4617                 };
4618
4619                 target-module@7000 {                    /* 0x4ae37000, ap 40 68.0 */
4620                         compatible = "ti,sysc";
4621                         status = "disabled";
4622                         #address-cells = <1>;
4623                         #size-cells = <1>;
4624                         ranges = <0x0 0x7000 0x1000>;
4625                 };
4626
4627                 target-module@9000 {                    /* 0x4ae39000, ap 42 70.0 */
4628                         compatible = "ti,sysc";
4629                         status = "disabled";
4630                         #address-cells = <1>;
4631                         #size-cells = <1>;
4632                         ranges = <0x0 0x9000 0x1000>;
4633                 };
4634
4635                 target-module@c000 {                    /* 0x4ae3c000, ap 30 04.0 */
4636                         compatible = "ti,sysc-omap4", "ti,sysc";
4637                         reg = <0xc020 0x4>;
4638                         reg-names = "rev";
4639                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4640                         clock-names = "fck";
4641                         #address-cells = <1>;
4642                         #size-cells = <1>;
4643                         ranges = <0x0 0xc000 0x2000>;
4644
4645                         dcan1: can@0 {
4646                                 compatible = "ti,dra7-d_can";
4647                                 reg = <0x0 0x2000>;
4648                                 syscon-raminit = <&scm_conf 0x558 0>;
4649                                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4650                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4651                                 status = "disabled";
4652                         };
4653                 };
4654         };
4655 };
4656