2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "dra74x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
13 #include <dt-bindings/input/input.h>
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
20 device_type = "memory";
21 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
28 evm_3v3_sd: fixedregulator-sd {
29 compatible = "regulator-fixed";
30 regulator-name = "evm_3v3_sd";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
34 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
37 evm_3v3_sw: fixedregulator-evm_3v3_sw {
38 compatible = "regulator-fixed";
39 regulator-name = "evm_3v3_sw";
40 vin-supply = <&sysen1>;
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
45 aic_dvdd: fixedregulator-aic_dvdd {
47 compatible = "regulator-fixed";
48 regulator-name = "aic_dvdd";
49 vin-supply = <&evm_3v3_sw>;
50 regulator-min-microvolt = <1800000>;
51 regulator-max-microvolt = <1800000>;
54 extcon_usb1: extcon_usb1 {
55 compatible = "linux,extcon-usb-gpio";
56 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
59 extcon_usb2: extcon_usb2 {
60 compatible = "linux,extcon-usb-gpio";
61 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
64 vtt_fixed: fixedregulator-vtt {
65 compatible = "regulator-fixed";
66 regulator-name = "vtt_fixed";
67 regulator-min-microvolt = <1350000>;
68 regulator-max-microvolt = <1350000>;
72 vin-supply = <&sysen2>;
73 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
77 compatible = "simple-audio-card";
78 simple-audio-card,name = "DRA7xx-EVM";
79 simple-audio-card,widgets =
80 "Headphone", "Headphone Jack",
82 "Microphone", "Mic Jack",
84 simple-audio-card,routing =
85 "Headphone Jack", "HPLOUT",
86 "Headphone Jack", "HPROUT",
91 "Mic Jack", "Mic Bias",
94 simple-audio-card,format = "dsp_b";
95 simple-audio-card,bitclock-master = <&sound0_master>;
96 simple-audio-card,frame-master = <&sound0_master>;
97 simple-audio-card,bitclock-inversion;
99 sound0_master: simple-audio-card,cpu {
100 sound-dai = <&mcasp3>;
101 system-clock-frequency = <5644800>;
104 simple-audio-card,codec {
105 sound-dai = <&tlv320aic3106>;
106 clocks = <&atl_clkin2_ck>;
111 compatible = "gpio-leds";
114 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
115 default-state = "off";
120 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
121 default-state = "off";
126 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
127 default-state = "off";
132 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
133 default-state = "off";
138 compatible = "gpio-keys";
139 #address-cells = <1>;
145 linux,code = <BTN_0>;
146 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
151 linux,code = <BTN_1>;
152 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
158 dcan1_pins_default: dcan1_pins_default {
159 pinctrl-single,pins = <
160 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
161 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
165 dcan1_pins_sleep: dcan1_pins_sleep {
166 pinctrl-single,pins = <
167 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
168 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
172 mmc1_pins_default: mmc1_pins_default {
173 pinctrl-single,pins = <
174 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
175 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
176 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
177 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
178 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
179 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
180 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
184 mmc2_pins_default: mmc2_pins_default {
185 pinctrl-single,pins = <
186 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
187 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
188 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
189 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
190 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
191 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
192 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
193 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
194 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
195 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
202 clock-frequency = <400000>;
204 tps659038: tps659038@58 {
205 compatible = "ti,tps659038";
207 ti,palmas-override-powerhold;
208 ti,system-power-controller;
211 compatible = "ti,tps659038-pmic";
214 smps123_reg: smps123 {
216 regulator-name = "smps123";
217 regulator-min-microvolt = < 850000>;
218 regulator-max-microvolt = <1250000>;
225 regulator-name = "smps45";
226 regulator-min-microvolt = < 850000>;
227 regulator-max-microvolt = <1250000>;
233 /* VDD_GPU - over VDD_SMPS6 */
234 regulator-name = "smps6";
235 regulator-min-microvolt = <850000>;
236 regulator-max-microvolt = <1250000>;
243 regulator-name = "smps7";
244 regulator-min-microvolt = <850000>;
245 regulator-max-microvolt = <1150000>;
252 regulator-name = "smps8";
253 regulator-min-microvolt = < 850000>;
254 regulator-max-microvolt = <1250000>;
261 regulator-name = "smps9";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
269 /* LDO1_OUT --> SDIO */
270 regulator-name = "ldo1";
271 regulator-min-microvolt = <1800000>;
272 regulator-max-microvolt = <3300000>;
279 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
280 regulator-name = "ldo2";
281 regulator-min-microvolt = <3300000>;
282 regulator-max-microvolt = <3300000>;
289 regulator-name = "ldo3";
290 regulator-min-microvolt = <1800000>;
291 regulator-max-microvolt = <1800000>;
298 regulator-name = "ldo9";
299 regulator-min-microvolt = <1050000>;
300 regulator-max-microvolt = <1050000>;
303 regulator-allow-bypass;
308 regulator-name = "ldoln";
309 regulator-min-microvolt = <1800000>;
310 regulator-max-microvolt = <1800000>;
316 /* VDDA_3V_USB: VDDA_USBHS33 */
317 regulator-name = "ldousb";
318 regulator-min-microvolt = <3300000>;
319 regulator-max-microvolt = <3300000>;
323 /* REGEN1 is unused */
326 /* Needed for PMIC internal resources */
327 regulator-name = "regen2";
332 /* REGEN3 is unused */
336 regulator-name = "sysen1";
343 regulator-name = "sysen2";
352 compatible = "ti,pcf8575", "nxp,pcf8575";
356 interrupt-parent = <&gpio6>;
357 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
362 pcf_gpio_21: gpio@21 {
363 compatible = "ti,pcf8575", "nxp,pcf8575";
365 lines-initial-states = <0x1408>;
368 interrupt-parent = <&gpio6>;
369 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
374 tlv320aic3106: tlv320aic3106@19 {
375 #sound-dai-cells = <0>;
376 compatible = "ti,tlv320aic3106";
378 adc-settle-ms = <40>;
379 ai3x-micbias-vg = <1>; /* 2.0V */
383 AVDD-supply = <&evm_3v3_sw>;
384 IOVDD-supply = <&evm_3v3_sw>;
385 DRVDD-supply = <&evm_3v3_sw>;
386 DVDD-supply = <&aic_dvdd>;
392 clock-frequency = <400000>;
395 compatible = "ti,pcf8575", "nxp,pcf8575";
400 /* vin6_sel_s0: high: VIN6, low: audio */
402 gpios = <1 GPIO_ACTIVE_HIGH>;
404 line-name = "vin6_sel_s0";
411 clock-frequency = <400000>;
424 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
425 <&dra7_pmx_core 0x3e0>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&mmc1_pins_default>;
440 vmmc-supply = <&evm_3v3_sd>;
441 vmmc_aux-supply = <&ldo1_reg>;
444 * SDCD signal is not being used here - using the fact that GPIO mode
445 * is always hardwired.
447 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&mmc2_pins_default>;
454 vmmc-supply = <&evm_3v3_sw>;
459 cpu0-supply = <&smps123_reg>;
465 spi-max-frequency = <76800000>;
467 compatible = "s25fl256s1";
468 spi-max-frequency = <76800000>;
470 spi-tx-bus-width = <1>;
471 spi-rx-bus-width = <4>;
472 #address-cells = <1>;
475 /* MTD partition table.
476 * The ROM checks the first four physical blocks
477 * for a valid file to boot and the flash here is
482 reg = <0x00000000 0x000010000>;
485 label = "QSPI.SPL.backup1";
486 reg = <0x00010000 0x00010000>;
489 label = "QSPI.SPL.backup2";
490 reg = <0x00020000 0x00010000>;
493 label = "QSPI.SPL.backup3";
494 reg = <0x00030000 0x00010000>;
497 label = "QSPI.u-boot";
498 reg = <0x00040000 0x00100000>;
501 label = "QSPI.u-boot-spl-os";
502 reg = <0x00140000 0x00080000>;
505 label = "QSPI.u-boot-env";
506 reg = <0x001c0000 0x00010000>;
509 label = "QSPI.u-boot-env.backup1";
510 reg = <0x001d0000 0x0010000>;
513 label = "QSPI.kernel";
514 reg = <0x001e0000 0x0800000>;
517 label = "QSPI.file-system";
518 reg = <0x009e0000 0x01620000>;
524 extcon = <&extcon_usb1>;
528 extcon = <&extcon_usb2>;
533 extcon = <&extcon_usb1>;
546 * For the existing IOdelay configuration via U-Boot we don't
547 * support NAND on dra7-evm. Keep it disabled. Enabling it
548 * requires a different configuration by U-Boot.
551 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
553 compatible = "ti,omap2-nand";
554 reg = <0 0 4>; /* device IO registers */
555 interrupt-parent = <&gpmc>;
556 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
557 <1 IRQ_TYPE_NONE>; /* termcount */
558 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
559 ti,nand-ecc-opt = "bch8";
561 nand-bus-width = <16>;
562 gpmc,device-width = <2>;
563 gpmc,sync-clk-ps = <0>;
565 gpmc,cs-rd-off-ns = <80>;
566 gpmc,cs-wr-off-ns = <80>;
567 gpmc,adv-on-ns = <0>;
568 gpmc,adv-rd-off-ns = <60>;
569 gpmc,adv-wr-off-ns = <60>;
570 gpmc,we-on-ns = <10>;
571 gpmc,we-off-ns = <50>;
573 gpmc,oe-off-ns = <40>;
574 gpmc,access-ns = <40>;
575 gpmc,wr-access-ns = <80>;
576 gpmc,rd-cycle-ns = <80>;
577 gpmc,wr-cycle-ns = <80>;
578 gpmc,bus-turnaround-ns = <0>;
579 gpmc,cycle2cycle-delay-ns = <0>;
580 gpmc,clk-activation-ns = <0>;
581 gpmc,wr-data-mux-bus-ns = <0>;
582 /* MTD partition table */
583 /* All SPL-* partitions are sized to minimal length
584 * which can be independently programmable. For
585 * NAND flash this is equal to size of erase-block */
586 #address-cells = <1>;
590 reg = <0x00000000 0x000020000>;
593 label = "NAND.SPL.backup1";
594 reg = <0x00020000 0x00020000>;
597 label = "NAND.SPL.backup2";
598 reg = <0x00040000 0x00020000>;
601 label = "NAND.SPL.backup3";
602 reg = <0x00060000 0x00020000>;
605 label = "NAND.u-boot-spl-os";
606 reg = <0x00080000 0x00040000>;
609 label = "NAND.u-boot";
610 reg = <0x000c0000 0x00100000>;
613 label = "NAND.u-boot-env";
614 reg = <0x001c0000 0x00020000>;
617 label = "NAND.u-boot-env.backup1";
618 reg = <0x001e0000 0x00020000>;
621 label = "NAND.kernel";
622 reg = <0x00200000 0x00800000>;
625 label = "NAND.file-system";
626 reg = <0x00a00000 0x0f600000>;
632 phy-supply = <&ldousb_reg>;
636 phy-supply = <&ldousb_reg>;
650 phy_id = <&davinci_mdio>, <2>;
652 dual_emac_res_vlan = <1>;
656 phy_id = <&davinci_mdio>, <3>;
658 dual_emac_res_vlan = <2>;
663 pinctrl-names = "default", "sleep", "active";
664 pinctrl-0 = <&dcan1_pins_sleep>;
665 pinctrl-1 = <&dcan1_pins_sleep>;
666 pinctrl-2 = <&dcan1_pins_default>;
670 assigned-clocks = <&abe_dpll_sys_clk_mux>,
675 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
676 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
681 bws = <DRA7_ATL_WS_MCASP2_FSX>;
682 aws = <DRA7_ATL_WS_MCASP3_FSX>;
687 #sound-dai-cells = <0>;
689 assigned-clocks = <&mcasp3_ahclkx_mux>;
690 assigned-clock-parents = <&atl_clkin2_ck>;
694 op-mode = <0>; /* MCASP_IIS_MODE */
697 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
706 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
709 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
716 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
719 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {