arch/arm/boot/dts/dra7-evm.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5 /dts-v1/;
   6
   7 #include "dra74x.dtsi"
   8 #include "dra7-evm-common.dtsi"
   9 #include "dra74x-mmc-iodelay.dtsi"
  10
  11 / {
  12         model = "TI DRA742";
  13         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  14
  15         memory@0 {
  16                 device_type = "memory";
  17                 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
  18         };
  19
  20         evm_12v0: fixedregulator-evm_12v0 {
  21                 /* main supply */
  22                 compatible = "regulator-fixed";
  23                 regulator-name = "evm_12v0";
  24                 regulator-min-microvolt = <12000000>;
  25                 regulator-max-microvolt = <12000000>;
  26                 regulator-always-on;
  27                 regulator-boot-on;
  28         };
  29
  30         evm_1v8_sw: fixedregulator-evm_1v8 {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "evm_1v8";
  33                 vin-supply = <&smps9_reg>;
  34                 regulator-min-microvolt = <1800000>;
  35                 regulator-max-microvolt = <1800000>;
  36         };
  37
  38         reserved-memory {
  39                 #address-cells = <2>;
  40                 #size-cells = <2>;
  41                 ranges;
  42
  43                 ipu2_memory_region: ipu2-memory@95800000 {
  44                         compatible = "shared-dma-pool";
  45                         reg = <0x0 0x95800000 0x0 0x3800000>;
  46                         reusable;
  47                         status = "okay";
  48                 };
  49
  50                 dsp1_memory_region: dsp1-memory@99000000 {
  51                         compatible = "shared-dma-pool";
  52                         reg = <0x0 0x99000000 0x0 0x4000000>;
  53                         reusable;
  54                         status = "okay";
  55                 };
  56
  57                 ipu1_memory_region: ipu1-memory@9d000000 {
  58                         compatible = "shared-dma-pool";
  59                         reg = <0x0 0x9d000000 0x0 0x2000000>;
  60                         reusable;
  61                         status = "okay";
  62                 };
  63
  64                 dsp2_memory_region: dsp2-memory@9f000000 {
  65                         compatible = "shared-dma-pool";
  66                         reg = <0x0 0x9f000000 0x0 0x800000>;
  67                         reusable;
  68                         status = "okay";
  69                 };
  70         };
  71
  72         evm_3v3_sd: fixedregulator-sd {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "evm_3v3_sd";
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 enable-active-high;
  78                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  79         };
  80
  81         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  82                 compatible = "regulator-fixed";
  83                 regulator-name = "evm_3v3_sw";
  84                 vin-supply = <&sysen1>;
  85                 regulator-min-microvolt = <3300000>;
  86                 regulator-max-microvolt = <3300000>;
  87         };
  88
  89         aic_dvdd: fixedregulator-aic_dvdd {
  90                 /* TPS77018DBVT */
  91                 compatible = "regulator-fixed";
  92                 regulator-name = "aic_dvdd";
  93                 vin-supply = <&evm_3v3_sw>;
  94                 regulator-min-microvolt = <1800000>;
  95                 regulator-max-microvolt = <1800000>;
  96         };
  97
  98         vsys_3v3: fixedregulator-vsys3v3 {
  99                 /* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
 100                 compatible = "regulator-fixed";
 101                 regulator-name = "vsys_3v3";
 102                 regulator-min-microvolt = <3300000>;
 103                 regulator-max-microvolt = <3300000>;
 104                 vin-supply = <&evm_12v0>;
 105                 regulator-always-on;
 106                 regulator-boot-on;
 107         };
 108
 109         evm_5v0: fixedregulator-evm_5v0 {
 110                 /* Output of Cntlr B of TPS43351-Q1 on dra7-evm */
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "evm_5v0";
 113                 regulator-min-microvolt = <5000000>;
 114                 regulator-max-microvolt = <5000000>;
 115                 vin-supply = <&evm_12v0>;
 116                 regulator-always-on;
 117                 regulator-boot-on;
 118         };
 119
 120         evm_3v6: fixedregulator-evm_3v6 {
 121                 compatible = "regulator-fixed";
 122                 regulator-name = "evm_3v6";
 123                 regulator-min-microvolt = <3600000>;
 124                 regulator-max-microvolt = <3600000>;
 125                 vin-supply = <&evm_5v0>;
 126                 regulator-always-on;
 127                 regulator-boot-on;
 128         };
 129
 130         vmmcwl_fixed: fixedregulator-mmcwl {
 131                 compatible = "regulator-fixed";
 132                 regulator-name = "vmmcwl_fixed";
 133                 regulator-min-microvolt = <1800000>;
 134                 regulator-max-microvolt = <1800000>;
 135                 gpio = <&gpio5 8 0>;
 136                 startup-delay-us = <70000>;
 137                 enable-active-high;
 138         };
 139
 140         vtt_fixed: fixedregulator-vtt {
 141                 compatible = "regulator-fixed";
 142                 regulator-name = "vtt_fixed";
 143                 regulator-min-microvolt = <1350000>;
 144                 regulator-max-microvolt = <1350000>;
 145                 regulator-always-on;
 146                 regulator-boot-on;
 147                 enable-active-high;
 148                 vin-supply = <&sysen2>;
 149                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 150         };
 151
 152 };
 153
 154 &dra7_pmx_core {
 155         dcan1_pins_default: dcan1_pins_default {
 156                 pinctrl-single,pins = <
 157                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 158                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 159                 >;
 160         };
 161
 162         dcan1_pins_sleep: dcan1_pins_sleep {
 163                 pinctrl-single,pins = <
 164                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 165                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 166                 >;
 167         };
 168 };
 169
 170 &i2c1 {
 171         status = "okay";
 172         clock-frequency = <400000>;
 173
 174         tps659038: tps659038@58 {
 175                 compatible = "ti,tps659038";
 176                 reg = <0x58>;
 177                 ti,palmas-override-powerhold;
 178                 ti,system-power-controller;
 179
 180                 tps659038_pmic {
 181                         compatible = "ti,tps659038-pmic";
 182
 183                         regulators {
 184                                 smps123_reg: smps123 {
 185                                         /* VDD_MPU */
 186                                         regulator-name = "smps123";
 187                                         regulator-min-microvolt = < 850000>;
 188                                         regulator-max-microvolt = <1250000>;
 189                                         regulator-always-on;
 190                                         regulator-boot-on;
 191                                 };
 192
 193                                 smps45_reg: smps45 {
 194                                         /* VDD_DSPEVE */
 195                                         regulator-name = "smps45";
 196                                         regulator-min-microvolt = < 850000>;
 197                                         regulator-max-microvolt = <1250000>;
 198                                         regulator-always-on;
 199                                         regulator-boot-on;
 200                                 };
 201
 202                                 smps6_reg: smps6 {
 203                                         /* VDD_GPU - over VDD_SMPS6 */
 204                                         regulator-name = "smps6";
 205                                         regulator-min-microvolt = <850000>;
 206                                         regulator-max-microvolt = <1250000>;
 207                                         regulator-always-on;
 208                                         regulator-boot-on;
 209                                 };
 210
 211                                 smps7_reg: smps7 {
 212                                         /* CORE_VDD */
 213                                         regulator-name = "smps7";
 214                                         regulator-min-microvolt = <850000>;
 215                                         regulator-max-microvolt = <1150000>;
 216                                         regulator-always-on;
 217                                         regulator-boot-on;
 218                                 };
 219
 220                                 smps8_reg: smps8 {
 221                                         /* VDD_IVAHD */
 222                                         regulator-name = "smps8";
 223                                         regulator-min-microvolt = < 850000>;
 224                                         regulator-max-microvolt = <1250000>;
 225                                         regulator-always-on;
 226                                         regulator-boot-on;
 227                                 };
 228
 229                                 smps9_reg: smps9 {
 230                                         /* VDDS1V8 */
 231                                         regulator-name = "smps9";
 232                                         regulator-min-microvolt = <1800000>;
 233                                         regulator-max-microvolt = <1800000>;
 234                                         regulator-always-on;
 235                                         regulator-boot-on;
 236                                 };
 237
 238                                 ldo1_reg: ldo1 {
 239                                         /* LDO1_OUT --> SDIO  */
 240                                         regulator-name = "ldo1";
 241                                         regulator-min-microvolt = <1800000>;
 242                                         regulator-max-microvolt = <3300000>;
 243                                         regulator-always-on;
 244                                         regulator-boot-on;
 245                                 };
 246
 247                                 ldo2_reg: ldo2 {
 248                                         /* VDD_RTCIO */
 249                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 250                                         regulator-name = "ldo2";
 251                                         regulator-min-microvolt = <3300000>;
 252                                         regulator-max-microvolt = <3300000>;
 253                                         regulator-always-on;
 254                                         regulator-boot-on;
 255                                 };
 256
 257                                 ldo3_reg: ldo3 {
 258                                         /* VDDA_1V8_PHY */
 259                                         regulator-name = "ldo3";
 260                                         regulator-min-microvolt = <1800000>;
 261                                         regulator-max-microvolt = <1800000>;
 262                                         regulator-always-on;
 263                                         regulator-boot-on;
 264                                 };
 265
 266                                 ldo9_reg: ldo9 {
 267                                         /* VDD_RTC */
 268                                         regulator-name = "ldo9";
 269                                         regulator-min-microvolt = <1050000>;
 270                                         regulator-max-microvolt = <1050000>;
 271                                         regulator-always-on;
 272                                         regulator-boot-on;
 273                                         regulator-allow-bypass;
 274                                 };
 275
 276                                 ldoln_reg: ldoln {
 277                                         /* VDDA_1V8_PLL */
 278                                         regulator-name = "ldoln";
 279                                         regulator-min-microvolt = <1800000>;
 280                                         regulator-max-microvolt = <1800000>;
 281                                         regulator-always-on;
 282                                         regulator-boot-on;
 283                                 };
 284
 285                                 ldousb_reg: ldousb {
 286                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 287                                         regulator-name = "ldousb";
 288                                         regulator-min-microvolt = <3300000>;
 289                                         regulator-max-microvolt = <3300000>;
 290                                         regulator-boot-on;
 291                                 };
 292
 293                                 /* REGEN1 is unused */
 294
 295                                 regen2: regen2 {
 296                                         /* Needed for PMIC internal resources */
 297                                         regulator-name = "regen2";
 298                                         regulator-boot-on;
 299                                         regulator-always-on;
 300                                 };
 301
 302                                 /* REGEN3 is unused */
 303
 304                                 sysen1: sysen1 {
 305                                         /* PMIC_REGEN_3V3 */
 306                                         regulator-name = "sysen1";
 307                                         regulator-boot-on;
 308                                         regulator-always-on;
 309                                 };
 310
 311                                 sysen2: sysen2 {
 312                                         /* PMIC_REGEN_DDR */
 313                                         regulator-name = "sysen2";
 314                                         regulator-boot-on;
 315                                         regulator-always-on;
 316                                 };
 317                         };
 318                 };
 319         };
 320
 321         pcf_lcd: gpio@20 {
 322                 compatible = "ti,pcf8575", "nxp,pcf8575";
 323                 reg = <0x20>;
 324                 gpio-controller;
 325                 #gpio-cells = <2>;
 326                 interrupt-parent = <&gpio6>;
 327                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 328                 interrupt-controller;
 329                 #interrupt-cells = <2>;
 330         };
 331
 332         pcf_gpio_21: gpio@21 {
 333                 compatible = "ti,pcf8575", "nxp,pcf8575";
 334                 reg = <0x21>;
 335                 lines-initial-states = <0x1408>;
 336                 gpio-controller;
 337                 #gpio-cells = <2>;
 338                 interrupt-parent = <&gpio6>;
 339                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 340                 interrupt-controller;
 341                 #interrupt-cells = <2>;
 342         };
 343
 344         tlv320aic3106: tlv320aic3106@19 {
 345                 #sound-dai-cells = <0>;
 346                 compatible = "ti,tlv320aic3106";
 347                 reg = <0x19>;
 348                 adc-settle-ms = <40>;
 349                 ai3x-micbias-vg = <1>;          /* 2.0V */
 350                 status = "okay";
 351
 352                 /* Regulators */
 353                 AVDD-supply = <&evm_3v3_sw>;
 354                 IOVDD-supply = <&evm_3v3_sw>;
 355                 DRVDD-supply = <&evm_3v3_sw>;
 356                 DVDD-supply = <&aic_dvdd>;
 357         };
 358 };
 359
 360 &i2c2 {
 361         status = "okay";
 362         clock-frequency = <400000>;
 363
 364         pcf_hdmi: gpio@26 {
 365                 compatible = "ti,pcf8575", "nxp,pcf8575";
 366                 reg = <0x26>;
 367                 gpio-controller;
 368                 #gpio-cells = <2>;
 369                 p1 {
 370                         /* vin6_sel_s0: high: VIN6, low: audio */
 371                         gpio-hog;
 372                         gpios = <1 GPIO_ACTIVE_HIGH>;
 373                         output-low;
 374                         line-name = "vin6_sel_s0";
 375                 };
 376         };
 377 };
 378
 379 &mmc1 {
 380         status = "okay";
 381         vmmc-supply = <&evm_3v3_sd>;
 382         vqmmc-supply = <&ldo1_reg>;
 383         bus-width = <4>;
 384         /*
 385          * SDCD signal is not being used here - using the fact that GPIO mode
 386          * is always hardwired.
 387          */
 388         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 389         pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104";
 390         pinctrl-0 = <&mmc1_pins_default>;
 391         pinctrl-1 = <&mmc1_pins_hs>;
 392         pinctrl-2 = <&mmc1_pins_sdr12>;
 393         pinctrl-3 = <&mmc1_pins_sdr25>;
 394         pinctrl-4 = <&mmc1_pins_sdr50>;
 395         pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>;
 396         pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>;
 397         pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
 398         pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
 399 };
 400
 401 &mmc2 {
 402         status = "okay";
 403         vmmc-supply = <&evm_1v8_sw>;
 404         vqmmc-supply = <&evm_1v8_sw>;
 405         bus-width = <8>;
 406         non-removable;
 407         pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
 408         pinctrl-0 = <&mmc2_pins_default>;
 409         pinctrl-1 = <&mmc2_pins_hs>;
 410         pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>;
 411         pinctrl-3 = <&mmc2_pins_ddr_rev20>;
 412         pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>;
 413         pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
 414 };
 415
 416 &mmc4 {
 417         status = "okay";
 418         vmmc-supply = <&evm_3v6>;
 419         vqmmc-supply = <&vmmcwl_fixed>;
 420         pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11", "sdr25";
 421         pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_rev11_conf>;
 422         pinctrl-1 = <&mmc4_pins_default &mmc4_iodelay_ds_rev20_conf>;
 423         pinctrl-2 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
 424         pinctrl-3 = <&mmc4_pins_hs &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
 425         pinctrl-4 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
 426         pinctrl-5 = <&mmc4_pins_sdr12 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
 427         pinctrl-6 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev11_conf>;
 428         pinctrl-7 = <&mmc4_pins_sdr25 &mmc4_iodelay_sdr12_hs_sdr25_rev20_conf>;
 429 };
 430
 431 &cpu0 {
 432         vdd-supply = <&smps123_reg>;
 433 };
 434
 435 &elm {
 436         status = "okay";
 437 };
 438
 439 &gpmc {
 440         /*
 441         * For the existing IOdelay configuration via U-Boot we don't
 442         * support NAND on dra7-evm. Keep it disabled. Enabling it
 443         * requires a different configuration by U-Boot.
 444         */
 445         status = "disabled";
 446         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 447         nand@0,0 {
 448                 compatible = "ti,omap2-nand";
 449                 reg = <0 0 4>;          /* device IO registers */
 450                 interrupt-parent = <&gpmc>;
 451                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 452                              <1 IRQ_TYPE_NONE>; /* termcount */
 453                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 454                 ti,nand-xfer-type = "prefetch-dma";
 455                 ti,nand-ecc-opt = "bch8";
 456                 ti,elm-id = <&elm>;
 457                 nand-bus-width = <16>;
 458                 gpmc,device-width = <2>;
 459                 gpmc,sync-clk-ps = <0>;
 460                 gpmc,cs-on-ns = <0>;
 461                 gpmc,cs-rd-off-ns = <80>;
 462                 gpmc,cs-wr-off-ns = <80>;
 463                 gpmc,adv-on-ns = <0>;
 464                 gpmc,adv-rd-off-ns = <60>;
 465                 gpmc,adv-wr-off-ns = <60>;
 466                 gpmc,we-on-ns = <10>;
 467                 gpmc,we-off-ns = <50>;
 468                 gpmc,oe-on-ns = <4>;
 469                 gpmc,oe-off-ns = <40>;
 470                 gpmc,access-ns = <40>;
 471                 gpmc,wr-access-ns = <80>;
 472                 gpmc,rd-cycle-ns = <80>;
 473                 gpmc,wr-cycle-ns = <80>;
 474                 gpmc,bus-turnaround-ns = <0>;
 475                 gpmc,cycle2cycle-delay-ns = <0>;
 476                 gpmc,clk-activation-ns = <0>;
 477                 gpmc,wr-data-mux-bus-ns = <0>;
 478                 /* MTD partition table */
 479                 /* All SPL-* partitions are sized to minimal length
 480                  * which can be independently programmable. For
 481                  * NAND flash this is equal to size of erase-block */
 482                 #address-cells = <1>;
 483                 #size-cells = <1>;
 484                 partition@0 {
 485                         label = "NAND.SPL";
 486                         reg = <0x00000000 0x000020000>;
 487                 };
 488                 partition@1 {
 489                         label = "NAND.SPL.backup1";
 490                         reg = <0x00020000 0x00020000>;
 491                 };
 492                 partition@2 {
 493                         label = "NAND.SPL.backup2";
 494                         reg = <0x00040000 0x00020000>;
 495                 };
 496                 partition@3 {
 497                         label = "NAND.SPL.backup3";
 498                         reg = <0x00060000 0x00020000>;
 499                 };
 500                 partition@4 {
 501                         label = "NAND.u-boot-spl-os";
 502                         reg = <0x00080000 0x00040000>;
 503                 };
 504                 partition@5 {
 505                         label = "NAND.u-boot";
 506                         reg = <0x000c0000 0x00100000>;
 507                 };
 508                 partition@6 {
 509                         label = "NAND.u-boot-env";
 510                         reg = <0x001c0000 0x00020000>;
 511                 };
 512                 partition@7 {
 513                         label = "NAND.u-boot-env.backup1";
 514                         reg = <0x001e0000 0x00020000>;
 515                 };
 516                 partition@8 {
 517                         label = "NAND.kernel";
 518                         reg = <0x00200000 0x00800000>;
 519                 };
 520                 partition@9 {
 521                         label = "NAND.file-system";
 522                         reg = <0x00a00000 0x0f600000>;
 523                 };
 524         };
 525 };
 526
 527 &usb2_phy1 {
 528         phy-supply = <&ldousb_reg>;
 529 };
 530
 531 &usb2_phy2 {
 532         phy-supply = <&ldousb_reg>;
 533 };
 534
 535 &gpio7_target {
 536         ti,no-reset-on-init;
 537         ti,no-idle-on-init;
 538 };
 539
 540 &mac_sw {
 541         status = "okay";
 542 };
 543
 544 &cpsw_port1 {
 545         phy-handle = <&ethphy0>;
 546         phy-mode = "rgmii";
 547         ti,dual-emac-pvid = <1>;
 548 };
 549
 550 &cpsw_port2 {
 551         phy-handle = <&ethphy1>;
 552         phy-mode = "rgmii";
 553         ti,dual-emac-pvid = <2>;
 554 };
 555
 556 &davinci_mdio_sw {
 557         ethphy0: ethernet-phy@2 {
 558                 reg = <2>;
 559         };
 560
 561         ethphy1: ethernet-phy@3 {
 562                 reg = <3>;
 563         };
 564 };
 565
 566 &dcan1 {
 567         status = "okay";
 568         pinctrl-names = "default", "sleep", "active";
 569         pinctrl-0 = <&dcan1_pins_sleep>;
 570         pinctrl-1 = <&dcan1_pins_sleep>;
 571         pinctrl-2 = <&dcan1_pins_default>;
 572 };
 573
 574 &ipu2 {
 575         status = "okay";
 576         memory-region = <&ipu2_memory_region>;
 577 };
 578
 579 &ipu1 {
 580         status = "okay";
 581         memory-region = <&ipu1_memory_region>;
 582 };
 583
 584 &dsp1 {
 585         status = "okay";
 586         memory-region = <&dsp1_memory_region>;
 587 };
 588
 589 &dsp2 {
 590         status = "okay";
 591         memory-region = <&dsp2_memory_region>;
 592 };