1 /include/ "skeleton.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
6 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
9 compatible = "marvell,dove";
10 model = "Marvell Armada 88AP510 SoC";
11 interrupt-parent = <&intc>;
24 compatible = "marvell,pj4a", "marvell,sheeva-v7";
26 next-level-cache = <&l2>;
32 compatible = "marvell,tauros2-cache";
33 marvell,tauros2-cache-features = <0>;
37 compatible = "marvell,dove-gpu-subsystem";
43 compatible = "i2c-mux-pinctrl";
49 pinctrl-names = "i2c0", "i2c1", "i2c2";
50 pinctrl-0 = <&pmx_i2cmux_0>;
51 pinctrl-1 = <&pmx_i2cmux_1>;
52 pinctrl-2 = <&pmx_i2cmux_2>;
65 /* Requires pmx_i2c1 on i2c controller node */
73 /* Requires pmx_i2c2 on i2c controller node */
79 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
82 controller = <&mbusc>;
83 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
84 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
86 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
87 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
88 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
89 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
90 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
93 compatible = "marvell,dove-pcie";
100 bus-range = <0x00 0xff>;
102 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
103 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
104 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
105 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
106 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
107 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
112 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
113 reg = <0x0800 0 0 0 0>;
114 clocks = <&gate_clk 4>;
115 marvell,pcie-port = <0>;
117 #address-cells = <3>;
119 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
120 0x81000000 0 0 0x81000000 0x1 0 1 0>;
121 bus-range = <0x00 0xff>;
123 #interrupt-cells = <1>;
124 interrupt-map-mask = <0 0 0 0>;
125 interrupt-map = <0 0 0 0 &intc 16>;
131 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
132 reg = <0x1000 0 0 0 0>;
133 clocks = <&gate_clk 5>;
134 marvell,pcie-port = <1>;
136 #address-cells = <3>;
138 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
139 0x81000000 0 0 0x81000000 0x2 0 1 0>;
140 bus-range = <0x00 0xff>;
142 #interrupt-cells = <1>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &intc 18>;
149 compatible = "simple-bus";
150 #address-cells = <1>;
152 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
153 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
154 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
155 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
157 spi0: spi-ctrl@10600 {
158 compatible = "marvell,orion-spi";
159 #address-cells = <1>;
163 reg = <0x10600 0x28>;
164 clocks = <&core_clk 0>;
165 pinctrl-0 = <&pmx_spi0>;
166 pinctrl-names = "default";
170 i2c: i2c-ctrl@11000 {
171 compatible = "marvell,mv64xxx-i2c";
172 reg = <0x11000 0x20>;
173 #address-cells = <1>;
176 clock-frequency = <400000>;
178 clocks = <&core_clk 0>;
182 uart0: serial@12000 {
183 compatible = "ns16550a";
184 reg = <0x12000 0x100>;
187 clocks = <&core_clk 0>;
191 uart1: serial@12100 {
192 compatible = "ns16550a";
193 reg = <0x12100 0x100>;
196 clocks = <&core_clk 0>;
197 pinctrl-0 = <&pmx_uart1>;
198 pinctrl-names = "default";
202 uart2: serial@12200 {
203 compatible = "ns16550a";
204 reg = <0x12200 0x100>;
207 clocks = <&core_clk 0>;
211 uart3: serial@12300 {
212 compatible = "ns16550a";
213 reg = <0x12300 0x100>;
216 clocks = <&core_clk 0>;
220 spi1: spi-ctrl@14600 {
221 compatible = "marvell,orion-spi";
222 #address-cells = <1>;
226 reg = <0x14600 0x28>;
227 clocks = <&core_clk 0>;
231 mbusc: mbus-ctrl@20000 {
232 compatible = "marvell,mbus-controller";
233 reg = <0x20000 0x80>, <0x800100 0x8>;
236 sysc: system-ctrl@20000 {
237 compatible = "marvell,orion-system-controller";
238 reg = <0x20000 0x110>;
241 bridge_intc: bridge-interrupt-ctrl@20110 {
242 compatible = "marvell,orion-bridge-intc";
243 interrupt-controller;
244 #interrupt-cells = <1>;
247 marvell,#interrupts = <5>;
250 intc: main-interrupt-ctrl@20200 {
251 compatible = "marvell,orion-intc";
252 interrupt-controller;
253 #interrupt-cells = <1>;
254 reg = <0x20200 0x10>, <0x20210 0x10>;
258 compatible = "marvell,orion-timer";
259 reg = <0x20300 0x20>;
260 interrupt-parent = <&bridge_intc>;
261 interrupts = <1>, <2>;
262 clocks = <&core_clk 0>;
266 compatible = "marvell,orion-wdt";
267 reg = <0x20300 0x28>, <0x20108 0x4>;
268 interrupt-parent = <&bridge_intc>;
270 clocks = <&core_clk 0>;
273 crypto: crypto-engine@30000 {
274 compatible = "marvell,dove-crypto";
275 reg = <0x30000 0x10000>;
278 clocks = <&gate_clk 15>;
279 marvell,crypto-srams = <&crypto_sram>;
280 marvell,crypto-sram-size = <0x800>;
284 ehci0: usb-host@50000 {
285 compatible = "marvell,orion-ehci";
286 reg = <0x50000 0x1000>;
288 clocks = <&gate_clk 0>;
292 ehci1: usb-host@51000 {
293 compatible = "marvell,orion-ehci";
294 reg = <0x51000 0x1000>;
296 clocks = <&gate_clk 1>;
300 xor0: dma-engine@60800 {
301 compatible = "marvell,orion-xor";
304 clocks = <&gate_clk 23>;
320 xor1: dma-engine@60900 {
321 compatible = "marvell,orion-xor";
324 clocks = <&gate_clk 24>;
340 sdio1: sdio-host@90000 {
341 compatible = "marvell,dove-sdhci";
342 reg = <0x90000 0x100>;
343 interrupts = <36>, <38>;
344 clocks = <&gate_clk 9>;
345 pinctrl-0 = <&pmx_sdio1>;
346 pinctrl-names = "default";
350 eth: ethernet-ctrl@72000 {
351 compatible = "marvell,orion-eth";
352 #address-cells = <1>;
354 reg = <0x72000 0x4000>;
355 clocks = <&gate_clk 2>;
356 marvell,tx-checksum-limit = <1600>;
360 compatible = "marvell,orion-eth-port";
363 /* overwrite MAC address in bootloader */
364 local-mac-address = [00 00 00 00 00 00];
365 phy-handle = <ðphy>;
369 mdio: mdio-bus@72004 {
370 compatible = "marvell,orion-mdio";
371 #address-cells = <1>;
373 reg = <0x72004 0x84>;
375 clocks = <&gate_clk 2>;
378 ethphy: ethernet-phy {
379 /* set phy address in board file */
383 sdio0: sdio-host@92000 {
384 compatible = "marvell,dove-sdhci";
385 reg = <0x92000 0x100>;
386 interrupts = <35>, <37>;
387 clocks = <&gate_clk 8>;
388 pinctrl-0 = <&pmx_sdio0>;
389 pinctrl-names = "default";
393 sata0: sata-host@a0000 {
394 compatible = "marvell,orion-sata";
395 reg = <0xa0000 0x2400>;
397 clocks = <&gate_clk 3>;
404 sata_phy0: sata-phy@a2000 {
405 compatible = "marvell,mvebu-sata-phy";
406 reg = <0xa2000 0x0334>;
407 clocks = <&gate_clk 3>;
408 clock-names = "sata";
413 audio0: audio-controller@b0000 {
414 compatible = "marvell,dove-audio";
415 reg = <0xb0000 0x2210>;
416 interrupts = <19>, <20>;
417 clocks = <&gate_clk 12>;
418 clock-names = "internal";
422 audio1: audio-controller@b4000 {
423 compatible = "marvell,dove-audio";
424 reg = <0xb4000 0x2210>;
425 interrupts = <21>, <22>;
426 clocks = <&gate_clk 13>;
427 clock-names = "internal";
431 pmu: power-management@d0000 {
432 compatible = "marvell,dove-pmu", "simple-bus";
433 reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
434 ranges = <0x00000000 0x000d0000 0x8000
435 0x00008000 0x000d8000 0x8000>;
437 interrupt-controller;
438 #address-cells = <1>;
440 #interrupt-cells = <1>;
444 vpu_domain: vpu-domain {
445 #power-domain-cells = <0>;
446 marvell,pmu_pwr_mask = <0x00000008>;
447 marvell,pmu_iso_mask = <0x00000001>;
451 gpu_domain: gpu-domain {
452 #power-domain-cells = <0>;
453 marvell,pmu_pwr_mask = <0x00000004>;
454 marvell,pmu_iso_mask = <0x00000002>;
459 thermal: thermal-diode@001c {
460 compatible = "marvell,dove-thermal";
461 reg = <0x001c 0x0c>, <0x005c 0x08>;
464 gate_clk: clock-gating-ctrl@0038 {
465 compatible = "marvell,dove-gating-clock";
467 clocks = <&core_clk 0>;
471 divider_clk: core-clock@0064 {
472 compatible = "marvell,dove-divider-clock";
477 pinctrl: pin-ctrl@0200 {
478 compatible = "marvell,dove-pinctrl";
481 clocks = <&gate_clk 22>;
483 pmx_gpio_0: pmx-gpio-0 {
484 marvell,pins = "mpp0";
485 marvell,function = "gpio";
488 pmx_gpio_1: pmx-gpio-1 {
489 marvell,pins = "mpp1";
490 marvell,function = "gpio";
493 pmx_gpio_2: pmx-gpio-2 {
494 marvell,pins = "mpp2";
495 marvell,function = "gpio";
498 pmx_gpio_3: pmx-gpio-3 {
499 marvell,pins = "mpp3";
500 marvell,function = "gpio";
503 pmx_gpio_4: pmx-gpio-4 {
504 marvell,pins = "mpp4";
505 marvell,function = "gpio";
508 pmx_gpio_5: pmx-gpio-5 {
509 marvell,pins = "mpp5";
510 marvell,function = "gpio";
513 pmx_gpio_6: pmx-gpio-6 {
514 marvell,pins = "mpp6";
515 marvell,function = "gpio";
518 pmx_gpio_7: pmx-gpio-7 {
519 marvell,pins = "mpp7";
520 marvell,function = "gpio";
523 pmx_gpio_8: pmx-gpio-8 {
524 marvell,pins = "mpp8";
525 marvell,function = "gpio";
528 pmx_gpio_9: pmx-gpio-9 {
529 marvell,pins = "mpp9";
530 marvell,function = "gpio";
533 pmx_pcie1_clkreq: pmx-pcie1-clkreq {
534 marvell,pins = "mpp9";
535 marvell,function = "pex1";
538 pmx_gpio_10: pmx-gpio-10 {
539 marvell,pins = "mpp10";
540 marvell,function = "gpio";
543 pmx_gpio_11: pmx-gpio-11 {
544 marvell,pins = "mpp11";
545 marvell,function = "gpio";
548 pmx_pcie0_clkreq: pmx-pcie0-clkreq {
549 marvell,pins = "mpp11";
550 marvell,function = "pex0";
553 pmx_gpio_12: pmx-gpio-12 {
554 marvell,pins = "mpp12";
555 marvell,function = "gpio";
558 pmx_gpio_13: pmx-gpio-13 {
559 marvell,pins = "mpp13";
560 marvell,function = "gpio";
563 pmx_audio1_extclk: pmx-audio1-extclk {
564 marvell,pins = "mpp13";
565 marvell,function = "audio1";
568 pmx_gpio_14: pmx-gpio-14 {
569 marvell,pins = "mpp14";
570 marvell,function = "gpio";
573 pmx_gpio_15: pmx-gpio-15 {
574 marvell,pins = "mpp15";
575 marvell,function = "gpio";
578 pmx_gpio_16: pmx-gpio-16 {
579 marvell,pins = "mpp16";
580 marvell,function = "gpio";
583 pmx_gpio_17: pmx-gpio-17 {
584 marvell,pins = "mpp17";
585 marvell,function = "gpio";
588 pmx_gpio_18: pmx-gpio-18 {
589 marvell,pins = "mpp18";
590 marvell,function = "gpio";
593 pmx_gpio_19: pmx-gpio-19 {
594 marvell,pins = "mpp19";
595 marvell,function = "gpio";
598 pmx_gpio_20: pmx-gpio-20 {
599 marvell,pins = "mpp20";
600 marvell,function = "gpio";
603 pmx_gpio_21: pmx-gpio-21 {
604 marvell,pins = "mpp21";
605 marvell,function = "gpio";
608 pmx_camera: pmx-camera {
609 marvell,pins = "mpp_camera";
610 marvell,function = "camera";
613 pmx_camera_gpio: pmx-camera-gpio {
614 marvell,pins = "mpp_camera";
615 marvell,function = "gpio";
618 pmx_sdio0: pmx-sdio0 {
619 marvell,pins = "mpp_sdio0";
620 marvell,function = "sdio0";
623 pmx_sdio0_gpio: pmx-sdio0-gpio {
624 marvell,pins = "mpp_sdio0";
625 marvell,function = "gpio";
628 pmx_sdio1: pmx-sdio1 {
629 marvell,pins = "mpp_sdio1";
630 marvell,function = "sdio1";
633 pmx_sdio1_gpio: pmx-sdio1-gpio {
634 marvell,pins = "mpp_sdio1";
635 marvell,function = "gpio";
638 pmx_audio1_gpio: pmx-audio1-gpio {
639 marvell,pins = "mpp_audio1";
640 marvell,function = "gpio";
643 pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
644 marvell,pins = "mpp_audio1";
645 marvell,function = "i2s1/spdifo";
649 marvell,pins = "mpp_spi0";
650 marvell,function = "spi0";
653 pmx_spi0_gpio: pmx-spi0-gpio {
654 marvell,pins = "mpp_spi0";
655 marvell,function = "gpio";
658 pmx_spi1_4_7: pmx-spi1-4-7 {
659 marvell,pins = "mpp4", "mpp5",
661 marvell,function = "spi1";
664 pmx_spi1_20_23: pmx-spi1-20-23 {
665 marvell,pins = "mpp20", "mpp21",
667 marvell,function = "spi1";
670 pmx_uart1: pmx-uart1 {
671 marvell,pins = "mpp_uart1";
672 marvell,function = "uart1";
675 pmx_uart1_gpio: pmx-uart1-gpio {
676 marvell,pins = "mpp_uart1";
677 marvell,function = "gpio";
681 marvell,pins = "mpp_nand";
682 marvell,function = "nand";
685 pmx_nand_gpo: pmx-nand-gpo {
686 marvell,pins = "mpp_nand";
687 marvell,function = "gpo";
691 marvell,pins = "mpp17", "mpp19";
692 marvell,function = "twsi";
696 marvell,pins = "mpp_audio1";
697 marvell,function = "twsi";
700 pmx_ssp_i2c2: pmx-ssp-i2c2 {
701 marvell,pins = "mpp_audio1";
702 marvell,function = "ssp/twsi";
705 pmx_i2cmux_0: pmx-i2cmux-0 {
706 marvell,pins = "twsi";
707 marvell,function = "twsi-opt1";
710 pmx_i2cmux_1: pmx-i2cmux-1 {
711 marvell,pins = "twsi";
712 marvell,function = "twsi-opt2";
715 pmx_i2cmux_2: pmx-i2cmux-2 {
716 marvell,pins = "twsi";
717 marvell,function = "twsi-opt3";
721 core_clk: core-clocks@0214 {
722 compatible = "marvell,dove-core-clock";
727 gpio0: gpio-ctrl@0400 {
728 compatible = "marvell,orion-gpio";
733 interrupt-controller;
734 #interrupt-cells = <2>;
735 interrupt-parent = <&intc>;
736 interrupts = <12>, <13>, <14>, <60>;
739 gpio1: gpio-ctrl@0420 {
740 compatible = "marvell,orion-gpio";
745 interrupt-controller;
746 #interrupt-cells = <2>;
747 interrupt-parent = <&intc>;
751 rtc: real-time-clock@8500 {
752 compatible = "marvell,orion-rtc";
758 gconf: global-config@e802c {
759 compatible = "marvell,dove-global-config",
761 reg = <0xe802c 0x14>;
764 gpio2: gpio-ctrl@e8400 {
765 compatible = "marvell,orion-gpio";
768 reg = <0xe8400 0x0c>;
772 lcd1: lcd-controller@810000 {
773 compatible = "marvell,dove-lcd";
774 reg = <0x810000 0x1000>;
779 lcd0: lcd-controller@820000 {
780 compatible = "marvell,dove-lcd";
781 reg = <0x820000 0x1000>;
786 crypto_sram: sa-sram@ffffe000 {
787 compatible = "mmio-sram";
788 reg = <0xffffe000 0x800>;
789 clocks = <&gate_clk 15>;
790 #address-cells = <1>;
795 clocks = <÷r_clk 1>;
796 clock-names = "core";
797 compatible = "vivante,gc";
799 power-domains = <&gpu_domain>;
800 reg = <0x840000 0x4000>;