1 /include/ "skeleton.dtsi"
3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
6 compatible = "marvell,dove";
7 model = "Marvell Armada 88AP510 SoC";
20 compatible = "marvell,pj4a", "marvell,sheeva-v7";
22 next-level-cache = <&l2>;
28 compatible = "marvell,tauros2-cache";
29 marvell,tauros2-cache-features = <0>;
33 compatible = "simple-bus";
36 interrupt-parent = <&intc>;
38 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
39 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
40 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
41 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
42 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
43 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
44 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
45 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
48 compatible = "marvell,orion-timer";
50 interrupt-parent = <&bridge_intc>;
51 interrupts = <1>, <2>;
52 clocks = <&core_clk 0>;
55 intc: main-interrupt-ctrl@20200 {
56 compatible = "marvell,orion-intc";
58 #interrupt-cells = <1>;
59 reg = <0x20200 0x10>, <0x20210 0x10>;
62 bridge_intc: bridge-interrupt-ctrl@20110 {
63 compatible = "marvell,orion-bridge-intc";
65 #interrupt-cells = <1>;
68 marvell,#interrupts = <5>;
71 core_clk: core-clocks@d0214 {
72 compatible = "marvell,dove-core-clock";
77 gate_clk: clock-gating-ctrl@d0038 {
78 compatible = "marvell,dove-gating-clock";
80 clocks = <&core_clk 0>;
84 thermal: thermal-diode@d001c {
85 compatible = "marvell,dove-thermal";
86 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
90 compatible = "ns16550a";
91 reg = <0x12000 0x100>;
94 clocks = <&core_clk 0>;
99 compatible = "ns16550a";
100 reg = <0x12100 0x100>;
103 clocks = <&core_clk 0>;
104 pinctrl-0 = <&pmx_uart1>;
105 pinctrl-names = "default";
109 uart2: serial@12200 {
110 compatible = "ns16550a";
111 reg = <0x12000 0x100>;
114 clocks = <&core_clk 0>;
118 uart3: serial@12300 {
119 compatible = "ns16550a";
120 reg = <0x12100 0x100>;
123 clocks = <&core_clk 0>;
127 gpio0: gpio-ctrl@d0400 {
128 compatible = "marvell,orion-gpio";
131 reg = <0xd0400 0x20>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 interrupts = <12>, <13>, <14>, <60>;
138 gpio1: gpio-ctrl@d0420 {
139 compatible = "marvell,orion-gpio";
142 reg = <0xd0420 0x20>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
149 gpio2: gpio-ctrl@e8400 {
150 compatible = "marvell,orion-gpio";
153 reg = <0xe8400 0x0c>;
157 pinctrl: pin-ctrl@d0200 {
158 compatible = "marvell,dove-pinctrl";
159 reg = <0xd0200 0x10>;
160 clocks = <&gate_clk 22>;
162 pmx_gpio_0: pmx-gpio-0 {
163 marvell,pins = "mpp0";
164 marvell,function = "gpio";
167 pmx_gpio_1: pmx-gpio-1 {
168 marvell,pins = "mpp1";
169 marvell,function = "gpio";
172 pmx_gpio_2: pmx-gpio-2 {
173 marvell,pins = "mpp2";
174 marvell,function = "gpio";
177 pmx_gpio_3: pmx-gpio-3 {
178 marvell,pins = "mpp3";
179 marvell,function = "gpio";
182 pmx_gpio_4: pmx-gpio-4 {
183 marvell,pins = "mpp4";
184 marvell,function = "gpio";
187 pmx_gpio_5: pmx-gpio-5 {
188 marvell,pins = "mpp5";
189 marvell,function = "gpio";
192 pmx_gpio_6: pmx-gpio-6 {
193 marvell,pins = "mpp6";
194 marvell,function = "gpio";
197 pmx_gpio_7: pmx-gpio-7 {
198 marvell,pins = "mpp7";
199 marvell,function = "gpio";
202 pmx_gpio_8: pmx-gpio-8 {
203 marvell,pins = "mpp8";
204 marvell,function = "gpio";
207 pmx_gpio_9: pmx-gpio-9 {
208 marvell,pins = "mpp9";
209 marvell,function = "gpio";
212 pmx_gpio_10: pmx-gpio-10 {
213 marvell,pins = "mpp10";
214 marvell,function = "gpio";
217 pmx_gpio_11: pmx-gpio-11 {
218 marvell,pins = "mpp11";
219 marvell,function = "gpio";
222 pmx_gpio_12: pmx-gpio-12 {
223 marvell,pins = "mpp12";
224 marvell,function = "gpio";
227 pmx_gpio_13: pmx-gpio-13 {
228 marvell,pins = "mpp13";
229 marvell,function = "gpio";
232 pmx_gpio_14: pmx-gpio-14 {
233 marvell,pins = "mpp14";
234 marvell,function = "gpio";
237 pmx_gpio_15: pmx-gpio-15 {
238 marvell,pins = "mpp15";
239 marvell,function = "gpio";
242 pmx_gpio_16: pmx-gpio-16 {
243 marvell,pins = "mpp16";
244 marvell,function = "gpio";
247 pmx_gpio_17: pmx-gpio-17 {
248 marvell,pins = "mpp17";
249 marvell,function = "gpio";
252 pmx_gpio_18: pmx-gpio-18 {
253 marvell,pins = "mpp18";
254 marvell,function = "gpio";
257 pmx_gpio_19: pmx-gpio-19 {
258 marvell,pins = "mpp19";
259 marvell,function = "gpio";
262 pmx_gpio_20: pmx-gpio-20 {
263 marvell,pins = "mpp20";
264 marvell,function = "gpio";
267 pmx_gpio_21: pmx-gpio-21 {
268 marvell,pins = "mpp21";
269 marvell,function = "gpio";
272 pmx_camera: pmx-camera {
273 marvell,pins = "mpp_camera";
274 marvell,function = "camera";
277 pmx_camera_gpio: pmx-camera-gpio {
278 marvell,pins = "mpp_camera";
279 marvell,function = "gpio";
282 pmx_sdio0: pmx-sdio0 {
283 marvell,pins = "mpp_sdio0";
284 marvell,function = "sdio0";
287 pmx_sdio0_gpio: pmx-sdio0-gpio {
288 marvell,pins = "mpp_sdio0";
289 marvell,function = "gpio";
292 pmx_sdio1: pmx-sdio1 {
293 marvell,pins = "mpp_sdio1";
294 marvell,function = "sdio1";
297 pmx_sdio1_gpio: pmx-sdio1-gpio {
298 marvell,pins = "mpp_sdio1";
299 marvell,function = "gpio";
302 pmx_audio1_gpio: pmx-audio1-gpio {
303 marvell,pins = "mpp_audio1";
304 marvell,function = "gpio";
308 marvell,pins = "mpp_spi0";
309 marvell,function = "spi0";
312 pmx_spi0_gpio: pmx-spi0-gpio {
313 marvell,pins = "mpp_spi0";
314 marvell,function = "gpio";
317 pmx_uart1: pmx-uart1 {
318 marvell,pins = "mpp_uart1";
319 marvell,function = "uart1";
322 pmx_uart1_gpio: pmx-uart1-gpio {
323 marvell,pins = "mpp_uart1";
324 marvell,function = "gpio";
328 marvell,pins = "mpp_nand";
329 marvell,function = "nand";
332 pmx_nand_gpo: pmx-nand-gpo {
333 marvell,pins = "mpp_nand";
334 marvell,function = "gpo";
338 spi0: spi-ctrl@10600 {
339 compatible = "marvell,orion-spi";
340 #address-cells = <1>;
344 reg = <0x10600 0x28>;
345 clocks = <&core_clk 0>;
346 pinctrl-0 = <&pmx_spi0>;
347 pinctrl-names = "default";
351 spi1: spi-ctrl@14600 {
352 compatible = "marvell,orion-spi";
353 #address-cells = <1>;
357 reg = <0x14600 0x28>;
358 clocks = <&core_clk 0>;
362 i2c0: i2c-ctrl@11000 {
363 compatible = "marvell,mv64xxx-i2c";
364 reg = <0x11000 0x20>;
365 #address-cells = <1>;
368 clock-frequency = <400000>;
370 clocks = <&core_clk 0>;
374 ehci0: usb-host@50000 {
375 compatible = "marvell,orion-ehci";
376 reg = <0x50000 0x1000>;
378 clocks = <&gate_clk 0>;
382 ehci1: usb-host@51000 {
383 compatible = "marvell,orion-ehci";
384 reg = <0x51000 0x1000>;
386 clocks = <&gate_clk 1>;
390 sdio0: sdio-host@92000 {
391 compatible = "marvell,dove-sdhci";
392 reg = <0x92000 0x100>;
393 interrupts = <35>, <37>;
394 clocks = <&gate_clk 8>;
395 pinctrl-0 = <&pmx_sdio0>;
396 pinctrl-names = "default";
400 sdio1: sdio-host@90000 {
401 compatible = "marvell,dove-sdhci";
402 reg = <0x90000 0x100>;
403 interrupts = <36>, <38>;
404 clocks = <&gate_clk 9>;
405 pinctrl-0 = <&pmx_sdio1>;
406 pinctrl-names = "default";
410 sata0: sata-host@a0000 {
411 compatible = "marvell,orion-sata";
412 reg = <0xa0000 0x2400>;
414 clocks = <&gate_clk 3>;
419 rtc: real-time-clock@d8500 {
420 compatible = "marvell,orion-rtc";
421 reg = <0xd8500 0x20>;
424 crypto: crypto-engine@30000 {
425 compatible = "marvell,orion-crypto";
426 reg = <0x30000 0x10000>,
428 reg-names = "regs", "sram";
430 clocks = <&gate_clk 15>;
434 xor0: dma-engine@60800 {
435 compatible = "marvell,orion-xor";
438 clocks = <&gate_clk 23>;
455 xor1: dma-engine@60900 {
456 compatible = "marvell,orion-xor";
459 clocks = <&gate_clk 24>;
476 mdio: mdio-bus@72004 {
477 compatible = "marvell,orion-mdio";
478 #address-cells = <1>;
480 reg = <0x72004 0x84>;
482 clocks = <&gate_clk 2>;
485 ethphy: ethernet-phy {
486 device-type = "ethernet-phy";
487 /* set phy address in board file */
491 eth: ethernet-controller@72000 {
492 compatible = "marvell,orion-eth";
493 #address-cells = <1>;
495 reg = <0x72000 0x4000>;
496 clocks = <&gate_clk 2>;
497 marvell,tx-checksum-limit = <1600>;
501 device_type = "network";
502 compatible = "marvell,orion-eth-port";
505 /* overwrite MAC address in bootloader */
506 local-mac-address = [00 00 00 00 00 00];
507 phy-handle = <ðphy>;