Merge tag 'iio-fixes-for-5.6a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / dm816x-clocks.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 &scrm {
4         main_fapll: main_fapll {
5                 #clock-cells = <1>;
6                 compatible = "ti,dm816-fapll-clock";
7                 reg = <0x400 0x40>;
8                 clocks = <&sys_clkin_ck &sys_clkin_ck>;
9                 clock-indices = <1>, <2>, <3>, <4>, <5>,
10                                 <6>, <7>;
11                 clock-output-names = "main_pll_clk1",
12                                      "main_pll_clk2",
13                                      "main_pll_clk3",
14                                      "main_pll_clk4",
15                                      "main_pll_clk5",
16                                      "main_pll_clk6",
17                                      "main_pll_clk7";
18         };
19
20         ddr_fapll: ddr_fapll {
21                 #clock-cells = <1>;
22                 compatible = "ti,dm816-fapll-clock";
23                 reg = <0x440 0x30>;
24                 clocks = <&sys_clkin_ck &sys_clkin_ck>;
25                 clock-indices = <1>, <2>, <3>, <4>;
26                 clock-output-names = "ddr_pll_clk1",
27                                      "ddr_pll_clk2",
28                                      "ddr_pll_clk3",
29                                      "ddr_pll_clk4";
30         };
31
32         video_fapll: video_fapll {
33                 #clock-cells = <1>;
34                 compatible = "ti,dm816-fapll-clock";
35                 reg = <0x470 0x30>;
36                 clocks = <&sys_clkin_ck &sys_clkin_ck>;
37                 clock-indices = <1>, <2>, <3>;
38                 clock-output-names = "video_pll_clk1",
39                                      "video_pll_clk2",
40                                      "video_pll_clk3";
41         };
42
43         audio_fapll: audio_fapll {
44                 #clock-cells = <1>;
45                 compatible = "ti,dm816-fapll-clock";
46                 reg = <0x4a0 0x30>;
47                 clocks = <&main_fapll 7>, < &sys_clkin_ck>;
48                 clock-indices = <1>, <2>, <3>, <4>, <5>;
49                 clock-output-names = "audio_pll_clk1",
50                                      "audio_pll_clk2",
51                                      "audio_pll_clk3",
52                                      "audio_pll_clk4",
53                                      "audio_pll_clk5";
54         };
55 };
56
57 &scrm_clocks {
58         secure_32k_ck: secure_32k_ck {
59                 #clock-cells = <0>;
60                 compatible = "fixed-clock";
61                 clock-frequency = <32768>;
62         };
63
64         sys_32k_ck: sys_32k_ck {
65                 #clock-cells = <0>;
66                 compatible = "fixed-clock";
67                 clock-frequency = <32768>;
68         };
69
70         tclkin_ck: tclkin_ck {
71                 #clock-cells = <0>;
72                 compatible = "fixed-clock";
73                 clock-frequency = <32768>;
74         };
75
76         sys_clkin_ck: sys_clkin_ck {
77                 #clock-cells = <0>;
78                 compatible = "fixed-clock";
79                 clock-frequency = <27000000>;
80         };
81 };
82
83 /* 0x48180000 */
84 &prcm_clocks {
85         clkout_pre_ck: clkout_pre_ck@100 {
86                 #clock-cells = <0>;
87                 compatible = "ti,mux-clock";
88                 clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
89                           &audio_fapll 1>;
90                 reg = <0x100>;
91         };
92
93         clkout_div_ck: clkout_div_ck@100 {
94                 #clock-cells = <0>;
95                 compatible = "ti,divider-clock";
96                 clocks = <&clkout_pre_ck>;
97                 ti,bit-shift = <3>;
98                 ti,max-div = <8>;
99                 reg = <0x100>;
100         };
101
102         clkout_ck: clkout_ck@100 {
103                 #clock-cells = <0>;
104                 compatible = "ti,gate-clock";
105                 clocks = <&clkout_div_ck>;
106                 ti,bit-shift = <7>;
107                 reg = <0x100>;
108         };
109
110         /* CM_DPLL clocks p1795 */
111         sysclk1_ck: sysclk1_ck@300 {
112                 #clock-cells = <0>;
113                 compatible = "ti,divider-clock";
114                 clocks = <&main_fapll 1>;
115                 ti,max-div = <7>;
116                 reg = <0x0300>;
117         };
118
119         sysclk2_ck: sysclk2_ck@304 {
120                 #clock-cells = <0>;
121                 compatible = "ti,divider-clock";
122                 clocks = <&main_fapll 2>;
123                 ti,max-div = <7>;
124                 reg = <0x0304>;
125         };
126
127         sysclk3_ck: sysclk3_ck@308 {
128                 #clock-cells = <0>;
129                 compatible = "ti,divider-clock";
130                 clocks = <&main_fapll 3>;
131                 ti,max-div = <7>;
132                 reg = <0x0308>;
133         };
134
135         sysclk4_ck: sysclk4_ck@30c {
136                 #clock-cells = <0>;
137                 compatible = "ti,divider-clock";
138                 clocks = <&main_fapll 4>;
139                 ti,max-div = <1>;
140                 reg = <0x030c>;
141         };
142
143         sysclk5_ck: sysclk5_ck@310 {
144                 #clock-cells = <0>;
145                 compatible = "ti,divider-clock";
146                 clocks = <&sysclk4_ck>;
147                 ti,max-div = <1>;
148                 reg = <0x0310>;
149         };
150
151         sysclk6_ck: sysclk6_ck@314 {
152                 #clock-cells = <0>;
153                 compatible = "ti,divider-clock";
154                 clocks = <&main_fapll 4>;
155                 ti,dividers = <2>, <4>;
156                 reg = <0x0314>;
157         };
158
159         sysclk10_ck: sysclk10_ck@324 {
160                 #clock-cells = <0>;
161                 compatible = "ti,divider-clock";
162                 clocks = <&ddr_fapll 2>;
163                 ti,max-div = <7>;
164                 reg = <0x0324>;
165         };
166
167         sysclk24_ck: sysclk24_ck@3b4 {
168                 #clock-cells = <0>;
169                 compatible = "ti,divider-clock";
170                 clocks = <&main_fapll 5>;
171                 ti,max-div = <7>;
172                 reg = <0x03b4>;
173         };
174
175         mpu_ck: mpu_ck@15dc {
176                 #clock-cells = <0>;
177                 compatible = "ti,gate-clock";
178                 clocks = <&sysclk2_ck>;
179                 ti,bit-shift = <1>;
180                 reg = <0x15dc>;
181         };
182
183         audio_pll_a_ck: audio_pll_a_ck@35c {
184                 #clock-cells = <0>;
185                 compatible = "ti,divider-clock";
186                 clocks = <&audio_fapll 1>;
187                 ti,max-div = <7>;
188                 reg = <0x035c>;
189         };
190
191         sysclk18_ck: sysclk18_ck@378 {
192                 #clock-cells = <0>;
193                 compatible = "ti,mux-clock";
194                 clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
195                 reg = <0x0378>;
196         };
197
198         timer1_fck: timer1_fck@390 {
199                 #clock-cells = <0>;
200                 compatible = "ti,mux-clock";
201                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
202                 reg = <0x0390>;
203         };
204
205         timer2_fck: timer2_fck@394 {
206                 #clock-cells = <0>;
207                 compatible = "ti,mux-clock";
208                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
209                 reg = <0x0394>;
210         };
211
212         timer3_fck: timer3_fck@398 {
213                 #clock-cells = <0>;
214                 compatible = "ti,mux-clock";
215                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
216                 reg = <0x0398>;
217         };
218
219         timer4_fck: timer4_fck@39c {
220                 #clock-cells = <0>;
221                 compatible = "ti,mux-clock";
222                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
223                 reg = <0x039c>;
224         };
225
226         timer5_fck: timer5_fck@3a0 {
227                 #clock-cells = <0>;
228                 compatible = "ti,mux-clock";
229                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
230                 reg = <0x03a0>;
231         };
232
233         timer6_fck: timer6_fck@3a4 {
234                 #clock-cells = <0>;
235                 compatible = "ti,mux-clock";
236                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
237                 reg = <0x03a4>;
238         };
239
240         timer7_fck: timer7_fck@3a8 {
241                 #clock-cells = <0>;
242                 compatible = "ti,mux-clock";
243                 clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
244                 reg = <0x03a8>;
245         };
246 };
247
248 &prcm {
249         default_cm: default_cm@500 {
250                 compatible = "ti,omap4-cm";
251                 reg = <0x500 0x100>;
252                 #address-cells = <1>;
253                 #size-cells = <1>;
254                 ranges = <0 0x500 0x100>;
255
256                 default_clkctrl: clk@0 {
257                         compatible = "ti,clkctrl";
258                         reg = <0x0 0x5c>;
259                         #clock-cells = <2>;
260                 };
261         };
262
263         alwon_cm: alwon_cm@1400 {
264                 compatible = "ti,omap4-cm";
265                 reg = <0x1400 0x300>;
266                 #address-cells = <1>;
267                 #size-cells = <1>;
268                 ranges = <0 0x1400 0x300>;
269
270                 alwon_clkctrl: clk@0 {
271                         compatible = "ti,clkctrl";
272                         reg = <0x0 0x208>;
273                         #clock-cells = <2>;
274                 };
275         };
276 };