arch/arm/boot/dts/berlin2q.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
   4  */
   5
   6 #include <dt-bindings/clock/berlin2q.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         model = "Marvell Armada 1500 pro (BG2-Q) SoC";
  11         compatible = "marvell,berlin2q", "marvell,berlin";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 enable-method = "marvell,berlin-smp";
  24
  25                 cpu0: cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         next-level-cache = <&l2>;
  29                         reg = <0>;
  30
  31                         clocks = <&chip_clk CLKID_CPU>;
  32                         clock-latency = <100000>;
  33                         /* Can be modified by the bootloader */
  34                         operating-points = <
  35                                 /* kHz    uV */
  36                                 1200000 1200000
  37                                 1000000 1200000
  38                                 800000  1200000
  39                                 600000  1200000
  40                         >;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         compatible = "arm,cortex-a9";
  45                         device_type = "cpu";
  46                         next-level-cache = <&l2>;
  47                         reg = <1>;
  48                 };
  49
  50                 cpu2: cpu@2 {
  51                         compatible = "arm,cortex-a9";
  52                         device_type = "cpu";
  53                         next-level-cache = <&l2>;
  54                         reg = <2>;
  55                 };
  56
  57                 cpu3: cpu@3 {
  58                         compatible = "arm,cortex-a9";
  59                         device_type = "cpu";
  60                         next-level-cache = <&l2>;
  61                         reg = <3>;
  62                 };
  63         };
  64
  65         refclk: oscillator {
  66                 compatible = "fixed-clock";
  67                 #clock-cells = <0>;
  68                 clock-frequency = <25000000>;
  69         };
  70
  71         soc@f7000000 {
  72                 compatible = "simple-bus";
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75
  76                 ranges = <0 0xf7000000 0x1000000>;
  77                 interrupt-parent = <&gic>;
  78
  79                 pmu {
  80                         compatible = "arm,cortex-a9-pmu";
  81                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  85                         interrupt-affinity = <&cpu0>,
  86                                              <&cpu1>,
  87                                              <&cpu2>,
  88                                              <&cpu3>;
  89                 };
  90
  91                 sdhci0: sdhci@ab0000 {
  92                         compatible = "mrvl,pxav3-mmc";
  93                         reg = <0xab0000 0x200>;
  94                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
  95                         clock-names = "io", "core";
  96                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  97                         status = "disabled";
  98                 };
  99
 100                 sdhci1: sdhci@ab0800 {
 101                         compatible = "mrvl,pxav3-mmc";
 102                         reg = <0xab0800 0x200>;
 103                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
 104                         clock-names = "io", "core";
 105                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 106                         status = "disabled";
 107                 };
 108
 109                 sdhci2: sdhci@ab1000 {
 110                         compatible = "mrvl,pxav3-mmc";
 111                         reg = <0xab1000 0x200>;
 112                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 113                         clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
 114                         clock-names = "io", "core";
 115                         status = "disabled";
 116                 };
 117
 118                 l2: l2-cache-controller@ac0000 {
 119                         compatible = "arm,pl310-cache";
 120                         reg = <0xac0000 0x1000>;
 121                         cache-unified;
 122                         cache-level = <2>;
 123                         arm,data-latency = <2 2 2>;
 124                         arm,tag-latency = <2 2 2>;
 125                 };
 126
 127                 scu: snoop-control-unit@ad0000 {
 128                         compatible = "arm,cortex-a9-scu";
 129                         reg = <0xad0000 0x58>;
 130                 };
 131
 132                 local-timer@ad0600 {
 133                         compatible = "arm,cortex-a9-twd-timer";
 134                         reg = <0xad0600 0x20>;
 135                         clocks = <&chip_clk CLKID_TWD>;
 136                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 137                 };
 138
 139                 gic: interrupt-controller@ad1000 {
 140                         compatible = "arm,cortex-a9-gic";
 141                         reg = <0xad1000 0x1000>, <0xad0100 0x100>;
 142                         interrupt-controller;
 143                         #interrupt-cells = <3>;
 144                 };
 145
 146                 usb_phy2: phy@a2f400 {
 147                         compatible = "marvell,berlin2cd-usb-phy";
 148                         reg = <0xa2f400 0x128>;
 149                         #phy-cells = <0>;
 150                         resets = <&chip_rst 0x104 14>;
 151                         status = "disabled";
 152                 };
 153
 154                 usb2: usb@a30000 {
 155                         compatible = "chipidea,usb2";
 156                         reg = <0xa30000 0x10000>;
 157                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&chip_clk CLKID_USB2>;
 159                         phys = <&usb_phy2>;
 160                         phy-names = "usb-phy";
 161                         status = "disabled";
 162                 };
 163
 164                 usb_phy0: phy@b74000 {
 165                         compatible = "marvell,berlin2cd-usb-phy";
 166                         reg = <0xb74000 0x128>;
 167                         #phy-cells = <0>;
 168                         resets = <&chip_rst 0x104 12>;
 169                         status = "disabled";
 170                 };
 171
 172                 usb_phy1: phy@b78000 {
 173                         compatible = "marvell,berlin2cd-usb-phy";
 174                         reg = <0xb78000 0x128>;
 175                         #phy-cells = <0>;
 176                         resets = <&chip_rst 0x104 13>;
 177                         status = "disabled";
 178                 };
 179
 180                 eth0: ethernet@b90000 {
 181                         compatible = "marvell,pxa168-eth";
 182                         reg = <0xb90000 0x10000>;
 183                         clocks = <&chip_clk CLKID_GETH0>;
 184                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 185                         /* set by bootloader */
 186                         local-mac-address = [00 00 00 00 00 00];
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         phy-connection-type = "mii";
 190                         phy-handle = <&ethphy0>;
 191                         status = "disabled";
 192
 193                         ethphy0: ethernet-phy@0 {
 194                                 reg = <0>;
 195                         };
 196                 };
 197
 198                 cpu-ctrl@dd0000 {
 199                         compatible = "marvell,berlin-cpu-ctrl";
 200                         reg = <0xdd0000 0x10000>;
 201                 };
 202
 203                 apb@e80000 {
 204                         compatible = "simple-bus";
 205                         #address-cells = <1>;
 206                         #size-cells = <1>;
 207
 208                         ranges = <0 0xe80000 0x10000>;
 209                         interrupt-parent = <&aic>;
 210
 211                         gpio0: gpio@400 {
 212                                 compatible = "snps,dw-apb-gpio";
 213                                 reg = <0x0400 0x400>;
 214                                 #address-cells = <1>;
 215                                 #size-cells = <0>;
 216
 217                                 porta: gpio-port@0 {
 218                                         compatible = "snps,dw-apb-gpio-port";
 219                                         gpio-controller;
 220                                         #gpio-cells = <2>;
 221                                         snps,nr-gpios = <32>;
 222                                         reg = <0>;
 223                                         interrupt-controller;
 224                                         #interrupt-cells = <2>;
 225                                         interrupts = <0>;
 226                                 };
 227                         };
 228
 229                         gpio1: gpio@800 {
 230                                 compatible = "snps,dw-apb-gpio";
 231                                 reg = <0x0800 0x400>;
 232                                 #address-cells = <1>;
 233                                 #size-cells = <0>;
 234
 235                                 portb: gpio-port@1 {
 236                                         compatible = "snps,dw-apb-gpio-port";
 237                                         gpio-controller;
 238                                         #gpio-cells = <2>;
 239                                         snps,nr-gpios = <32>;
 240                                         reg = <0>;
 241                                         interrupt-controller;
 242                                         #interrupt-cells = <2>;
 243                                         interrupts = <1>;
 244                                 };
 245                         };
 246
 247                         gpio2: gpio@c00 {
 248                                 compatible = "snps,dw-apb-gpio";
 249                                 reg = <0x0c00 0x400>;
 250                                 #address-cells = <1>;
 251                                 #size-cells = <0>;
 252
 253                                 portc: gpio-port@2 {
 254                                         compatible = "snps,dw-apb-gpio-port";
 255                                         gpio-controller;
 256                                         #gpio-cells = <2>;
 257                                         snps,nr-gpios = <32>;
 258                                         reg = <0>;
 259                                         interrupt-controller;
 260                                         #interrupt-cells = <2>;
 261                                         interrupts = <2>;
 262                                 };
 263                         };
 264
 265                         gpio3: gpio@1000 {
 266                                 compatible = "snps,dw-apb-gpio";
 267                                 reg = <0x1000 0x400>;
 268                                 #address-cells = <1>;
 269                                 #size-cells = <0>;
 270
 271                                 portd: gpio-port@3 {
 272                                         compatible = "snps,dw-apb-gpio-port";
 273                                         gpio-controller;
 274                                         #gpio-cells = <2>;
 275                                         snps,nr-gpios = <32>;
 276                                         reg = <0>;
 277                                         interrupt-controller;
 278                                         #interrupt-cells = <2>;
 279                                         interrupts = <3>;
 280                                 };
 281                         };
 282
 283                         i2c0: i2c@1400 {
 284                                 compatible = "snps,designware-i2c";
 285                                 #address-cells = <1>;
 286                                 #size-cells = <0>;
 287                                 reg = <0x1400 0x100>;
 288                                 interrupts = <4>;
 289                                 clocks = <&chip_clk CLKID_CFG>;
 290                                 pinctrl-0 = <&twsi0_pmux>;
 291                                 pinctrl-names = "default";
 292                                 status = "disabled";
 293                         };
 294
 295                         i2c1: i2c@1800 {
 296                                 compatible = "snps,designware-i2c";
 297                                 #address-cells = <1>;
 298                                 #size-cells = <0>;
 299                                 reg = <0x1800 0x100>;
 300                                 interrupts = <5>;
 301                                 clocks = <&chip_clk CLKID_CFG>;
 302                                 pinctrl-0 = <&twsi1_pmux>;
 303                                 pinctrl-names = "default";
 304                                 status = "disabled";
 305                         };
 306
 307                         timer0: timer@2c00 {
 308                                 compatible = "snps,dw-apb-timer";
 309                                 reg = <0x2c00 0x14>;
 310                                 clocks = <&chip_clk CLKID_CFG>;
 311                                 clock-names = "timer";
 312                                 interrupts = <8>;
 313                         };
 314
 315                         timer1: timer@2c14 {
 316                                 compatible = "snps,dw-apb-timer";
 317                                 reg = <0x2c14 0x14>;
 318                                 clocks = <&chip_clk CLKID_CFG>;
 319                                 clock-names = "timer";
 320                         };
 321
 322                         timer2: timer@2c28 {
 323                                 compatible = "snps,dw-apb-timer";
 324                                 reg = <0x2c28 0x14>;
 325                                 clocks = <&chip_clk CLKID_CFG>;
 326                                 clock-names = "timer";
 327                                 status = "disabled";
 328                         };
 329
 330                         timer3: timer@2c3c {
 331                                 compatible = "snps,dw-apb-timer";
 332                                 reg = <0x2c3c 0x14>;
 333                                 clocks = <&chip_clk CLKID_CFG>;
 334                                 clock-names = "timer";
 335                                 status = "disabled";
 336                         };
 337
 338                         timer4: timer@2c50 {
 339                                 compatible = "snps,dw-apb-timer";
 340                                 reg = <0x2c50 0x14>;
 341                                 clocks = <&chip_clk CLKID_CFG>;
 342                                 clock-names = "timer";
 343                                 status = "disabled";
 344                         };
 345
 346                         timer5: timer@2c64 {
 347                                 compatible = "snps,dw-apb-timer";
 348                                 reg = <0x2c64 0x14>;
 349                                 clocks = <&chip_clk CLKID_CFG>;
 350                                 clock-names = "timer";
 351                                 status = "disabled";
 352                         };
 353
 354                         timer6: timer@2c78 {
 355                                 compatible = "snps,dw-apb-timer";
 356                                 reg = <0x2c78 0x14>;
 357                                 clocks = <&chip_clk CLKID_CFG>;
 358                                 clock-names = "timer";
 359                                 status = "disabled";
 360                         };
 361
 362                         timer7: timer@2c8c {
 363                                 compatible = "snps,dw-apb-timer";
 364                                 reg = <0x2c8c 0x14>;
 365                                 clocks = <&chip_clk CLKID_CFG>;
 366                                 clock-names = "timer";
 367                                 status = "disabled";
 368                         };
 369
 370                         aic: interrupt-controller@3800 {
 371                                 compatible = "snps,dw-apb-ictl";
 372                                 reg = <0x3800 0x30>;
 373                                 interrupt-controller;
 374                                 #interrupt-cells = <1>;
 375                                 interrupt-parent = <&gic>;
 376                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 377                         };
 378                 };
 379
 380                 chip: chip-control@ea0000 {
 381                         compatible = "simple-mfd", "syscon";
 382                         reg = <0xea0000 0x400>, <0xdd0170 0x10>;
 383
 384                         chip_clk: clock {
 385                                 compatible = "marvell,berlin2q-clk";
 386                                 #clock-cells = <1>;
 387                                 clocks = <&refclk>;
 388                                 clock-names = "refclk";
 389                         };
 390
 391                         soc_pinctrl: pin-controller {
 392                                 compatible = "marvell,berlin2q-soc-pinctrl";
 393
 394                                 sd1_pmux: sd1-pmux {
 395                                         groups = "G31";
 396                                         function = "sd1";
 397                                 };
 398
 399                                 twsi0_pmux: twsi0-pmux {
 400                                         groups = "G6";
 401                                         function = "twsi0";
 402                                 };
 403
 404                                 twsi1_pmux: twsi1-pmux {
 405                                         groups = "G7";
 406                                         function = "twsi1";
 407                                 };
 408                         };
 409
 410                         chip_rst: reset {
 411                                 compatible = "marvell,berlin2-reset";
 412                                 #reset-cells = <2>;
 413                         };
 414                 };
 415
 416                 ahci: sata@e90000 {
 417                         compatible = "marvell,berlin2q-ahci", "generic-ahci";
 418                         reg = <0xe90000 0x1000>;
 419                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&chip_clk CLKID_SATA>;
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423
 424                         sata0: sata-port@0 {
 425                                 reg = <0>;
 426                                 phys = <&sata_phy 0>;
 427                                 status = "disabled";
 428                         };
 429
 430                         sata1: sata-port@1 {
 431                                 reg = <1>;
 432                                 phys = <&sata_phy 1>;
 433                                 status = "disabled";
 434                         };
 435                 };
 436
 437                 sata_phy: phy@e900a0 {
 438                         compatible = "marvell,berlin2q-sata-phy";
 439                         reg = <0xe900a0 0x200>;
 440                         clocks = <&chip_clk CLKID_SATA>;
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         #phy-cells = <1>;
 444                         status = "disabled";
 445
 446                         sata-phy@0 {
 447                                 reg = <0>;
 448                         };
 449
 450                         sata-phy@1 {
 451                                 reg = <1>;
 452                         };
 453                 };
 454
 455                 usb0: usb@ed0000 {
 456                         compatible = "chipidea,usb2";
 457                         reg = <0xed0000 0x10000>;
 458                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 459                         clocks = <&chip_clk CLKID_USB0>;
 460                         phys = <&usb_phy0>;
 461                         phy-names = "usb-phy";
 462                         status = "disabled";
 463                 };
 464
 465                 usb1: usb@ee0000 {
 466                         compatible = "chipidea,usb2";
 467                         reg = <0xee0000 0x10000>;
 468                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 469                         clocks = <&chip_clk CLKID_USB1>;
 470                         phys = <&usb_phy1>;
 471                         phy-names = "usb-phy";
 472                         status = "disabled";
 473                 };
 474
 475                 pwm: pwm@f20000 {
 476                         compatible = "marvell,berlin-pwm";
 477                         reg = <0xf20000 0x40>;
 478                         clocks = <&chip_clk CLKID_CFG>;
 479                         #pwm-cells = <3>;
 480                 };
 481
 482                 apb@fc0000 {
 483                         compatible = "simple-bus";
 484                         #address-cells = <1>;
 485                         #size-cells = <1>;
 486
 487                         ranges = <0 0xfc0000 0x10000>;
 488                         interrupt-parent = <&sic>;
 489
 490                         wdt0: watchdog@1000 {
 491                                 compatible = "snps,dw-wdt";
 492                                 reg = <0x1000 0x100>;
 493                                 clocks = <&refclk>;
 494                                 interrupts = <0>;
 495                         };
 496
 497                         wdt1: watchdog@2000 {
 498                                 compatible = "snps,dw-wdt";
 499                                 reg = <0x2000 0x100>;
 500                                 clocks = <&refclk>;
 501                                 interrupts = <1>;
 502                         };
 503
 504                         wdt2: watchdog@3000 {
 505                                 compatible = "snps,dw-wdt";
 506                                 reg = <0x3000 0x100>;
 507                                 clocks = <&refclk>;
 508                                 interrupts = <2>;
 509                         };
 510
 511                         sm_gpio1: gpio@5000 {
 512                                 compatible = "snps,dw-apb-gpio";
 513                                 reg = <0x5000 0x400>;
 514                                 #address-cells = <1>;
 515                                 #size-cells = <0>;
 516
 517                                 portf: gpio-port@5 {
 518                                         compatible = "snps,dw-apb-gpio-port";
 519                                         gpio-controller;
 520                                         #gpio-cells = <2>;
 521                                         snps,nr-gpios = <32>;
 522                                         reg = <0>;
 523                                 };
 524                         };
 525
 526                         i2c2: i2c@7000 {
 527                                 compatible = "snps,designware-i2c";
 528                                 #address-cells = <1>;
 529                                 #size-cells = <0>;
 530                                 reg = <0x7000 0x100>;
 531                                 interrupts = <6>;
 532                                 clocks = <&refclk>;
 533                                 pinctrl-0 = <&twsi2_pmux>;
 534                                 pinctrl-names = "default";
 535                                 status = "disabled";
 536                         };
 537
 538                         i2c3: i2c@8000 {
 539                                 compatible = "snps,designware-i2c";
 540                                 #address-cells = <1>;
 541                                 #size-cells = <0>;
 542                                 reg = <0x8000 0x100>;
 543                                 interrupts = <7>;
 544                                 clocks = <&refclk>;
 545                                 pinctrl-0 = <&twsi3_pmux>;
 546                                 pinctrl-names = "default";
 547                                 status = "disabled";
 548                         };
 549
 550                         uart0: uart@9000 {
 551                                 compatible = "snps,dw-apb-uart";
 552                                 reg = <0x9000 0x100>;
 553                                 interrupts = <8>;
 554                                 clocks = <&refclk>;
 555                                 reg-shift = <2>;
 556                                 pinctrl-0 = <&uart0_pmux>;
 557                                 pinctrl-names = "default";
 558                                 status = "disabled";
 559                         };
 560
 561                         uart1: uart@a000 {
 562                                 compatible = "snps,dw-apb-uart";
 563                                 reg = <0xa000 0x100>;
 564                                 interrupts = <9>;
 565                                 clocks = <&refclk>;
 566                                 reg-shift = <2>;
 567                                 pinctrl-0 = <&uart1_pmux>;
 568                                 pinctrl-names = "default";
 569                                 status = "disabled";
 570                         };
 571
 572                         sm_gpio0: gpio@c000 {
 573                                 compatible = "snps,dw-apb-gpio";
 574                                 reg = <0xc000 0x400>;
 575                                 #address-cells = <1>;
 576                                 #size-cells = <0>;
 577
 578                                 porte: gpio-port@4 {
 579                                         compatible = "snps,dw-apb-gpio-port";
 580                                         gpio-controller;
 581                                         #gpio-cells = <2>;
 582                                         snps,nr-gpios = <32>;
 583                                         reg = <0>;
 584                                 };
 585                         };
 586
 587                         sysctrl: pin-controller@d000 {
 588                                 compatible = "simple-mfd", "syscon";
 589                                 reg = <0xd000 0x100>;
 590
 591                                 sys_pinctrl: pin-controller {
 592                                         compatible = "marvell,berlin2q-system-pinctrl";
 593
 594                                         uart0_pmux: uart0-pmux {
 595                                                 groups = "GSM12";
 596                                                 function = "uart0";
 597                                         };
 598
 599                                         uart1_pmux: uart1-pmux {
 600                                                 groups = "GSM14";
 601                                                 function = "uart1";
 602                                         };
 603
 604                                         twsi2_pmux: twsi2-pmux {
 605                                                 groups = "GSM13";
 606                                                 function = "twsi2";
 607                                         };
 608
 609                                         twsi3_pmux: twsi3-pmux {
 610                                                 groups = "GSM14";
 611                                                 function = "twsi3";
 612                                         };
 613                                 };
 614
 615                                 adc: adc {
 616                                         compatible = "marvell,berlin2-adc";
 617                                         interrupts = <12>, <14>;
 618                                         interrupt-names = "adc", "tsen";
 619                                 };
 620                         };
 621
 622                         sic: interrupt-controller@e000 {
 623                                 compatible = "snps,dw-apb-ictl";
 624                                 reg = <0xe000 0x30>;
 625                                 interrupt-controller;
 626                                 #interrupt-cells = <1>;
 627                                 interrupt-parent = <&gic>;
 628                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 629                         };
 630                 };
 631         };
 632 };