1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
8 compatible = "brcm,bcm2711";
13 interrupt-parent = <&gicv2>;
18 * Common BCM283x peripherals
19 * BCM2711-specific peripherals
20 * ARM-local peripherals
22 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
23 <0x7c000000 0x0 0xfc000000 0x02000000>,
24 <0x40000000 0x0 0xff800000 0x00800000>;
25 /* Emulate a contiguous 30-bit address range for DMA */
26 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
29 * This node is the provider for the enable-method for
30 * bringing up secondary cores.
32 local_intc: local_intc@40000000 {
33 compatible = "brcm,bcm2836-l1-intc";
34 reg = <0x40000000 0x100>;
37 gicv2: interrupt-controller@40041000 {
39 #interrupt-cells = <3>;
40 compatible = "arm,gic-400";
41 reg = <0x40041000 0x1000>,
45 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
46 IRQ_TYPE_LEVEL_HIGH)>;
49 avs_monitor: avs-monitor@7d5d2000 {
50 compatible = "brcm,bcm2711-avs-monitor",
51 "syscon", "simple-mfd";
52 reg = <0x7d5d2000 0xf00>;
55 compatible = "brcm,bcm2711-thermal";
56 #thermal-sensor-cells = <0>;
61 compatible = "brcm,bcm2835-dma";
62 reg = <0x7e007000 0xb00>;
63 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
75 interrupt-names = "dma0",
87 brcm,dma-channel-mask = <0x07f5>;
90 pm: watchdog@7e100000 {
91 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
92 #power-domain-cells = <1>;
94 reg = <0x7e100000 0x114>,
97 clocks = <&clocks BCM2835_CLOCK_V3D>,
98 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
99 <&clocks BCM2835_CLOCK_H264>,
100 <&clocks BCM2835_CLOCK_ISP>;
101 clock-names = "v3d", "peri_image", "h264", "isp";
102 system-power-controller;
106 compatible = "brcm,bcm2711-rng200";
107 reg = <0x7e104000 0x28>;
110 uart2: serial@7e201400 {
111 compatible = "arm,pl011", "arm,primecell";
112 reg = <0x7e201400 0x200>;
113 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&clocks BCM2835_CLOCK_UART>,
115 <&clocks BCM2835_CLOCK_VPU>;
116 clock-names = "uartclk", "apb_pclk";
117 arm,primecell-periphid = <0x00241011>;
121 uart3: serial@7e201600 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x7e201600 0x200>;
124 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&clocks BCM2835_CLOCK_UART>,
126 <&clocks BCM2835_CLOCK_VPU>;
127 clock-names = "uartclk", "apb_pclk";
128 arm,primecell-periphid = <0x00241011>;
132 uart4: serial@7e201800 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0x7e201800 0x200>;
135 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clocks BCM2835_CLOCK_UART>,
137 <&clocks BCM2835_CLOCK_VPU>;
138 clock-names = "uartclk", "apb_pclk";
139 arm,primecell-periphid = <0x00241011>;
143 uart5: serial@7e201a00 {
144 compatible = "arm,pl011", "arm,primecell";
145 reg = <0x7e201a00 0x200>;
146 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clocks BCM2835_CLOCK_UART>,
148 <&clocks BCM2835_CLOCK_VPU>;
149 clock-names = "uartclk", "apb_pclk";
150 arm,primecell-periphid = <0x00241011>;
155 compatible = "brcm,bcm2835-spi";
156 reg = <0x7e204600 0x0200>;
157 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clocks BCM2835_CLOCK_VPU>;
159 #address-cells = <1>;
165 compatible = "brcm,bcm2835-spi";
166 reg = <0x7e204800 0x0200>;
167 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&clocks BCM2835_CLOCK_VPU>;
169 #address-cells = <1>;
175 compatible = "brcm,bcm2835-spi";
176 reg = <0x7e204a00 0x0200>;
177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&clocks BCM2835_CLOCK_VPU>;
179 #address-cells = <1>;
185 compatible = "brcm,bcm2835-spi";
186 reg = <0x7e204c00 0x0200>;
187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clocks BCM2835_CLOCK_VPU>;
189 #address-cells = <1>;
195 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
196 reg = <0x7e205600 0x200>;
197 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clocks BCM2835_CLOCK_VPU>;
199 #address-cells = <1>;
205 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
206 reg = <0x7e205800 0x200>;
207 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clocks BCM2835_CLOCK_VPU>;
209 #address-cells = <1>;
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
216 reg = <0x7e205a00 0x200>;
217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clocks BCM2835_CLOCK_VPU>;
219 #address-cells = <1>;
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
226 reg = <0x7e205c00 0x200>;
227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clocks BCM2835_CLOCK_VPU>;
229 #address-cells = <1>;
235 compatible = "brcm,bcm2835-pwm";
236 reg = <0x7e20c800 0x28>;
237 clocks = <&clocks BCM2835_CLOCK_PWM>;
238 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
239 assigned-clock-rates = <10000000>;
245 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
250 * emmc2 has different DMA constraints based on SoC revisions. It was
251 * moved into its own bus, so as for RPi4's firmware to update them.
252 * The firmware will find whether the emmc2bus alias is defined, and if
253 * so, it'll edit the dma-ranges property below accordingly.
256 compatible = "simple-bus";
257 #address-cells = <2>;
260 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
261 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
263 emmc2: emmc2@7e340000 {
264 compatible = "brcm,bcm2711-emmc2";
265 reg = <0x0 0x7e340000 0x100>;
266 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
273 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
274 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
278 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
282 compatible = "arm,armv8-timer";
283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
284 IRQ_TYPE_LEVEL_LOW)>,
285 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
286 IRQ_TYPE_LEVEL_LOW)>,
287 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
288 IRQ_TYPE_LEVEL_LOW)>,
289 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
290 IRQ_TYPE_LEVEL_LOW)>;
291 /* This only applies to the ARMv7 stub */
292 arm,cpu-registers-not-fw-configured;
296 #address-cells = <1>;
298 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
302 compatible = "arm,cortex-a72";
304 enable-method = "spin-table";
305 cpu-release-addr = <0x0 0x000000d8>;
310 compatible = "arm,cortex-a72";
312 enable-method = "spin-table";
313 cpu-release-addr = <0x0 0x000000e0>;
318 compatible = "arm,cortex-a72";
320 enable-method = "spin-table";
321 cpu-release-addr = <0x0 0x000000e8>;
326 compatible = "arm,cortex-a72";
328 enable-method = "spin-table";
329 cpu-release-addr = <0x0 0x000000f0>;
334 compatible = "simple-bus";
335 #address-cells = <2>;
338 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
339 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
341 pcie0: pcie@7d500000 {
342 compatible = "brcm,bcm2711-pcie";
343 reg = <0x0 0x7d500000 0x9310>;
345 #address-cells = <3>;
346 #interrupt-cells = <1>;
348 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "pcie", "msi";
351 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
352 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
353 IRQ_TYPE_LEVEL_HIGH>;
355 msi-parent = <&pcie0>;
357 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
360 * The wrapper around the PCIe block has a bug
361 * preventing it from accessing beyond the first 3GB of
364 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
369 genet: ethernet@7d580000 {
370 compatible = "brcm,bcm2711-genet-v5";
371 reg = <0x0 0x7d580000 0x10000>;
372 #address-cells = <0x1>;
374 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
378 genet_mdio: mdio@e14 {
379 compatible = "brcm,genet-mdio-v5";
382 #address-cells = <0x0>;
390 clock-frequency = <54000000>;
394 compatible = "brcm,bcm2711-cprman";
398 coefficients = <(-487) 410040>;
399 thermal-sensors = <&thermal>;
403 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
407 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
411 compatible = "brcm,bcm2711-gpio";
412 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
417 gpclk0_gpio49: gpclk0_gpio49 {
424 gpclk1_gpio50: gpclk1_gpio50 {
431 gpclk2_gpio51: gpclk2_gpio51 {
439 i2c0_gpio46: i2c0_gpio46 {
451 i2c1_gpio46: i2c1_gpio46 {
463 i2c3_gpio2: i2c3_gpio2 {
475 i2c3_gpio4: i2c3_gpio4 {
487 i2c4_gpio6: i2c4_gpio6 {
499 i2c4_gpio8: i2c4_gpio8 {
511 i2c5_gpio10: i2c5_gpio10 {
523 i2c5_gpio12: i2c5_gpio12 {
535 i2c6_gpio0: i2c6_gpio0 {
547 i2c6_gpio22: i2c6_gpio22 {
559 i2c_slave_gpio8: i2c_slave_gpio8 {
569 jtag_gpio48: jtag_gpio48 {
581 mii_gpio28: mii_gpio28 {
590 mii_gpio36: mii_gpio36 {
600 pcm_gpio50: pcm_gpio50 {
610 pwm0_0_gpio12: pwm0_0_gpio12 {
617 pwm0_0_gpio18: pwm0_0_gpio18 {
624 pwm1_0_gpio40: pwm1_0_gpio40 {
631 pwm0_1_gpio13: pwm0_1_gpio13 {
638 pwm0_1_gpio19: pwm0_1_gpio19 {
645 pwm1_1_gpio41: pwm1_1_gpio41 {
652 pwm0_1_gpio45: pwm0_1_gpio45 {
659 pwm0_0_gpio52: pwm0_0_gpio52 {
666 pwm0_1_gpio53: pwm0_1_gpio53 {
674 rgmii_gpio35: rgmii_gpio35 {
684 rgmii_irq_gpio34: rgmii_irq_gpio34 {
690 rgmii_irq_gpio39: rgmii_irq_gpio39 {
696 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
703 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
711 spi0_gpio46: spi0_gpio46 {
720 spi2_gpio46: spi2_gpio46 {
730 spi3_gpio0: spi3_gpio0 {
739 spi4_gpio4: spi4_gpio4 {
748 spi5_gpio12: spi5_gpio12 {
757 spi6_gpio18: spi6_gpio18 {
767 uart2_gpio0: uart2_gpio0 {
779 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
791 uart3_gpio4: uart3_gpio4 {
803 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
815 uart4_gpio8: uart4_gpio8 {
827 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
839 uart5_gpio12: uart5_gpio12 {
851 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
866 #address-cells = <2>;
871 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
872 * that's not good enough for the BCM2711 as some devices can
873 * only address the lower 1G of memory (ZONE_DMA).
875 alloc-ranges = <0x0 0x00000000 0x40000000>;
879 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
880 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
884 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
885 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
889 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
893 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
897 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
901 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
905 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
909 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
913 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
914 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
920 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
924 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
928 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
932 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
936 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;