1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
8 compatible = "brcm,bcm2711";
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
37 * Common BCM283x peripherals
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
49 * bringing up secondary cores.
51 local_intc: local_intc@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
53 reg = <0x40000000 0x100>;
56 gicv2: interrupt-controller@40041000 {
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
60 reg = <0x40041000 0x1000>,
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
65 IRQ_TYPE_LEVEL_HIGH)>;
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
71 reg = <0x7d5d2000 0xf00>;
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
80 compatible = "brcm,bcm2835-dma";
81 reg = <0x7e007000 0xb00>;
82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-names = "dma0",
106 brcm,dma-channel-mask = <0x07f5>;
109 pm: watchdog@7e100000 {
110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
113 reg = <0x7e100000 0x114>,
116 clocks = <&clocks BCM2835_CLOCK_V3D>,
117 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
118 <&clocks BCM2835_CLOCK_H264>,
119 <&clocks BCM2835_CLOCK_ISP>;
120 clock-names = "v3d", "peri_image", "h264", "isp";
121 system-power-controller;
125 compatible = "brcm,bcm2711-rng200";
126 reg = <0x7e104000 0x28>;
129 uart2: serial@7e201400 {
130 compatible = "arm,pl011", "arm,primecell";
131 reg = <0x7e201400 0x200>;
132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&clocks BCM2835_CLOCK_UART>,
134 <&clocks BCM2835_CLOCK_VPU>;
135 clock-names = "uartclk", "apb_pclk";
136 arm,primecell-periphid = <0x00241011>;
140 uart3: serial@7e201600 {
141 compatible = "arm,pl011", "arm,primecell";
142 reg = <0x7e201600 0x200>;
143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&clocks BCM2835_CLOCK_UART>,
145 <&clocks BCM2835_CLOCK_VPU>;
146 clock-names = "uartclk", "apb_pclk";
147 arm,primecell-periphid = <0x00241011>;
151 uart4: serial@7e201800 {
152 compatible = "arm,pl011", "arm,primecell";
153 reg = <0x7e201800 0x200>;
154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clocks BCM2835_CLOCK_UART>,
156 <&clocks BCM2835_CLOCK_VPU>;
157 clock-names = "uartclk", "apb_pclk";
158 arm,primecell-periphid = <0x00241011>;
162 uart5: serial@7e201a00 {
163 compatible = "arm,pl011", "arm,primecell";
164 reg = <0x7e201a00 0x200>;
165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&clocks BCM2835_CLOCK_UART>,
167 <&clocks BCM2835_CLOCK_VPU>;
168 clock-names = "uartclk", "apb_pclk";
169 arm,primecell-periphid = <0x00241011>;
174 compatible = "brcm,bcm2835-spi";
175 reg = <0x7e204600 0x0200>;
176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&clocks BCM2835_CLOCK_VPU>;
178 #address-cells = <1>;
184 compatible = "brcm,bcm2835-spi";
185 reg = <0x7e204800 0x0200>;
186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clocks BCM2835_CLOCK_VPU>;
188 #address-cells = <1>;
194 compatible = "brcm,bcm2835-spi";
195 reg = <0x7e204a00 0x0200>;
196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clocks BCM2835_CLOCK_VPU>;
198 #address-cells = <1>;
204 compatible = "brcm,bcm2835-spi";
205 reg = <0x7e204c00 0x0200>;
206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&clocks BCM2835_CLOCK_VPU>;
208 #address-cells = <1>;
214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
215 reg = <0x7e205600 0x200>;
216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clocks BCM2835_CLOCK_VPU>;
218 #address-cells = <1>;
224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
225 reg = <0x7e205800 0x200>;
226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clocks BCM2835_CLOCK_VPU>;
228 #address-cells = <1>;
234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
235 reg = <0x7e205a00 0x200>;
236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clocks BCM2835_CLOCK_VPU>;
238 #address-cells = <1>;
244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
245 reg = <0x7e205c00 0x200>;
246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clocks BCM2835_CLOCK_VPU>;
248 #address-cells = <1>;
253 pixelvalve0: pixelvalve@7e206000 {
254 compatible = "brcm,bcm2711-pixelvalve0";
255 reg = <0x7e206000 0x100>;
256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
260 pixelvalve1: pixelvalve@7e207000 {
261 compatible = "brcm,bcm2711-pixelvalve1";
262 reg = <0x7e207000 0x100>;
263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
267 pixelvalve2: pixelvalve@7e20a000 {
268 compatible = "brcm,bcm2711-pixelvalve2";
269 reg = <0x7e20a000 0x100>;
270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
275 compatible = "brcm,bcm2835-pwm";
276 reg = <0x7e20c800 0x28>;
277 clocks = <&clocks BCM2835_CLOCK_PWM>;
278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
279 assigned-clock-rates = <10000000>;
284 pixelvalve4: pixelvalve@7e216000 {
285 compatible = "brcm,bcm2711-pixelvalve4";
286 reg = <0x7e216000 0x100>;
287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
292 compatible = "brcm,bcm2711-hvs";
293 reg = <0x7e400000 0x8000>;
294 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
297 pixelvalve3: pixelvalve@7ec12000 {
298 compatible = "brcm,bcm2711-pixelvalve3";
299 reg = <0x7ec12000 0x100>;
300 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
305 compatible = "brcm,bcm2711-vec";
306 reg = <0x7ec13000 0x1000>;
307 clocks = <&clocks BCM2835_CLOCK_VEC>;
308 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
312 dvp: clock@7ef00000 {
313 compatible = "brcm,brcm2711-dvp";
314 reg = <0x7ef00000 0x10>;
315 clocks = <&clk_108MHz>;
320 aon_intr: interrupt-controller@7ef00100 {
321 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
322 reg = <0x7ef00100 0x30>;
323 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
324 interrupt-controller;
325 #interrupt-cells = <1>;
328 hdmi0: hdmi@7ef00700 {
329 compatible = "brcm,bcm2711-hdmi0";
330 reg = <0x7ef00700 0x300>,
348 clock-names = "hdmi", "bvb", "audio", "cec";
350 interrupt-parent = <&aon_intr>;
351 interrupts = <0>, <1>, <2>,
353 interrupt-names = "cec-tx", "cec-rx", "cec-low",
354 "wakeup", "hpd-connected", "hpd-removed";
357 dma-names = "audio-rx";
362 compatible = "brcm,bcm2711-hdmi-i2c";
363 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
364 reg-names = "bsc", "auto-i2c";
365 clock-frequency = <97500>;
369 hdmi1: hdmi@7ef05700 {
370 compatible = "brcm,bcm2711-hdmi1";
371 reg = <0x7ef05700 0x300>,
390 clock-names = "hdmi", "bvb", "audio", "cec";
392 interrupt-parent = <&aon_intr>;
393 interrupts = <8>, <7>, <6>,
395 interrupt-names = "cec-tx", "cec-rx", "cec-low",
396 "wakeup", "hpd-connected", "hpd-removed";
398 dma-names = "audio-rx";
403 compatible = "brcm,bcm2711-hdmi-i2c";
404 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
405 reg-names = "bsc", "auto-i2c";
406 clock-frequency = <97500>;
412 * emmc2 has different DMA constraints based on SoC revisions. It was
413 * moved into its own bus, so as for RPi4's firmware to update them.
414 * The firmware will find whether the emmc2bus alias is defined, and if
415 * so, it'll edit the dma-ranges property below accordingly.
418 compatible = "simple-bus";
419 #address-cells = <2>;
422 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
423 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
425 emmc2: mmc@7e340000 {
426 compatible = "brcm,bcm2711-emmc2";
427 reg = <0x0 0x7e340000 0x100>;
428 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
435 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
436 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
444 compatible = "arm,armv8-timer";
445 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
446 IRQ_TYPE_LEVEL_LOW)>,
447 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
448 IRQ_TYPE_LEVEL_LOW)>,
449 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
450 IRQ_TYPE_LEVEL_LOW)>,
451 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
452 IRQ_TYPE_LEVEL_LOW)>;
453 /* This only applies to the ARMv7 stub */
454 arm,cpu-registers-not-fw-configured;
458 #address-cells = <1>;
460 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
462 /* Source for d/i-cache-line-size and d/i-cache-sets
463 * https://developer.arm.com/documentation/100095/0003
464 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
465 * Source for d/i-cache-size
466 * https://www.raspberrypi.com/documentation/computers
467 * /processors.html#bcm2711
471 compatible = "arm,cortex-a72";
473 enable-method = "spin-table";
474 cpu-release-addr = <0x0 0x000000d8>;
475 d-cache-size = <0x8000>;
476 d-cache-line-size = <64>;
477 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
478 i-cache-size = <0xc000>;
479 i-cache-line-size = <64>;
480 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
481 next-level-cache = <&l2>;
486 compatible = "arm,cortex-a72";
488 enable-method = "spin-table";
489 cpu-release-addr = <0x0 0x000000e0>;
490 d-cache-size = <0x8000>;
491 d-cache-line-size = <64>;
492 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
493 i-cache-size = <0xc000>;
494 i-cache-line-size = <64>;
495 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
496 next-level-cache = <&l2>;
501 compatible = "arm,cortex-a72";
503 enable-method = "spin-table";
504 cpu-release-addr = <0x0 0x000000e8>;
505 d-cache-size = <0x8000>;
506 d-cache-line-size = <64>;
507 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
508 i-cache-size = <0xc000>;
509 i-cache-line-size = <64>;
510 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
511 next-level-cache = <&l2>;
516 compatible = "arm,cortex-a72";
518 enable-method = "spin-table";
519 cpu-release-addr = <0x0 0x000000f0>;
520 d-cache-size = <0x8000>;
521 d-cache-line-size = <64>;
522 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
523 i-cache-size = <0xc000>;
524 i-cache-line-size = <64>;
525 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
526 next-level-cache = <&l2>;
529 /* Source for d/i-cache-line-size and d/i-cache-sets
530 * https://developer.arm.com/documentation/100095/0003
531 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
532 * Source for d/i-cache-size
533 * https://www.raspberrypi.com/documentation/computers
534 * /processors.html#bcm2711
537 compatible = "cache";
538 cache-size = <0x100000>;
539 cache-line-size = <64>;
540 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
546 compatible = "simple-bus";
547 #address-cells = <2>;
550 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
551 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
553 pcie0: pcie@7d500000 {
554 compatible = "brcm,bcm2711-pcie";
555 reg = <0x0 0x7d500000 0x9310>;
557 #address-cells = <3>;
558 #interrupt-cells = <1>;
560 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-names = "pcie", "msi";
563 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
565 IRQ_TYPE_LEVEL_HIGH>,
566 <0 0 0 2 &gicv2 GIC_SPI 144
567 IRQ_TYPE_LEVEL_HIGH>,
568 <0 0 0 3 &gicv2 GIC_SPI 145
569 IRQ_TYPE_LEVEL_HIGH>,
570 <0 0 0 4 &gicv2 GIC_SPI 146
571 IRQ_TYPE_LEVEL_HIGH>;
573 msi-parent = <&pcie0>;
575 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
578 * The wrapper around the PCIe block has a bug
579 * preventing it from accessing beyond the first 3GB of
582 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
587 genet: ethernet@7d580000 {
588 compatible = "brcm,bcm2711-genet-v5";
589 reg = <0x0 0x7d580000 0x10000>;
590 #address-cells = <0x1>;
592 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
596 genet_mdio: mdio@e14 {
597 compatible = "brcm,genet-mdio-v5";
600 #address-cells = <0x1>;
608 clock-frequency = <54000000>;
612 compatible = "brcm,bcm2711-cprman";
616 coefficients = <(-487) 410040>;
617 thermal-sensors = <&thermal>;
621 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
625 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
626 compatible = "brcm,bcm2711-dsi1";
630 compatible = "brcm,bcm2711-gpio";
631 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
636 gpio-ranges = <&gpio 0 0 58>;
638 gpclk0_gpio49: gpclk0_gpio49 {
645 gpclk1_gpio50: gpclk1_gpio50 {
652 gpclk2_gpio51: gpclk2_gpio51 {
660 i2c0_gpio46: i2c0_gpio46 {
672 i2c1_gpio46: i2c1_gpio46 {
684 i2c3_gpio2: i2c3_gpio2 {
696 i2c3_gpio4: i2c3_gpio4 {
708 i2c4_gpio6: i2c4_gpio6 {
720 i2c4_gpio8: i2c4_gpio8 {
732 i2c5_gpio10: i2c5_gpio10 {
744 i2c5_gpio12: i2c5_gpio12 {
756 i2c6_gpio0: i2c6_gpio0 {
768 i2c6_gpio22: i2c6_gpio22 {
780 i2c_slave_gpio8: i2c_slave_gpio8 {
790 jtag_gpio48: jtag_gpio48 {
802 mii_gpio28: mii_gpio28 {
811 mii_gpio36: mii_gpio36 {
821 pcm_gpio50: pcm_gpio50 {
831 pwm0_0_gpio12: pwm0_0_gpio12 {
838 pwm0_0_gpio18: pwm0_0_gpio18 {
845 pwm1_0_gpio40: pwm1_0_gpio40 {
852 pwm0_1_gpio13: pwm0_1_gpio13 {
859 pwm0_1_gpio19: pwm0_1_gpio19 {
866 pwm1_1_gpio41: pwm1_1_gpio41 {
873 pwm0_1_gpio45: pwm0_1_gpio45 {
880 pwm0_0_gpio52: pwm0_0_gpio52 {
887 pwm0_1_gpio53: pwm0_1_gpio53 {
895 rgmii_gpio35: rgmii_gpio35 {
905 rgmii_irq_gpio34: rgmii_irq_gpio34 {
911 rgmii_irq_gpio39: rgmii_irq_gpio39 {
917 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
924 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
932 spi0_gpio46: spi0_gpio46 {
941 spi2_gpio46: spi2_gpio46 {
951 spi3_gpio0: spi3_gpio0 {
960 spi4_gpio4: spi4_gpio4 {
969 spi5_gpio12: spi5_gpio12 {
978 spi6_gpio18: spi6_gpio18 {
988 uart2_gpio0: uart2_gpio0 {
1000 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
1012 uart3_gpio4: uart3_gpio4 {
1024 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
1036 uart4_gpio8: uart4_gpio8 {
1048 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
1060 uart5_gpio12: uart5_gpio12 {
1072 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
1087 #address-cells = <2>;
1092 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
1093 * that's not good enough for the BCM2711 as some devices can
1094 * only address the lower 1G of memory (ZONE_DMA).
1096 alloc-ranges = <0x0 0x00000000 0x40000000>;
1100 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1101 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1105 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1106 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1114 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1118 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1122 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1126 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1130 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1134 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1141 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1145 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1149 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1153 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1157 compatible = "brcm,bcm2711-vec";
1158 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;