4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
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21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
65 compatible = "arm,cortex-a9";
66 next-level-cache = <&L2>;
67 enable-method = "brcm,bcm-nsp-smp";
68 secondary-boot-reg = <0xffff0fec>;
74 compatible = "arm,cortex-a9-pmu";
75 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
76 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-affinity = <&cpu0>, <&cpu1>;
81 compatible = "simple-bus";
82 ranges = <0x00000000 0x19000000 0x00023000>;
88 compatible = "brcm,nsp-armpll";
90 reg = <0x00000 0x1000>;
94 compatible = "arm,cortex-a9-global-timer";
95 reg = <0x20200 0x100>;
96 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
97 clocks = <&periph_clk>;
101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0x20600 0x20>;
103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_EDGE_RISING)>;
105 clocks = <&periph_clk>;
109 compatible = "arm,cortex-a9-twd-wdt";
110 reg = <0x20620 0x20>;
111 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
112 IRQ_TYPE_LEVEL_HIGH)>;
113 clocks = <&periph_clk>;
116 gic: interrupt-controller@21000 {
117 compatible = "arm,cortex-a9-gic";
118 #interrupt-cells = <3>;
119 #address-cells = <0>;
120 interrupt-controller;
121 reg = <0x21000 0x1000>,
125 L2: cache-controller@22000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x22000 0x1000>;
134 #address-cells = <1>;
140 compatible = "fixed-clock";
141 clock-frequency = <25000000>;
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
152 iprocslow: iprocslow {
154 compatible = "fixed-factor-clock";
155 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
160 periph_clk: periph_clk {
162 compatible = "fixed-factor-clock";
170 compatible = "simple-bus";
171 ranges = <0x00000000 0x18000000 0x0011c40c>;
172 #address-cells = <1>;
176 compatible = "brcm,nsp-gpio-a";
182 interrupt-controller;
183 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
184 gpio-ranges = <&pinctrl 0 0 32>;
188 compatible = "ns16550a";
189 reg = <0x0300 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "ns16550a";
197 reg = <0x0400 0x100>;
198 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
204 compatible = "arm,pl330", "arm,primecell";
205 reg = <0x20000 0x1000>;
206 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&iprocslow>;
216 clock-names = "apb_pclk";
223 compatible = "brcm,sdhci-iproc-cygnus";
224 reg = <0x21000 0x100>;
225 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
232 amac0: ethernet@22000 {
233 compatible = "brcm,nsp-amac";
234 reg = <0x022000 0x1000>,
236 reg-names = "amac_base", "idm_base";
237 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
242 amac1: ethernet@23000 {
243 compatible = "brcm,nsp-amac";
244 reg = <0x023000 0x1000>,
246 reg-names = "amac_base", "idm_base";
247 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
252 amac2: ethernet@24000 {
253 compatible = "brcm,nsp-amac";
254 reg = <0x024000 0x1000>,
256 reg-names = "amac_base", "idm_base";
257 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
262 mailbox: mailbox@25c00 {
263 compatible = "brcm,iproc-fa2-mbox";
264 reg = <0x25c00 0x400>;
265 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
267 brcm,rx-status-len = <32>;
273 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
274 reg = <0x026000 0x600>,
277 reg-names = "nand", "iproc-idm", "iproc-ext";
278 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
280 #address-cells = <1>;
287 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
288 reg = <0x027200 0x184>,
292 reg-names = "mspi", "bspi", "intr_regs",
294 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
301 interrupt-names = "spi_lr_fullness_reached",
302 "spi_lr_session_aborted",
304 "spi_lr_session_done",
308 clocks = <&iprocmed>;
309 clock-names = "iprocmed";
311 #address-cells = <1>;
316 compatible = "generic-xhci";
317 reg = <0x29000 0x1000>;
318 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
320 phy-names = "usb3-phy";
326 compatible = "generic-ehci";
327 reg = <0x2a000 0x100>;
328 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
334 compatible = "generic-ohci";
335 reg = <0x2b000 0x100>;
336 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
342 compatible = "brcm,spum-nsp-crypto";
343 reg = <0x2f000 0x900>;
344 mboxes = <&mailbox 0>;
348 compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
349 reg = <0x30000 0x50>;
353 interrupt-controller;
354 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
358 compatible = "brcm,iproc-pwm";
359 reg = <0x31000 0x28>;
366 compatible = "brcm,bcm-nsp-rng";
367 reg = <0x33000 0x14>;
370 ccbtimer0: timer@34000 {
371 compatible = "arm,sp804", "arm,primecell";
372 reg = <0x34000 0x1000>;
373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&iprocslow>;
376 clock-names = "apb_pclk";
379 ccbtimer1: timer@35000 {
380 compatible = "arm,sp804", "arm,primecell";
381 reg = <0x35000 0x1000>;
382 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&iprocslow>;
385 clock-names = "apb_pclk";
389 compatible = "brcm,nsp-srab";
390 reg = <0x36000 0x1000>,
393 reg-names = "srab", "mux_config", "sgmii";
394 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "link_state_p0",
417 "imp_sleep_timer_p5",
418 "imp_sleep_timer_p7",
419 "imp_sleep_timer_p8";
422 /* ports are defined in board DTS */
426 compatible = "brcm,iproc-i2c";
427 reg = <0x38000 0x50>;
428 #address-cells = <1>;
430 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
431 clock-frequency = <100000>;
437 compatible = "arm,sp805", "arm,primecell";
438 reg = <0x39000 0x1000>;
439 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&iprocslow>, <&iprocslow>;
441 clock-names = "wdog_clk", "apb_pclk";
444 lcpll0: lcpll0@3f100 {
446 compatible = "brcm,nsp-lcpll0";
447 reg = <0x3f100 0x14>;
449 clock-output-names = "lcpll0", "pcie_phy", "sdio",
453 genpll: genpll@3f140 {
455 compatible = "brcm,nsp-genpll";
456 reg = <0x3f140 0x24>;
458 clock-output-names = "genpll", "phy", "ethernetclk",
459 "usbclk", "iprocfast", "sata1",
463 pinctrl: pinctrl@3f1c0 {
464 compatible = "brcm,nsp-pinmux";
465 reg = <0x3f1c0 0x04>,
470 thermal: thermal@3f2c0 {
471 compatible = "brcm,ns-thermal";
472 reg = <0x3f2c0 0x10>;
473 #thermal-sensor-cells = <0>;
476 sata_phy: sata_phy@40100 {
477 compatible = "brcm,iproc-nsp-sata-phy";
478 reg = <0x40100 0x340>;
480 #address-cells = <1>;
483 sata_phy0: sata-phy@0 {
489 sata_phy1: sata-phy@1 {
497 compatible = "brcm,bcm-nsp-ahci";
498 reg-names = "ahci", "top-ctrl";
499 reg = <0x41000 0x1000>, <0x40020 0x1c>;
500 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
501 #address-cells = <1>;
509 phy-names = "sata-phy";
515 phy-names = "sata-phy";
519 usb3_phy: usb3-phy@104000 {
520 compatible = "brcm,ns-bx-usb3-phy";
521 reg = <0x104000 0x1000>,
523 reg-names = "dmp", "ccb-mii";
529 pcie0: pcie@18012000 {
530 compatible = "brcm,iproc-pcie";
531 reg = <0x18012000 0x1000>;
533 #interrupt-cells = <1>;
534 interrupt-map-mask = <0 0 0 0>;
535 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
537 linux,pci-domain = <0>;
539 bus-range = <0x00 0xff>;
541 #address-cells = <3>;
545 /* Note: The HW does not support I/O resources. So,
546 * only the memory resource range is being specified.
548 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
553 msi-parent = <&msi0>;
554 msi0: msi-controller {
555 compatible = "brcm,iproc-msi";
557 interrupt-parent = <&gic>;
558 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
566 pcie1: pcie@18013000 {
567 compatible = "brcm,iproc-pcie";
568 reg = <0x18013000 0x1000>;
570 #interrupt-cells = <1>;
571 interrupt-map-mask = <0 0 0 0>;
572 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
574 linux,pci-domain = <1>;
576 bus-range = <0x00 0xff>;
578 #address-cells = <3>;
582 /* Note: The HW does not support I/O resources. So,
583 * only the memory resource range is being specified.
585 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
590 msi-parent = <&msi1>;
591 msi1: msi-controller {
592 compatible = "brcm,iproc-msi";
594 interrupt-parent = <&gic>;
595 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
603 pcie2: pcie@18014000 {
604 compatible = "brcm,iproc-pcie";
605 reg = <0x18014000 0x1000>;
607 #interrupt-cells = <1>;
608 interrupt-map-mask = <0 0 0 0>;
609 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
611 linux,pci-domain = <2>;
613 bus-range = <0x00 0xff>;
615 #address-cells = <3>;
619 /* Note: The HW does not support I/O resources. So,
620 * only the memory resource range is being specified.
622 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
627 msi-parent = <&msi2>;
628 msi2: msi-controller {
629 compatible = "brcm,iproc-msi";
631 interrupt-parent = <&gic>;
632 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
642 polling-delay-passive = <0>;
643 polling-delay = <1000>;
644 coefficients = <(-556) 418000>;
645 thermal-sensors = <&thermal>;
649 temperature = <125000>;